74ACT299
8 BIT PIPO SHIFT REGISTER
WITH ASYNCHRONOUS CLEAR
■
■
■
■
■
■
■
■
■
HIGH SPEED:
fMAX = 240MHz (TYP.) at VCC = 5V
LOW POWER DISSIPATION:
ICC = 8µA(MAX.) at TA=25°C
COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.), V IL = 0.8V (MAX.)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 299
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74ACT299 is an advanced high-speed CMOS
8-BIT PIPO
SHIFT REGISTER (3-STATE)
fabricated with sub-micron silicon gate and
double-layer metal wiring C2MOS technology.
These devices have four modes (HOLD, SHIFT
LEFT, SHIFT RIGHT and LOAD DATA). Each
mode is chosen by two function select inputs (S0,
S1) as shown in the Truth Table. When one or
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
TSSOP
74ACT299B
74ACT299M
T&R
74ACT299MTR
74ACT299TTR
both enable inputs, (G1, G2) are high, the eight
input/output terminals are in the high-impedance
state; however sequential operation or clearing of
the register is not affected. Clear function is
asynchronousto clock.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
1/13
74ACT299
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
1, 19
2, 3
7, 13, 6, 14, 5, 15, 4, 16
8, 17
9
11
12
18
10
20
S0, S1
G1, G2
A/QA to H/QH
QA’ to QH’
CLEAR
SR
CLOCK
SL
GND
VCC
NAME AND FUNCTION
Mode Select Inputs
3-State Output Enable Inputs (Active LOW)
Parallel Data Inputs or 3-State Parallel Outputs (Bus Driver)
Serial Outputs (Standard Output)
Asyncrhronous Master Reset Input (Active LOW)
Serial Data Shift Right Input
Clock Input (LOW to HIGH, Edge-triggered)
Serial Data Shift Left Input
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
MODE
CLEAR
FUNCTION
SELECTED
INPUTS/OUTPUTS
OUTPUT
CONTROL
SERIAL
CLOCK
A/QA
H/QH
QA’
QH’
Z
L
L
QA0
H
Z
L
L
QH0
QGn
L
L
L
QA0
H
L
L
L
QH0
QGn
L
L
QGn
L
QGn
X
QBn
H
QBn
H
QBn
L
QBn
L
a
h
a
h
S1
S0
G1*
G2*
H
L
X
L
L
H
X
L
L
H
X
L
L
L
L
X
L
L
L
L
H
L
H
L
L
X
SHIFT
LEFT
H
H
L
L
L
H
H
H
L
L
L
L
X
LOAD
H
H
H
X
X
X
X
Z
CLEAR
HOLD
SHIFT
RIGHT
L
L
L
H
H
OUTPUTS
X
X
X
X
SL
SR
X
X
X
X
X
X
X
X
X
H
* : When one or both controls are high, the eight input/output terminals are the high impedance state: howewer sequential operation or cleanig
of the register is not affected.
Z : High Impedance
Qn0 : The level of An before the indicated steady state input conditions were established.
Qnn : The level of Qn before the most recent active transition indicated by OR
a, h : The level of the steadystate inputs A, H, respectively.
X : Don’t Care
2/13
74ACT299
LOGIC DIAGRAM
3/13
74ACT299
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Supply Voltage
Value
Unit
-0.5 to +7
V
VI
DC Input Voltage
-0.5 to VCC + 0.5
V
VO
DC Output Voltage
-0.5 to VCC + 0.5
± 20
V
mA
IIK
DC Input Diode Current
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
± 50
mA
ICC or IGND DC VCC or Ground Current
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
± 400
mA
-65 to +150
°C
300
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Unit
Supply Voltage
4.5 to 5.5
V
VI
Input Voltage
0 to VCC
V
VO
Output Voltage
0 to VCC
V
Top
Operating Temperature
dt/dv
Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1)
1) VIN from 0.8V to 2.0V
4/13
Value
-55 to 125
°C
8
ns/V
74ACT299
DC SPECIFICATIONS
Test Condition
Symbol
Parameter
Value
TA = 25°C
VCC
(V)
Min.
Typ.
2.0
2.0
1.5
1.5
Max.
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
Unit
Max.
VIH
High Level Input
Voltage
4.5
5.5
VO = 0.1 V or
VCC-0.1V
VIL
Low Level Input
Voltage
4.5
5.5
VO = 0.1 V or
VCC-0.1V
VOH
High Level Output
Voltage
4.5
IO=-50 µA
4.4
4.49
4.4
4.4
5.5
IO=-50 µA
5.4
5.49
5.4
5.4
4.5
IO=-24 mA
3.86
3.76
3.7
5.5
IO=-24 mA
4.86
4.76
4.7
4.5
IO=50 µA
0.001
0.1
0.1
0.1
5.5
IO=50 µA
0.001
0.1
0.1
0.1
4.5
IO=24 mA
0.36
0.44
0.5
5.5
IO=24 mA
0.36
0.44
0.5
5.5
VI = VCC or GND
± 0.1
±1
±1
µA
5.5
VI = VIH or VIL
VO = VCC or GND
± 0.5
±5
± 10
µA
1.5
1.6
mA
80
160
µA
VOL
II
IOZ
ICCT
Low Level Output
Voltage
Input Leakage Current
High Impedance
Output Leakege
Current
Max ICC/Input
5.5
VI = VCC - 2.1V
ICC
Quiescent Supply
Current
5.5
VI = VCC or GND
IOLD
Dynamic Output
Current (note 1, 2)
5.5
IOHD
1.5
1.5
2.0
2.0
0.8
0.8
0.6
8
2.0
2.0
0.8
0.8
V
0.8
0.8
V
V
VOLD = 1.65 V max
75
50
mA
VOHD = 3.85 V min
-75
-50
mA
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on trasmission lines with impedances as low as 50Ω
5/13
74ACT299
AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
Test Condition
Symbol
tPLH
tPHL
tPLH
tPHL
tPHL
tPHL
tPZL
tPZH
tPLZ
tPHZ
tW
tW
ts
th
ts
th
tREM
fMAX
Parameter
TA = 25°C
Min.
-40 to 85°C
-55 to 125°C
Typ.
Max.
Min.
Max.
Min.
Max.
Unit
Propagation Delay
Time CLOCK to
Q’A’ Q’H
5.0(*)
6.5
10.5
1.0
15.0
1.0
16.0
ns
Propagation Delay
Time CLOCK to QA
- QH
5.0(*)
6.5
11.4
1.0
15.0
1.0
16.0
ns
Propagation Delay
Time CLEAR to Q’A’
Q’H
5.0(*)
6.4
10.0
1.0
17.5
1.0
18.0
ns
Propagation Delay
Time CLEAR to QA
- QH
5.0(*)
6.6
10.5
1.0
17.5
1.0
18.0
ns
Output Enable
Time
5.0(*)
6.4
11.4
1.0
13.5
1.0
14.5
ns
Output Disable
Time
5.0(*)
6.2
9.6
1.0
13.5
1.0
14.5
ns
CLEAR Pulse
Width, LOW
CLOCK pulse
Width
Setup Time HIGH
or LOW(S0 or S1 to
CK)
Hold Time HIGH or
LOW (S0 or S1 to
CK)
Setup Time HIGH
or LOW
(SR or SL to CK)
Hold Time HIGH or
LOW
(SR or SL to CK)
Recovery Time
CLR to CK
Maximum Clock
Frequency
(*) Voltage range is 5.0V ± 0.5V
6/13
VCC
(V)
Value
5.0(*)
5.0
5.0
5.0
ns
5.0(*)
5.0
5.0
5.0
ns
5.0(*)
6.0
6.5
6.5
ns
5.0(*)
0.0
0.0
0.0
ns
5.0(*)
3.5
3.5
3.5
ns
5.0(*)
2.0
2.0
2.0
ns
5.0(*)
2.0
2.0
2.0
ns
5.0(*)
80
240
80
80
MHz
74ACT299
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
Value
TA = 25°C
VCC
(V)
-55 to 125°C
Min.
Min.
Max.
5.0
4
10
5.0
13
pF
160
pF
Input Capacitance
CI/O
I/O Capacitance
CPD
Power Dissipation
Capacitance (note
1)
5.0
fIN = 10MHz
Max.
Unit
Typ.
CIN
Min.
-40 to 85°C
Max.
10
10
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x f IN + ICC/n (per circuit)
TEST CIRCUIT
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
2VCC
tPZH, tPHZ
Open
CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
7/13
74ACT299
WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
8/13
74ACT299
WAVEFORM 3: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
WAVEFORM 4: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
9/13
74ACT299
Plastic DIP-20 (0.25) MECHANICAL DATA
mm
DIM.
MIN.
a1
0.254
B
1.39
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.010
1.65
0.055
0.065
b
0.45
0.018
b1
0.25
0.010
D
25.4
1.000
E
8.5
0.335
e
2.54
0.100
e3
22.86
0.900
F
7.1
0.280
I
3.93
0.155
L
Z
3.3
0.130
1.34
0.053
P001J
10/13
74ACT299
SO-20 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
A
a1
inch
MAX.
MIN.
TYP.
2.65
0.10
0.104
0.20
a2
MAX.
0.004
0.007
2.45
0.096
b
0.35
0.49
0.013
0.019
b1
0.23
0.32
0.009
0.012
C
0.50
0.020
c1
45 (typ.)
D
12.60
13.00
0.496
0.512
E
10.00
10.65
0.393
0.419
e
1.27
0.050
e3
11.43
0.450
F
7.40
7.60
0.291
0.299
L
0.50
1.27
0.19
0.050
M
S
0.75
0.029
8 (max.)
P013L
11/13
74ACT299
TSSOP20 MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
A
MIN.
TYP.
1.1
0.433
A1
0.05
0.10
0.15
0.002
0.004
0.006
A2
0.85
0.9
0.95
0.335
0.354
0.374
b
0.19
0.30
0.0075
0.0118
c
0.09
0.2
0.0035
0.0079
D
6.4
6.5
6.6
0.252
0.256
0.260
E
6.25
6.4
6.5
0.246
0.252
0.256
E1
4.3
4.4
4.48
0.169
0.173
0.176
e
0.65 BSC
0.0256 BSC
K
0o
4o
8o
0o
4o
8o
L
0.50
0.60
0.70
0.020
0.024
0.028
A
A2
A1
b
K
e
E1
PIN 1 IDENTIFICATION
1
L
E
c
D
12/13
MAX.
74ACT299
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2001 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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13/13
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