74ACT74TTR

74ACT74 DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 250MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), V IL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74ACT74 is an advanced high-speed CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. A signal on the D INPUT is transferred to the Q and Q OUTPUTS during the positive going transition of the clock pulse. DIP SOP TSSOP ORDER CODES PACKAGE TUBE DIP SOP TSSOP 74ACT74B 74ACT74M T&R 74ACT74MTR 74ACT74TTR CLEAR and PRESET are independent of the clock and accomplished by a low setting on the appropriate input. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS April 2001 1/12 74ACT74 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1, 13 1CLR, 2CLR 2, 12 3, 11 1D, 2D 1CK, 2CK 4, 10 1PR, 2PR 5, 9 6, 8 1Q, 2Q 1Q, 2Q 7 14 GND VCC NAME AND FUNCTION Asyncronous Reset Direct Input Data Inputs Clock Input (LOW to HIGH, Edge Triggered) Asyncronous Set - Direct Input True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS OUTPUTS FUNCTION CLR PR D CK Q Q L H L H L L X X X X X X L H H L L H H H L L H H H H H L H H X Qn Qn X : Don’t Care LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/12 CLEAR PRESET NO CHANGE 74ACT74 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 50 mA ± 200 mA VI DC Input Voltage VO DC Output Voltage IIK ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) V -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Value Unit Supply Voltage 4.5 to 5.5 V VI Input Voltage 0 to VCC V VO Output Voltage 0 to VCC V Top Operating Temperature -55 to 125 °C 8 ns/V dt/dv Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) 1) VIN from 0.8V to 2.0V 3/12 74ACT74 DC SPECIFICATIONS Test Condition Symbol Parameter Value TA = 25°C VCC (V) Min. Typ. 2.0 2.0 1.5 1.5 Max. -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. VIH High Level Input Voltage 4.5 5.5 VO = 0.1 V or VCC-0.1V VIL Low Level Input Voltage 4.5 5.5 VO = 0.1 V or VCC-0.1V VOH High Level Output Voltage 4.5 IO=-50 µA 4.4 4.49 5.5 IO=-50 µA 5.4 5.49 4.5 IO=-24 mA 3.86 5.5 IO=-24 mA 4.86 4.5 IO=50 µA 0.001 0.1 0.1 0.1 5.5 IO=50 µA 0.001 0.1 0.1 0.1 4.5 IO=24 mA 0.36 0.44 0.5 5.5 IO=24 mA 0.36 0.44 0.5 5.5 VI = VCC or GND ± 0.1 ±1 ±1 µA 1.5 1.6 mA 40 40 µA VOLD = 1.65 V max 75 50 mA VOHD = 3.85 V min -75 -50 mA VOL II ICCT Low Level Output Voltage Input Leakage Current Max ICC/Input 5.5 VI = VCC - 2.1V ICC Quiescent Supply Current 5.5 VI = VCC or GND IOLD Dynamic Output Current (note 1, 2) 5.5 IOHD 2.0 2.0 1.5 1.5 0.8 0.8 2.0 2.0 0.8 0.8 4.4 4.4 5.4 5.4 3.76 3.7 4.76 0.6 4 V 0.8 0.8 V 4.7 V 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) Test Condition Symbol Parameter tPLH tPHL Propagation Delay Time CK to Q or Q tPLH tPHL Propagation Delay Time PR or CLR to Q or Q tW Pulse Width HIGH or LOW, CK or PR or CLR Setup Time D to CK ts HIGH or LOW th Hold Time D to CK HIGH or LOW tREM Removal Tim| PR or CLR to CK fMAX Maximum Clock Frequency (*) Voltage range is 5.0V ± 0.5V 4/12 VCC (V) Value TA = 25°C -55 to 125°C Min. Min. Max. 5.0(*) 5.0 10.0 11.0 11.0 ns 5.0(*) 5.0 10.0 11.0 11.0 ns 5.0(*) 1.5 5.0 6.0 6.0 ns 5.0(*) 0.5 3.0 3.5 3.5 ns 5.0(*) -0.5 1.0 1.0 1.0 ns 5.0(*) -0.7 1.0 1.0 1.0 ns 100 250 85 Max. Unit Typ. 5.0(*) Min. -40 to 85°C 85 Max. MHz 74ACT74 CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter TA = 25°C VCC (V) CIN Input Capacitance 5.0 CPD Power Dissipation Capacitance (note 1) 5.0 Value Min. fIN = 10MHz Typ. Max. -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. 3 pF 43 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per Flip-Flop) TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) 5/12 74ACT74 WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/12 74ACT74 WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 7/12 74ACT74 WAVEFORM 3: RECOVERY TIMES (f=1MHz; 50% duty cycle) WAVEFORM 4: PULSE WIDTH 8/12 74ACT74 Plastic DIP-14 MECHANICAL DATA mm DIM. MIN. a1 0.51 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 F 7.1 0.280 I 5.1 0.201 L Z 3.3 1.27 0.130 2.54 0.050 0.100 P001A 9/12 74ACT74 SO-14 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45 (typ.) D 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.68 0.026 8 (max.) P013G 10/12 74ACT74 TSSOP14 MECHANICAL DATA mm DIM. MIN. inch TYP. A MAX. MIN. TYP. MAX. 1.1 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.20 0.0035 0.0079 D 4.9 5 5.1 0.193 0.197 0.201 E 6.25 6.4 6.5 0.246 0.252 0.256 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 BSC 0.0256 BSC K 0o 4o 8o 0o 4o 8o L 0.50 0.60 0.70 0.020 0.024 0.028 A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 11/12 74ACT74 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom © http://www.st.com 12/12