74LVC161284
LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER
■
HIGH SPEED: tPD = 9ns (MAX.) at VCC = 3V
■
LOW POWER DISSIPATION:
ICC=20µA (MAX) at VCC=3.6V TA=85°C
■
TTL COMPATIBLE INPUTS
VIH=2V (MIN) VIL=0.8(MAX)
■
OPERATING VOLTAGE RANGE:
VCC(OPR) = 3.0V to 3.6V
■
A PORT HAVE STANDARD 4mA TOTEM
POLE OUTPUT
■
B PORT HIGH DRIVE SOURCE/SINK
CAPABILITY OF 14mA
■
SUPPORT IEEE STD 1284-I (LEVEL 1 TYPE)
AND IEEE STD 1284-II (LEVEL 2 TYPE) FOR
BIDIRECTIONAL PARALLEL
COMMUNICATIONS BETWEEN PERSONAL
COMPUTER ANT PRINTING PERIPHERALS
)
s
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ct
TSSOP
)
(s
■
TRANSLATION CAPABILITY ALLOW
OUTPUTS ON CABLE SIDE TO INTERFACE
WITH 5V SIGNAL
■
PULL-UP RESISTOR INTEGRATED ON ALL
OPEN-DRAIN OUTPUT ELIMINATE THE
NEED FOR DISCRETE RESISTOR
■
REPLACE THE FUNCTION OF TWO
74LVC1284 DEVICES
PACKAGE
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TSSOP
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ORDER CODES
TUBE
T&R
74LVC161284TTR
PIN CONNECTION
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DESCRIPTION
The 74LVC161284 contains eight high speed non
inverting bidirectional buffers and eleven control/
status non-inverting buffers with open drain
outputs fabricated in silicon gate C2MOS
technology. It’s intended to provide a standard
signaling method for a bi-direction parallel
peripheral in an Extended Capabilities Port Mode
(ECP). The HD (Active HIGH) input pin enables
the Cable port to switch from Open Drain to a high
drive totem pole output, capable of sourcing 14mA
on all thirteen buffer and 84mA on PERI LOGIC
OUTPUT buffer. The DIR input determines the
direction of data flow on the bidirectional buffers.
DIR (Active HIGH) enables data flow from A port
to B port. DIR (Active LOW) enables data flow
from B port to A port. It is available in the
commercial temperature range.
May 2003
1/11
74LVC161284
LOGIC DIAGRAM
)
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NOTE A:
NOTE B:
)
(s
t
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u
The PMOS transistors prevent backdriving current from the signal pins to VCC/CABLE when VCC/CABLE is open or at GND. The
PMOS transistor is turned off when the associated driver is in the low state.
The PMOS transistor prevents backdriving current from the signal pins to VCC/CABLE when VCC/CABLE is open or at GND.
PIN DESCRIPTION
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PIN No
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1
2, 3, 4, 5, 6
8, 9, 11, 12, 13, 14, 16, 17
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SYMBOL
NAME AND FUNCTION
HD
A9 to A13
A1 to A8
PLI
High Drive Enable Input
Side A Input
Side A Input or Output
Side A Output
24
A14 to A17
HLO
25
HLI
29, 28, 27, 26
C14 to C17
PLO
19
20, 21, 22, 23
30
41, 40, 38, 37, 36, 35, 33, 32
47, 46, 45, 44, 43
48
10, 15, 34, 39
2/11
s
b
O
Peripheral Logic Input
Host Logic Output
Host Logic Input
Side Cable Output
Peripheral Logic Output
7, 18
B1 to B8
Y9 to Y13
DIR
GND
VCC
Side Cable Input or Output
Side Cable Output
Direction Control Input
Ground (0V)
Positive Supply Voltage
31, 42
VCC/CABLE
Cable Power Supply
74LVC161284
TRUTH TABLE
INPUT
OUTPUT
DIR
HD
L
L
L
H
H
L
H
H
OUTPUT
Y9-Y13 and PLO Open
Drain
Y9-Y13 and PLO Totem
Pole
B1-B8 Y9-Y13 and PLO
Open Drain
B1-B8 Y9-Y13 and PLO
Totem Pole
B1-B8 Data to A1-A8
A9-A13 Data to Y9-Y13
C14-C17 Data to C14-C17
A1-A8 Data to B1-B8
A9-A13 Data to Y9-Y13
C14-C17 Data to C14-C17
)
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(
ct
ABSOLUTE MAXIMUM RATINGS
Symbol
u
d
o
Parameter
Value
Supply Voltage
VCC
-0.5 to +4.6
Cable Supply Voltage (must be ≥ VCC)
VCCcable
VIB
DC Input Voltage A1-A13, PLIN, DIR, HDIN
DC Input Voltage B1-B8, C14-C17, HLIN
VIBp
DC Input Voltage B1-B8, C14-C17, HLIN (40ns transient)
VIA
so
VOA
DC Output Voltage A1-A8, A14-A17, HLIN
VOB
DC Output Voltage B1-B8, Y9-Y13, PLIN
VOBp
DC Output Voltage B1-B8, Y9-Y13, PLIN (40ns transient)
IIK
DC Input Diode Current DIR, HD A9-A13, PLIN C14-C17
IOK
DC Output Diode Current
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DC Output Current
IO
)-
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TL
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A1-A8, A14-A17, HLIN
B1-B8, Y9-Y13, PLIN
A1-A8, HLIN
-0.5 to +7.0
V
V
-0.5 to +5.5
V
-2 to +7
V
-0.5 to +VCC + 0.5
V
-0.5 to +5.5
V
-2 to +7
V
- 20
mA
± 50
mA
- 50
± 25
± 50
PLO = HIGH
-50
Storage Temperature
Lead Temperature (10 sec)
V
-0.5 to +VCC + 0.5
B1-B8, Y9-Y13
PLO = LOW
ICC or IGND DC VCC or Ground Current per Supply Pin
Tstg
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Pr
Unit
mA
84
± 200
mA
-65 to +150
°C
300
°C
Absolute Maximum Rating are those value beyond which damage to the device may occur. Functional operation under these condition is not
implied
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VCCcable
Parameter
Value
Unit
Supply Voltage
3.0 to 3.6
V
Cable Supply Voltage
3.0 to 5.5
V
VI
Input Voltage
0 to VCC
V
VO
Open Drain Output Voltage
Top
Operating Temperature
0 to 5.5
V
-40 to 85
°C
3/11
74LVC161284
DC SPECIFICATIONS
Test Condition
Symbol
Parameter
High Level
Input Voltage
VIH
Low Level
Input Voltage
VIL
VCC
(V)
II
Input Current
Cn
HLIN
O
Vhys
ZO
RP
4/11
Power Off
Leakage
Current
Input
Hysteresis
Output
Impedance
Pull-up
Resistance
3.0
to
5.5
V
2.6
0.8
Cn
HLIN
0.8
V
)
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1.6
IO=-50µA
2.8
3.0
IO=-4mA
2.4
3.0
3.0
3.0
Bn, Yn
3.0
3.0
IO=-14mA
Bn, Yn
3.0
4.5
IO=-14mA
PL
3.15
3.15
IO=-500µA
3.0
3.0
IO=50µA
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0.77
3.0
IO=84mA
0.95
3.0
PL
3.0
PL
)-
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4.5
V
4.5
IO=84mA
0.90
3.6
VI = VCC
50
µA
3.6
3.6
VI=GND (Pull-up res)
-3.5
mA
3.6
5.0
VI = VCC or GND
±1
µA
3.6
5.0
VI = VCC IO=0
0.8
VI=GND (12xPull-up)
45
3.0
A1-A8
0.2
IO=14mA
Bn, Yn
Bn
3.1
0.4
3.0
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V
0.8
3.0
3.0
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2.0
2.23
IO=14mA
3.0
Cn
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IO=4mA
Bn, Yn
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P
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High
Impedance
Output
Leakage
Current
t
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bs
IOFF
3.0
to
3.6
An, Bn, PLIN, DIR, HD
Quiescent Supply Current
IOZ
Max.
2.3
All input except B or C
ICC
Min.
Unit
2
Low Level
An, HL
Output Voltage
VOL
-40 to 85 °C
VCCcable
(V)
An, Bn, PLIN, DIR, HD
High Level
An, HL
Output Voltage
VOH
Value
3.6
mA
3.6
5.0
VO = VCC
20
µA
3.6
3.6
VO=GND (Pull-up res)
-3.5
mA
3.6
5.0
VO = VCC or GND
± 20
µA
Open Drain Y Output
3.6
3.6
VO=GND (Pull-up res)
-3.5
mA
B, Y output (to GND)
0
5.0
VI or VO = 0 to 7V
100
µA
B, Y output (to VCC)
0
5.0
VI or VO = 0 to 7V
10
µA
An, Bn, PLIN, DIR, HD
3.3
5.0
0.4
Cn
HLIN
3.3
5.0
0.8
3.3
5.0
0.2
B1-B8, Y9-Y13
3.3
5.0
VB = VOH
30
55
Ω
B1-B8, Y9-Y13,
C14-C17
3.3
5.0
VB = VOH
1150
1650
Ω
V
74LVC161284
AC ELECTRICAL CHARACTERISTICS
Test Condition
Symbol
tPLH
tPHL
Parameter
Propagation
Delay Time
VCC
(V)
A1-A8 to B1-B8,
A9-A13 to Y9-Y13
B1-B8 to A1-A8,
C14-C17 to A14-A17
PLIN to PLOUT
3.0
to
3.6
-40 to 85 °C
VCCcable
(V)
3.0
to
5.5
HLIN to HLOUT
tPZH
tPZL
Enable Delay
Time
DIR to A
HD to Bn, Y9-Y13
tPLZ
tPHZ
Disable Delay
Time
DIR to A
tr tf
Rise and Fall Time
B1-B8, Y9-Y13 Open Drain
DIR to A
HD to Bn, Y9-Y13
tOSLH
tOSHL
Output To Output Skew Time (note1, 2)
Value
3.0
to
3.6
3.0
to
5.5
3.0
to
3.6
3.0
to
5.5
3.0
to
3.6
3.0
to
3.6
3.0
to
5.5
3.0
to
5.5
Unit
Min.
Max.
RL=500Ω CL=50pF
1
7.5
ns
RL=500Ω CL=50pF
1
9.0
ns
RL=500Ω CL=50pF
1
7.0
ns
RL=500Ω CL=50pF
1
11.0
ns
RL=500Ω CL=50pF
1
12
ns
RL=500Ω CL=50pF
1
8.5
ct
ns
8.5
ns
8.5
ns
1
8.5
ns
1
120
ns
1
2
ns
du
RL=500Ω CL=50pF
RL=500Ω CL=50pF
1
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P
RL=500Ω CL=50pF
ete
1
RL=500Ω CL=50pF
ol
RPULL-UP=500Ω
CL=50pF
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(s)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device
switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|
2) Parameter guaranteed by design
CAPACITANCE CHARACTERISTICS
od
Symbol
Parameter
e
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CIN
so
CI/O
b
O
t
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Pr
Control Input Capacitance
(HD, DIR, A9-A13, C14-C17,
PLIN, HLIN)
I/O Pin Capacitance
)
(s
Test Condition
Value
TA = 25 °C
Unit
VCC
(V)
VCC/CABLE
(V)
Open
Open
4
pF
3.3
5.0
6
pF
Min.
Typ.
Max.
5/11
74LVC161284
TEST CIRCUIT
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TEST
let
tPHL (A1-A8 to B1-B8, A9-A13 to Y9-Y13, PLHIN to PLH) (see waveform 1)
tPLH (A1-A8 to B1-B8, A9-A13 to Y9-Y13, PLHIN to PLH, HD to B1-B8, Y9-Y13, PLH)
(see waveform 1)
tPHL, tPLH (B1-B8 to A1-A8, C14-C17 to A14-A17, HLHIN to HLH) (see waveform 2)
tr, tf (A1-A8 to B1-B8, A9-A13 to Y9-Y13) (see waveform 1)
O
)
tPLZ (DIR to A1-A8) (see waveform 4)
tPHZ (DIR to A1-A8) (see waveform 4)
s
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tPZL (DIR to A1-A8) (see waveform 3)
tPZH (DIR to A1-A8) (see waveform 3)
u
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tPLZ (DIR to B1-B8) (see waveform 4)
Pr
o
s
b
tPHZ (DIR to B1-B8) (see waveform 4)
S1
S2
S3
Open
VCC
VCC
Open
GND
GND
Open
GND
GND
Open
VCC
GND
6V
GND
GND
Open
GND
GND
1.4V
GND
GND
4.4V
GND
GND
6V
GND
GND
Open
GND
GND
CL = 50 pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
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WAVEFORM 1: PROPAGATION DELAY INPUT An TO OUTPUT (f=1MHz; 50% duty cycle)
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6/11
74LVC161284
WAVEFORM 2: PROPAGATION DELAY INPUT Bn TO OUTPUT (f=1MHz; 50% duty cycle)
)
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VMO = 50%VCC
WAVEFORM 3: DATA TO OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
)
(s
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7/11
74LVC161284
WAVEFORM 4: DIR TO OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
)
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(s
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8/11
74LVC161284
TSSOP48 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
A
MIN.
TYP.
MAX.
1.2
A1
0.05
0.047
0.15
A2
0.002
0.006
0.9
0.035
b
0.17
0.27
0.0067
c
0.09
0.20
0.0035
D
12.4
12.6
0.488
E
E1
0˚
L
0.50
0.236
bs
let
o
s
b
O
)
8˚
ro
0.0079
0.496
s
(
t
c
0.75
0.244
0.0197 BSC
0˚
8˚
0.020
0.030
u
d
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P
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A
t
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6.2
0.5 BSC
K
du
0.318 BSC
6.0
e
0.011
P
e
8.1 BSC
)
s
(
ct
A2
A1
b
K
e
L
E
c
D
O
E1
PIN 1 IDENTIFICATION
1
7065588C
9/11
74LVC161284
Tape & Reel TSSOP48 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
A
TYP.
MAX.
12.992
C
12.8
13.2
D
20.2
0.795
N
60
2.362
0.504
0.519
)
s
(
ct
30.4
1.197
Ao
8.7
8.9
0.343
Bo
13.1
13.3
0.516
Ko
1.5
1.7
0.059
Po
3.9
4.1
P
11.9
12.1
)
(s
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10/11
MIN.
330
T
s
b
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MAX.
let
0.153
so
b
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P
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0.468
ro
du
0.350
0.524
0.067
0.161
0.476
74LVC161284
)
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(s
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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© 2003 STMicroelectronics - Printed in Italy - All Rights Reserved
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11/11