74LVC573AMTR

74LVC573A OCTAL D-TYPE LATCH HIGH PERFORMANCE ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 5V TOLERANT INPUTS HIGH SPEED: tPD = 6.8ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 1.65V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V DESCRIPTION The 74LVC573A is a low voltage CMOS OCTAL D-TYPE LATCH fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q PIN CONNECTION AND IEC LOGIC SYMBOLS February 2002 SOP TSSOP ORDER CODES PACKAGE TUBE T&R SOP TSSOP 74LVC573AM 74LVC573AMTR 74LVC573ATTR outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components. It has more speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 1/10 74LVC573A INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 OE 2, 3, 4, 5, 6, 7, 8, 9 12, 13, 14, 15, 16, 17, 18, 19 11 10 20 TRUTH TABLE NAME AND FUNCTION D0 to D7 3 State Output Enable Input (Active LOW) Data Inputs Q0 to Q7 3-State Latch Outputs LE GND VCC Latch Enable Input Ground (0V) Positive Supply Voltage INPUTS OUTPUT OE LE D Q H X X L L X L L H H L H Z NO CHANGE L H X : Don’t Care Z : High Impedance ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Value Unit Supply Voltage -0.5 to +7.0 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage (VCC = 0V) -0.5 to +7.0 V VO DC Output Voltage (High or Low State) (note 1) IIK DC Input Diode Current IOK IO -0.5 to VCC + 0.5 V - 50 mA DC Output Diode Current (note 2) - 50 mA DC Output Current ± 50 mA ICC or IGND DC VCC or Ground Current per Supply Pin Tstg Storage Temperature TL Lead Temperature (10 sec) ± 100 mA -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) IO absolute maximum rating must be observed 2) VO < GND 2/10 74LVC573A RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Value Supply Voltage (note 1) Unit 1.65 to 3.6 V 0 to 5.5 V VI Input Voltage VO Output Voltage (VCC = 0V) 0 to 5.5 V VO Output Voltage (High or Low State) 0 to VCC V IOH, IOL High or Low Level Output Current (VCC = 3.0 to 3.6V) ± 24 mA IOH, IOL High or Low Level Output Current (VCC = 2.7 to 3.0V) ± 12 mA IOH, IOL High or Low Level Output Current (VCC = 2.3 to 2.7V) ±8 mA IOH, IOL High or Low Level Output Current (VCC = 1.65 to 2.3V) ±4 mA Top dt/dv Operating Temperature Input Rise and Fall Time (note 2) -55 to 125 °C 0 to 10 ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V at VCC = 3.0V DC SPECIFICATIONS Test Condition Symbol VIH VIL VOH VOL II Ioff IOZ ICC ∆ICC Parameter Value -40 to 85 °C -55 to 125 °C Unit VCC (V) Min. High Level Input Voltage 1.65 to 1.95 0.65VCC 0.65VCC 2.3 to 2.7 2.7 to 3.6 1.7 2 1.7 2 Low Level Input Voltage 1.65 to 1.95 0.35VCC 0.35VCC 2.3 to 2.7 2.7 to 3.6 0.7 0.8 0.7 0.8 High Level Output Voltage 1.65 to 3.6 IO=-100 µA VCC-0.2 VCC-0.2 1.65 IO=-4 mA 1.2 1.2 2.3 IO=-8 mA 1.7 1.7 2.7 IO=-12 mA 2.2 2.2 3.0 IO=-18 mA 2.4 2.4 3.0 IO=-24 mA 2.2 2.2 1.65 to 3.6 IO=100 µA 0.2 0.2 1.65 IO=4 mA 0.45 0.45 2.3 IO=8 mA 0.7 0.7 2.7 IO=12 mA 0.4 0.4 3.0 IO=24 mA 0.55 0.55 3.6 VI = 0 to 5.5V ±5 ±5 µA 0 VI or VO = 5.5V 10 10 µA 3.6 VI = VIH orVIL VO = 0 to 5.5V ±5 ±5 µA VI = VCC or GND 10 10 VI or VO = 3.6 to 5.5V VIH = VCC-0.6V ± 10 ± 10 500 500 Low Level Output Voltage Input Leakage Current Power Off Leakage Current High Impedance Output Leakage Current Quiescent Supply Current ICC incr. per Input 3.6 2.7 to 3.6 Max. Min. Max. V V V V µA µA 3/10 74LVC573A DYNAMIC SWITCHING CHARACTERISTICS Test Condition Symbol VOLP VOLV Parameter Value TA = 25 °C VCC (V) Dynamic Low Level Quiet Output (note 1) Min. Typ. Max. 0.8 CL = 50pF VIL = 0V, VIH = 3.3V 3.3 Unit V -0.8 1) Number of output defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state. AC ELECTRICAL CHARACTERISTICS Test Condition Symbol tPLH tPHL tPLH tPHL tPZL tPZH tPLZ tPHZ tW ts th tOSLH tOSHL Parameter Propagation Delay Time D to Q VCC (V) 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 Propagation Delay 1.65 to 1.95 Time LE to Q 2.3 to 2.7 2.7 3.0 to 3.6 Output Enable Time 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 Output Disable Time 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 LE Pulse Width 1.65 to 1.95 HIGH 2.3 to 2.7 2.7 3.0 to 3.6 Setup Time D to LE, 1.65 to 1.95 (HIGH to LOW) 2.3 to 2.7 2.7 3.0 to 3.6 Hold Time LE (HIGH 1.65 to 1.95 to LOW) to D 2.3 to 2.7 2.7 3.0 to 3.6 Output To Output 2.7 to 3.6 Skew Time (note1, 2) Value CL (pF) RL (Ω) ts = tr (ns) 30 30 50 50 30 30 50 50 30 30 50 50 30 30 50 50 30 30 50 50 30 30 50 50 30 30 50 50 1000 500 500 500 1000 500 500 500 1000 500 500 500 1000 500 500 500 1000 500 500 500 1000 500 500 500 1000 500 500 500 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 -40 to 85 °C Min. 1.5 1 1.5 1 1 1 2 2 TBD TBD 3.3 3.3 TBD TBD 2 2 TBD TBD 1.5 1.5 Max. TBD TBD 7.8 6.8 TBD TBD 7.8 6.8 TBD TBD 8.7 7.7 TBD TBD 7.6 7.0 1 -55 to 125 °C Min. 1.5 1 1.5 1 1 1 2 2 TBD TBD 3.3 3.3 TDB TBD 2 2 TBD TBD 1.5 1.5 Unit Max. TBD TBD 9.4 8.2 TBD TBD 9.4 8.2 TBD TBD 10.4 9.2 TBD TBD 9.1 8.4 ns ns ns ns ns ns ns 1 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - t PLHn|, tOSHL = | tPHLm - tPHLn| 2) Parameter guaranteed by design 4/10 74LVC573A CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance (note 1) Value TA = 25 °C VCC (V) Min. 1.8 2.5 3.3 fIN = 10MHz Typ. Unit Max. 4 pF 28 30 34 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x f IN + ICC/n (per circuit) TEST CIRCUIT RT = ZOUT of pulse generator (typically 50Ω) TEST CIRCUIT AND WAVEFORM SYMBOL VALUE VCC Symbol CL 1.65 to 1.95V 2.3 to 2.7V 2.7V 3.0 to 3.6V 30pF 30pF 50pF 50pF R L = R1 1000Ω 500Ω 500Ω 500Ω VS 2 x VCC 2 x VCC 6V 7V VIH VCC VCC 2.7V 3.0V VM VCC/2 VCC/2 1.5V 1.5V VOH VCC VCC 3.0V 3.5V VX VOL + 0.15V VOL + 0.15V VOL + 0.3V VOL + 0.3V VY VOH - 0.15V VOH - 0.15V VOH - 0.3V VOH - 0.3V tr = tr