74LVQ245T

® 74LVQ245 LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER (3-STATE) s s s s s s s s s s s HIGH SPEED: tPD = 6 ns (TYP.) at VCC = 3.3V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 5 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.5V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12 mA (MIN) PCI BUS LEVELS GUARANTEED AT 24mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V (1.2VData Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 245 IMPROVED LATCH-UP IMMUNITY M (Micro Package) T (TSSOP Package) ORDER CODES : 74LVQ245M 74LVQ245T This IC is intended for two-way asynchronous communication between data buses; the direction of data trasmission is determined by DIR input. The enable input G can be used to disable the device so that the buses are effectively isolated. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. IT IS PROHIBITED TO APPLY A SIGNAL TO A TERMINAL WHEN IT IS IN OUTPUT MODE AND WHEN A BUS TERMINAL IS FLOATING (HIGH IMPEDANCE STATE) IT IS REQUESTED TO FIX THE INPUT LEVEL BY MEANS OF EXTERNAL PULL DOWN OR PULL UP RESISTOR. DESCRIPTION The LVQ245 is a low voltage CMOS OCTAL BUS TRANSCEIVER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. It has better speed performance at 3.3V than 5V LSTTL family combined with the true CMOS low power consumption. PIN CONNECTION AND IEC LOGIC SYMBOLS March 1999 1/8 74LVQ245 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2, 3, 4, 5, 6, 7, 8, 9 18, 17, 16, 15, 14, 13, 12, 11 19 10 20 SYMBOL DIR A1 to A8 B1 to B8 NAME AND FUNCT ION Directional Control Data Inputs/Outputs Data Inputs/Outputs G GND VCC Output Enable Input Ground (0V) Positive Supply Voltage TRUTH TABLE INPUT G L L H X:”H” or ”L” Z: High impedance F UNCTION DIR L H X A BUS OUTPUT INPUT Z B BUS INPUT OUTPUT Z OUT PUT A=B B=A Z ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VI/O IIK IOK IO Tstg TL Supply Voltage DC Input Voltage (DIR, G) DC Bus I/O Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 50 ± 400 -65 to +150 300 Unit V V V mA mA mA mA o o ICC or IGND DC VCC or Ground Current C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VI/O Top tr, tf Input Voltage (DIR, G) Bus I/O Voltage Operating Temperature: Input Rise and Fall Time (VCC = 3V) (note 2) Parameter Supply Voltage (note 1) Valu e 2 to 3.6 0 to VCC 0 to VCC -40 to +85 0 to 10 Unit V V V o C ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V 2/8 74LVQ245 DC SPECIFICATIONS Symb ol Parameter V CC (V) VIH VIL VOH High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current 3 State Output Leakage Current Quiescent Supply Current Dynamic Output Current (note 1, 2) 3.0 to 3.6 3.0 VO = 0.1 V or VCC - 0.1 V VI = V IH or V IL VI(*) = VIH or VIL (* ) Test Co nditions Min. 2.0 T yp. Valu e T A = 25 oC Max. 0.8 2.9 2.58 0.002 0 0.1 0.36 ±0.1 ±0.3 4 36 -25 2.99 2.9 2.48 2.2 0.1 0.44 0.55 ±1 ±3 40 -40 to 85 o C Min. 2.0 0.8 Max. Un it V V V I O =-50 µ A IO=-12 mA IO=-24 mA IO=50 µA IO=12 mA IO=24 mA VOL 3.0 V µA µA µA mA mA II IOZ ICC IOLD IOHD 3.6 3.6 3.6 3.6 VI = VCC or GND VI = VIH or VIL VO = VCC or GND VI = VCC or GND VOLD = 0.8 V max VOHD = 2 V min 1) Maximum test duration 2ms, one output loaded attime 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75 Ω. (*) All outputs loaded. DYNAMIC SWITCHING CHARACTERISTICS Symb ol Parameter V CC (V) VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 3.3 -0.8 3.3 3.3 C L = 50 pF 0.8 Test Co nditions Min. T yp. 0.5 -0.5 2 V Valu e T A = 25 oC Max. 0.8 -40 to 85 o C Min. Max. Un it 1) Worst case package 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND 3) max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD). f=1MHz 3/8 74LVQ245 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns) Symb ol Parameter V CC (V) tPLH tPHL tPZL tPZH tPLZ tPHZ tOSLH tOSHL Propagation Delay Time Output Enable Time Output Disable Time Output to Output Skew Time (note 1, 2) 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3(*) T est Con ditio n Valu e T A = 25 oC -40 to 85 o C Min. T yp. Max. Min. Max. 7.5 14.0 15.0 6.0 9.5 7.5 10 7.5 0.5 0.5 10.0 18.0 13.0 20.0 14.5 1.0 1.0 10.5 19.0 13.5 21.0 15.0 1.5 1.5 Un it ns ns ns ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tpHLn|) 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V CAPACITIVE CHARACTERISTICS Symb ol Parameter V CC (V) C IN C i/o CPD Input Capacitance Input/Output Capacitance Power Dissipation Capacitance (note 1) 3.3 3.3 3.3 Test Co nditions Min. T yp. 5 10 16 Valu e T A = 25 oC Max. -40 to 85 o C Min. Max. pF pF pF Un it 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/8(per circuit) TEST CIRCUIT T EST tPLH , tPHL tPZL , tPLZ tPZH , tPHZ CL = 50 pF or equivalent (includes jigand probe capacitance) RL = R1 = 500Ω orequivalent RT = ZOUT of pulse generator (typically 50Ω) SW IT CH Open 2VCC Open 4/8 74LVQ245 WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 5/8 74LVQ245 SO-20 MECHANICAL DATA DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.40 0.50 12.60 10.00 1.27 11.43 7.60 1.27 0.75 8 (max.) 0.291 0.19 13.00 10.65 0.35 0.23 0.50 45 (typ.) 0.496 0.393 0.050 0.450 0.299 0.050 0.029 0.512 0.419 0.10 mm TYP. MAX. 2.65 0.20 2.45 0.49 0.32 0.013 0.009 0.020 0.004 MIN. inch TYP. MAX. 0.104 0.007 0.096 0.019 0.012 P013L 6/8 74LVQ245 TSSOP20 MECHANICAL DATA mm MIN. A A1 A2 b c D E E1 e K L 0o 0.50 0.05 0.85 0.19 0.09 6.4 6.25 4.3 6.5 6.4 4.4 0.65 BSC 4o 0.60 8o 0.70 0o 0.020 0.10 0.9 TYP. MAX. 1.1 0.15 0.95 0.30 0.2 6.6 6.5 4.48 0.002 0.335 0.0075 0.0035 0.252 0.246 0.169 0.256 0.252 0.173 0.0256 BSC 4o 0.024 8o 0.028 0.004 0.354 MIN. inch TYP. MAX. 0.433 0.006 0.374 0.0118 0.0079 0.260 0.256 0.176 DIM. A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 7/8 74LVQ245 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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