74LVQ573

74LVQ573 LOW VOLTAGE CMOS OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING s s s s s s s s s s s HIGH SPEED: tPD = 5.8 ns (TYP.) at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.5V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573 IMPROVED LATCH-UP IMMUNITY SOP TSSOP Table 1: Order Codes PACKAGE SOP TSSOP T&R 74LVQ573MTR 74LVQ573TTR DESCRIPTION The 74LVQ573 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). Figure 1: Pin Connection And IEC Logic Symbols While the LE input is held at a high level, the Q outputs will follow the data input precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. In order to enhance PC board layout, the 74LVQ573 offers a pinout having inputs and outputs on opposite side of the package. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. July 2004 Rev. 5 1/13 74LVQ573 Figure 2: Input And Output Equivalent Circuit Table 2: Pin Description PIN N° 1 2, 3, 4, 5, 6, 7, 8, 9 12, 13, 14, 15, 16, 17, 18, 19 11 10 20 SYMBOL OE D0 to D7 Q0 to Q7 NAME AND FUNCTION 3 State Output Enable Input (Active LOW) Data Inputs 3-State Latch Outputs LE GND VCC Latch Enable Input Ground (0V) Positive Supply Voltage Table 3: Truth Table INPUTS OE H L L L LE X L H H D X X L H OUTPUT Q Z NO CHANGE* L H X : Don’t Care Z : High Impedance * : Q outputs are latched at the time when the LE input is taken low logic level Figure 3: Logic Diagram 2/13 74LVQ573 Table 4: Absolute Maximum Ratings Symbol VCC VI VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 50 ± 400 -65 to +150 300 Unit V V V mA mA mA mA °C °C ICC or IGND DC VCC or Ground Current Storage Temperature Tstg TL Lead Temperature (10 sec) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied Table 5: Recommended Operating Conditions Symbol VCC VI VO Top dt/dv Supply Voltage (note 1) Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 3.0V (note 2) Parameter Value 2 to 3.6 0 to VCC 0 to VCC -55 to 125 0 to 10 Unit V V V °C ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V Table 6: DC Specifications Test Condition Symbol Parameter VCC (V) 3.0 to 3.6 IO=-50 µA 3.0 IO=-12 mA IO=-24 mA VOL Low Level Output Voltage IO=50 µA 3.0 3.6 3.6 3.6 3.6 IO=12 mA IO=24 mA II IOZ ICC IOLD IOHD Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current Dynamic Output Current (note 1, 2) VI = VCC or GND VI = VIH or VIL VO = VCC or GND VI = VCC or GND VOLD = 0.8 V max VOHD = 2 V min ± 0.1 ±0.25 4 36 -25 0.002 0 0.1 0.36 TA = 25°C Min. 2.0 0.8 2.9 2.58 2.99 2.9 2.48 2.2 0.1 0.44 0.55 ±1 ± 2.5 40 25 -25 Typ. Max. Value -40 to 85°C Min. 2.0 0.8 2.9 2.48 2.2 0.1 0.44 0.55 ±1 ± 5.0 40 µA µA µA mA mA V V Max. -55 to 125°C Unit Min. 2.0 0.8 Max. V V VIH VIL VOH High Level Input Voltage Low Level Input Voltage High Level Output Voltage 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω 3/13 74LVQ573 Table 7: Dynamic Switching Characteristics Test Condition Symbol Parameter VCC (V) 3.3 3.3 CL = 50 pF 3.3 0.8 V TA = 25°C Min. Typ. 0.5 -0.8 2 -0.6 Max. 0.8 V V Value -40 to 85°C Min. Max. -55 to 125°C Min. Max. Unit VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. Table 8: AC Electrical Characteristics (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) Test Condition Symbol Parameter VCC (V) 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3 2.7 3.3 2.7 3.3 2.7 3.3 (*) Value TA = 25°C Min. Typ. 7.2 5.8 7.2 5.8 8.7 7.4 8.5 7.5 2.0 1.5 0.0 0.0 0.0 0.0 0.5 0.5 Max. 11.5 9.0 11.5 9.0 14.0 11.5 14.0 11.5 5.0 4.0 4.0 3.0 1.5 1.5 1.0 1.0 -40 to 85°C Min. Max. 13.5 10.5 13.5 10.5 16.0 13.5 16.0 13.5 6.0 4.0 4.5 3.0 1.5 1.5 1.0 1.0 -55 to 125°C Min. Max. 15.5 12.0 15.5 12.0 18.5 15.5 18.5 15.5 6.0 4.0 4.5 3.0 1.5 1.5 1.0 1.0 ns ns ns ns ns ns ns Unit tPLH tPHL Propagation Delay Time LE to Q tPLH tPHL Propagation Delay Time D to Q tPLZ tPHZ tPZL tPZH tW tsL tsH thL thH tOSLH tOSHL Output Disable Time Output Enable Time LE Pulse Width HIGH Setup Time D to LE HIGH or LOW Hold Time D to LE, HIGH or LOW Output To Output Skew Time (note1, 2) (*) (*) (*) ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|) 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V 4/13 74LVQ573 Table 9: Capacitive Characteristics Test Condition Symbol Parameter VCC (V) 3.3 3.3 3.3 fIN = 10MHz TA = 25°C Min. Typ. 4 8 10 Max. Value -40 to 85°C Min. Max. -55 to 125°C Min. Max. pF pF pF Unit CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per latch) Figure 4: Test Circuit TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ CL = 50pF or equivalent (includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) SWITCH Open 2VCC Open 5/13 74LVQ573 Figure 5: Waveform - LE To Qn Propagation Delays, LE Minimum Pulse Width, Dn To LE Setup And Hold Times (f=1MHz; 50% duty cycle) Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle) 6/13 74LVQ573 Figure 7: Waveform - Dn To Qn Propagation Delay Time (f=1MHz; 50% duty cycle) 7/13 74LVQ573 SO-20 MECHANICAL DATA DIM. A A1 B C D E e H h L k ddd 10.00 0.25 0.4 0° mm. MIN. 2.35 0.1 0.33 0.23 12.60 7.4 1.27 10.65 0.75 1.27 8° 0.100 0.394 0.010 0.016 0° TYP MAX. 2.65 0.30 0.51 0.32 13.00 7.6 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 8° 0.004 inch TYP. MAX. 0.104 0.012 0.020 0.013 0.512 0.299 0016022D 8/13 74LVQ573 TSSOP20 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0˚ 0.45 0.60 0.05 0.8 0.19 0.09 6.4 6.2 4.3 6.5 6.4 4.4 0.65 BSC 8˚ 0.75 0˚ 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 6.6 6.6 4.48 0.002 0.031 0.007 0.004 0.252 0.244 0.169 0.256 0.252 0.173 0.0256 BSC 8˚ 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0079 0.260 0.260 0.176 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0087225C 9/13 74LVQ573 Tape & Reel SO-20 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 10.8 13.2 3.1 3.9 11.9 12.8 20.2 60 30.4 11 13.4 3.3 4.1 12.1 0.425 0.520 0.122 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.433 0.528 0.130 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch 10/13 74LVQ573 Tape & Reel TSSOP20 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.8 6.9 1.7 3.9 11.9 12.8 20.2 60 22.4 7 7.1 1.9 4.1 12.1 0.268 0.272 0.067 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.276 0.280 0.075 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch 11/13 74LVQ573 Table 10: Revision History Date 29-Jul-2004 Revision 5 Description of Changes Ordering Codes Revision - pag. 1. 12/13 74LVQ573 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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