74LVQ574M

® 74LVQ574 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUTS NON INVERTING s s s s s s s s s s s HIGH SPEED: fMAX = 180 MHz (TYP.) at VCC = 3.3V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.5 V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12 mA (MIN) PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 574 IMPROVED LATCH-UP IMMUNITY M (Micro Package) T (TSSOP Package) ORDER CODES : 74LVQ574M 74LVQ574T On the positive transition of the clock, the Q outputs will be set to logic state that were setup at the D inputs. While the (OE) input is low, the 8 outputs will be in al normal logic state (high or low logic level) and while high level, the outputs will be in a high impedance state. The output control does not affect the internal operation of flip flop, that is, the old data can be retained or the new data can be entered even while the outputs are off. It has better speed performance at 3.3V than 5V LS-TTL family combined with the true CMOS low power consumpion. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. DESCRIPTION The LVQ574 is a low voltage CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron 2 silicon gate and double-layer metal wiring C MOS technology. It is ideal for low power and low noise 3.3V applications. These 8 bit D-Type flip-flops are controlled by a clock input (CK) and an output enable input (OE). PIN CONNECTION AND IEC LOGIC SYMBOLS February 1999 1/10 74LVQ574 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2, 3, 4, 5, 6, 7, 8, 9 12, 13, 14, 15, 16, 17, 18, 19 11 10 20 SYMBOL OE D0 to D7 NAME AND FUNCT ION 3 State Output Enable Input (Active LOW) Data Inputs Q0 to Q7 3 State Outputs CLOCK GND VCC Clock Input (LOW to HIGH, edge triggered) Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS OE H L L L X:”H” or ”L” Z: High Impedance OUT PUTS D X X L H Q Z NO CHANGE L H CK X LOGIC DIAGRAMS 2/10 74LVQ574 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 50 ± 400 -65 to +150 300 Unit V V V mA mA mA mA o o ICC or IGND DC VCC or Ground Current C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top dt/dv Input Voltage Output Voltage Operating Temperature: Input Rise and Fall Time (VCC = 3V) (note 2) Parameter Supply Voltage (note 1) Valu e 2 to 3.6 0 to VCC 0 to VCC -40 to +85 0 to 10 Unit V V V o C ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V 3/10 74LVQ574 DC SPECIFICATIONS Symb ol Parameter V CC (V) VIH VIL VOH High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current 3 State Output Leakage Current Quiescent Supply Current Dynamic Output Current (note 1, 2) 3.0 to 3.6 3.0 VI = V IH or V IL VI(*) = VIH or VIL (* ) Test Co nditions Min. 2.0 T yp. Valu e T A = 25 oC Max. 0.8 -40 to 85 o C Min. 2.0 0.8 2.9 2.48 2.2 0.002 0 0.1 0.36 ±0.1 ±0.25 4 36 -25 0.1 0.44 0.55 ±1 ±2.5 40 2.99 Max. Un it V V V I O =-50 µ A IO=-12 mA IO=-24 mA IO=50 µA IO=12 mA IO=24 mA 2.9 2.58 VOL 3.0 V µA µA µA mA mA II IOZ ICC IOLD IOHD 3.6 3.6 3.6 3.6 VI = VCC or GND VI = VIH or VIL VO = VCC or GND VI = VCC or GND VOLD = 0.8 V max VOHD = 2 V min 1) Maximum test duration 2ms, one output loaded attime 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 Ω. (*) All outputs loaded. DYNAMIC SWITCHING CHARACTERISTICS Symb ol Parameter V CC (V) VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 3.3 -0.8 3.3 3.3 C L = 50 pF 0.8 Test Co nditions Min. T yp. 0.5 -0.6 2 V Valu e T A = 25 oC Max. 0.8 -40 to 85 o C Min. Max. Un it 1) Worst case package 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND 3) max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD). f=1MHz 4/10 74LVQ574 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns) Symb ol Parameter V CC (V) tPLH tPHL tPLZ tPHZ tPZL tPZH tw tsL tsH thL thH fMAX tOSLH tOSHL Propagation Delay Time CK to Q Output Disable Time Output Enable Time Clock pulse Width, HIGH or LOW Setup Time D to CK HIGH or LOW Hold Time D to CK HIGH or LOW Maximum Clock Frequency Output to Output Skew Time (note 1, 2) 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3(*) 80 100 T est Con ditio n Valu e T A = 25 oC -40 to 85 o C Min. T yp. Max. Min. Max. 7.5 17.0 18.0 6.0 8.0 6.5 8.0 6.5 2.0 1.5 0.0 0.0 0.0 0.0 150 180 0.5 0.5 1.0 1.0 11.0 20.0 14.0 18.0 12..0 5.0 4.0 2.5 2.0 2.5 2.0 70 90 1.5 1.5 12.0 21.0 15.0 19.0 13.0 6.0 4.0 3.0 2.5 3.0 2.5 Un it ns ns ns ns ns ns MHz ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tpHLn|) 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V CAPACITIVE CHARACTERISTICS Symb ol Parameter V CC (V) C IN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) 3.3 3.3 3.3 fIN = 10 MHz Test Co nditions o Valu e T A = 25 C Min. T yp. 4 10 15 Max. -40 to 85 C Min. Max. o Un it pF pF pF 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/8(per FlipFlop) 5/10 74LVQ574 TEST CIRCUIT T EST tPLH , tPHL tPZL , tPLZ tPZH , tPHZ CL = 50 pF or equivalent (includes jigand probe capacitance) RL = R1 = 500Ω orequivalent RT = ZOUT of pulse generator (typically 50Ω) SW IT CH Open 2VCC Open WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/10 74LVQ574 WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3: PULSE WIDTH 7/10 74LVQ574 SO-20 MECHANICAL DATA DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.40 0.50 12.60 10.00 1.27 11.43 7.60 1.27 0.75 8 (max.) 0.291 0.19 13.00 10.65 0.35 0.23 0.50 45 (typ.) 0.496 0.393 0.050 0.450 0.299 0.050 0.029 0.512 0.419 0.10 mm TYP. MAX. 2.65 0.20 2.45 0.49 0.32 0.013 0.009 0.020 0.004 MIN. inch TYP. MAX. 0.104 0.007 0.096 0.019 0.012 P013L 8/10 74LVQ574 TSSOP20 MECHANICAL DATA mm MIN. A A1 A2 b c D E E1 e K L 0o 0.50 0.05 0.85 0.19 0.09 6.4 6.25 4.3 6.5 6.4 4.4 0.65 BSC 4o 0.60 8o 0.70 0o 0.020 0.10 0.9 TYP. MAX. 1.1 0.15 0.95 0.30 0.2 6.6 6.5 4.48 0.002 0.335 0.0075 0.0035 0.252 0.246 0.169 0.256 0.252 0.173 0.0256 BSC 4o 0.024 8o 0.028 0.004 0.354 MIN. inch TYP. MAX. 0.433 0.006 0.374 0.0118 0.0079 0.260 0.256 0.176 DIM. A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 9/10 74LVQ574 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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