74LVX02MTR

74LVX02 LOW VOLTAGE CMOS QUAD 2-INPUT NOR GATE WITH 5V TOLERANT INPUTS ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4.5ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL: VIL=0.8V, VIH=2V at VCC=3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 02 IMPROVED LATCH-UP IMMUNITY POWER DOWN PROTECTION ON INPUTS SOP Table 1: Order Codes t c u d o r P e t e l o t e l o T&R 74LVX02MTR 74LVX02TTR s b O The internal circuit is composed of 3 stages including buffer output, which provides high noise immunity and stable output. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V system. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. ) (s DESCRIPTION The 74LVX02 is a low voltage CMOS QUAD 2-INPUT NOR GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. u d o r P e PACKAGE SOP TSSOP ) s ( ct TSSOP s b O Figure 1: Pin Connection And IEC Logic Symbols August 2004 Rev. 4 1/11 74LVX02 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N° SYMBOL 2, 5, 8, 11 3, 6, 9, 12 1, 4, 10, 13 7 1A to 4A 1B to 4B 1Y to 4Y GND VCC 14 NAME AND FUNCTION Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage Table 3: Truth Table A B Y L L H H L H L H H L L L Symbol VCC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current o s b ) s ( ct ICC or IGND DC VCC or Ground Current Storage Temperature Tstg TL let Parameter du ro Lead Temperature (10 sec) P e -O u d o r P e Table 4: Absolute Maximum Ratings ) s ( ct Value Unit -0.5 to +7.0 V -0.5 to +7.0 V -0.5 to VCC + 0.5 - 20 V mA ± 20 mA ± 25 mA ± 50 mA -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. t e l o Table 5: Recommended Operating Conditions Symbol Value Unit Supply Voltage (note 1) 2 to 3.6 V VI Input Voltage 0 to 5.5 V VO Output Voltage Top Operating Temperature s b O VCC dt/dv Input Rise and Fall Time (note 2) (VCC = 3.3V) 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2.0V 2/11 Parameter 0 to VCC V -55 to 125 °C 0 to 100 ns/V 74LVX02 Table 6: DC Specifications Test Condition Symbol VIH VIL VOH VOL II ICC Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Value TA = 25°C VCC (V) Min. 2.0 3.0 3.6 2.0 3.0 3.6 VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) b O so e t e l -55 to 125°C Min. Min. Max. 1.5 2.0 2.4 0.5 0.8 0.8 0.5 0.8 0.8 IO=-50 µA 1.9 2.0 1.9 1.9 3.0 2.9 3.0 2.9 2.9 3.0 IO=-4 mA 2.58 2.48 2.4 2.0 IO=50 µA 0.0 0.1 0.1 3.0 IO=50 µA 0.0 0.1 0.1 3.0 IO=4 mA 0.36 0.44 3.6 VI = 5V or GND ± 0.1 3.6 VI = VCC or GND ) (s t c u VCC (V) od Pr 3.3 3.3 3.3 e t e l so Min. -0.5 b O Max. V 0.5 0.8 0.8 IO=-50 µA 2 Unit 1.5 2.0 2.4 2.0 Test Condition Parameter Max. 1.5 2.0 2.4 Table 7: Dynamic Switching Characteristics Symbol Typ. -40 to 85°C V ) s ( ct V u d o Pr 0.1 0.1 V 0.55 ±1 ±1 µA 20 20 µA Value TA = 25°C Typ. Max. 0.3 0.5 -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. -0.3 2 CL = 50 pF V 0.8 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. 3/11 74LVX02 Table 8: AC Electrical Characteristics (Input tr = tf = 3ns) Test Condition Symbol Parameter tPLH tPHL Propagation Delay Time tOSLH tOSHL Output To Output Skew Time (note1, 2) VCC (V) CL (pF) 2.7 2.7 Value TA = 25°C Min. -40 to 85°C -55 to 125°C Typ. Max. Min. Max. Min. Max. 15 50 5.9 8.4 10.7 14.2 1.0 1.0 13.5 17.0 1.0 1.0 15.0 19.0 3.3(*) 15 4.5 6.6 1.0 8.0 1.0 10.0 3.3(*) 2.7 50 7.0 10.1 1.0 11.5 1.0 13.0 50 3.3(*) 50 0.5 0.5 1.0 1.0 1.5 1.5 Unit 1.5 1.5 ns ) s ( ct ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V u d o r P e Table 9: Capacitive Characteristics t e l o Test Condition Symbol Parameter Value TA = 25°C VCC (V) CIN Input Capacitance 3.3 CPD Power Dissipation Capacitance (note 1) 3.3 Min. bs Typ. Max. 4 10 O ) s ( t c 15 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (per gate) u d o Figure 3: Test Circuit r P e t e l o s b O CL =15/50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) 4/11 74LVX02 Figure 4: Waveform - Propagation Delays (f=1MHz; 50% duty cycle) ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 5/11 74LVX02 SO-14 MECHANICAL DATA mm. DIM. MIN. inch TYP MAX. MIN. TYP. MAX. A 1.35 1.75 0.053 0.069 A1 0.1 0.25 0.004 0.010 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 8.55 8.75 0.337 0.344 E 3.8 4.0 0.150 e ) s ( ct 1.27 r P e 0.050 H 5.8 6.2 0.228 h 0.25 0.50 0.010 L 0.4 1.27 k 0° 8° (s) ddd 0.100 let -O o s b u d o 0.157 0.244 0.020 0.016 0.050 0° 8° 0.004 t c u d o r P e t e l o s b O 0016019D 6/11 74LVX02 TSSOP14 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 c 0.09 0.20 0.004 D 4.9 5 5.1 0.193 E 6.2 6.4 6.6 0.244 E1 4.3 4.4 4.48 0.169 1 e K 0˚ L 0.45 A 0.60 r P e 0.197 bs O ) 8˚ 0.75 s ( t c u d o 0.0089 t e l o 0.65 BSC ) s ( ct 0.012 0.201 0.252 0.260 0.173 0.176 0.0256 BSC 0˚ 8˚ 0.018 0.024 0.030 u d o r P e A2 let A1 o s b b O e K c L E D E1 PIN 1 IDENTIFICATION 1 0080337D 7/11 74LVX02 Tape & Reel SO-14 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A TYP. MAX. 330 13.2 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 0.504 0.519 ) s ( ct 22.4 0.882 Ao 6.4 6.6 0.252 Bo 9 9.2 0.354 Ko 2.1 2.3 0.082 Po 3.9 4.1 0.153 P 7.9 8.1 0.311 ) (s t c u d o r P e t e l o s b O 8/11 MIN. 0.260 ro P e let so b O du 0.362 0.090 0.161 0.319 74LVX02 Tape & Reel TSSOP14 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 330 13.2 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 0.504 0.519 ) s ( ct 22.4 0.882 Ao 6.7 6.9 0.264 Bo 5.3 5.5 0.209 Ko 1.6 1.8 0.063 Po 3.9 4.1 0.153 P 7.9 8.1 0.311 ) (s 0.272 ro P e let so b O du 0.217 0.071 0.161 0.319 t c u d o r P e t e l o s b O 9/11 74LVX02 Table 10: Revision History Date Revision 27-Aug-2004 4 Description of Changes Ordering Codes Revision - pag. 1. ) s ( ct u d o r P e t e l o ) (s t c u d o r P e t e l o s b O 10/11 s b O 74LVX02 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 11/11