74LVX174

74LVX174 LOW VOLTAGE CMOS HEX D-TYPE FLIP-FLOP WITH CLEAR WITH 5V TOLERANT INPUTS s HIGH SPEED: fMAX = 180MHz (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL: VIL=0.8V, VIH=2V at VCC=3V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 174 IMPROVED LATCH-UP IMMUNITY POWER DOWN PROTECTION ON INPUTS SOP TSSOP s s s s Table 1: Order Codes PACKAGE SOP TSSOP T&R 74LVX174MTR 74LVX174TTR s s s s s s DESCRIPTION The 74LVX174 is a low voltage CMOS HEX D-TYPE FLIP FLOP WITH CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. Figure 1: Pin Connection And IEC Logic Symbols Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse. When the CLEAR input is held low, the Q outputs are held low independently of the other inputs. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V system. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. August 2004 Rev. 3 1/12 74LVX174 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N° 1 2, 5, 7, 10, 12, 15 3, 4, 6, 11, 13, 14 9 8 16 SYMBOL CLEAR Q0 to Q5 D0 to D5 CLOCK GND VCC NAME AND FUNCTION Asynchronous Master Reset (Active LOW) Flip-Flop Outputs Data Inputs Clock Input (LOW-to-HIGH, Edge Triggered) Ground (0V) Positive Supply Voltage Table 3: Truth Table INPUTS CLEAR L H H H X : Don’t Care OUTPUTS FUNCTION CLOCK X Q L L H Qn NO CHANGE CLEAR D X L H X Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/12 74LVX174 Table 4: Absolute Maximum Ratings Symbol VCC VI VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 ± 20 ± 25 ± 50 -65 to +150 300 Unit V V V mA mA mA mA °C °C ICC or IGND DC VCC or Ground Current Storage Temperature Tstg TL Lead Temperature (10 sec) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 5: Recommended Operating Conditions Symbol VCC VI VO Top dt/dv Supply Voltage (note 1) Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time (note 2) (VCC = 3.3V) Parameter Value 2 to 3.6 0 to 5.5 0 to VCC -55 to 125 0 to 100 Unit V V V °C ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2.0V Table 6: DC Specifications Test Condition Symbol Parameter VCC (V) 2.0 3.0 3.6 2.0 3.0 3.6 2.0 3.0 3.0 VOL Low Level Output Voltage 2.0 3.0 3.0 II ICC Input Leakage Current Quiescent Supply Current 3.6 3.6 IO=-50 µA IO=-50 µA IO=-4 mA IO=50 µA IO=50 µA IO=4 mA VI = 5V or GND VI = VCC or GND TA = 25°C Min. 1.5 2.0 2.4 0.5 0.8 0.8 1.9 2.9 2.58 0.0 0.0 0.1 0.1 0.36 ± 0.1 4 2.0 3.0 1.9 2.9 2.48 0.1 0.1 0.44 ±1 40 Typ. Max. Value -40 to 85°C Min. 1.5 2.0 2.4 0.5 0.8 0.8 1.9 2.9 2.4 0.1 0.1 0.55 ±1 40 µA µA V V Max. -55 to 125°C Min. 1.5 2.0 2.4 0.5 0.8 0.8 Max. V Unit VIH High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL V VOH 3/12 74LVX174 Table 7: Dynamic Switching Characteristics Test Condition Symbol Parameter VCC (V) 3.3 3.3 3.3 CL = 50 pF TA = 25°C Min. Typ. 0.3 -0.8 2 0.8 -0.3 V Max. 0.8 Value -40 to 85°C Min. Max. -55 to 125°C Min. Max. Unit VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. Table 8: AC Electrical Characteristics (Input tr = tf = 3ns) Test Condition Symbol Parameter VCC (V) 2.7 2.7 3.3(*) tPLH tPHL Propagation Delay Time CLEAR to Q 3.3(*) 2.7 2.7 3.3(*) tWL tW tS CLEAR pulse Width, HIGH CLOCK pulse Width Setup Time Q to CLOCK HIGH or LOW Hold Time Q to CLOCK HIGH or LOW Recovery Time CLEAR to Q Maximum Clock Frequency 3.3(*) 2.7 3.3 2.7 3.3 2.7 (*) Value TA = 25°C Min. Typ. 7.6 10.1 5.9 8.4 7.9 10.4 6.2 8.7 6.5 5.0 6.5 5.0 7.5 5.0 0.0 0.0 4.5 3.0 Max. 14.5 18.0 9.3 12.8 15.0 18.5 9.7 13.2 -40 to 85°C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max. 17.5 21.0 11.0 14.5 18.5 22.0 11.5 15.0 7.5 5.0 7.5 5.0 8.5 6.0 0.0 0.0 4.5 3.0 55 40 95 55 1.0 1.0 1.5 1.5 1.5 1.5 ns MHz -55 to 125°C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max. 18.5 22.0 12.0 15.5 19.5 23.0 12.5 16.0 7.5 5.0 7.5 5.0 8.5 6.0 0.0 0.0 ns ns ns ns Unit CL (pF) 15 50 15 50 15 50 15 50 tPLH tPHL Propagation Delay Time CLOCK to Q (*) 3.3(*) 2.7 3.3 (*) ns th ns tREM fMAX 2.7 3.3(*) 2.7 2.7 3.3(*) 3.3(*) 2.7 3.3(*) 15 50 15 50 50 50 65 45 115 65 ns 130 60 180 95 0.5 0.5 tOSLH tOSHL Output To Output Skew Time (note1, 2) 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V 4/12 74LVX174 Table 9: Capacitive Characteristics Test Condition Symbol Parameter VCC (V) 3.3 3.3 fIN = 10MHz TA = 25°C Min. Typ. 5 23 Max. Value -40 to 85°C Min. Max. 10 -55 to 125°C Min. Max. 10 pF pF Unit CIN CPD Input Capacitance Power Dissipation Capacitance (note 1) 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit) Figure 4: Test Circuit CL =15/50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) Figure 5: Waveform - Propagation Delays (f=1MHz; 50% duty cycle) 5/12 74LVX174 Figure 6: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle) Figure 7: Waveform - Recovery Time, Minimum Pulse Width (f=1MHz; 50% duty cycle) 6/12 74LVX174 SO-16 MECHANICAL DATA DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8° (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45° (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.25 1.64 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.010 0.063 0.018 0.010 0016020D 7/12 74LVX174 TSSOP16 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0˚ 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8˚ 0.75 0˚ 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8˚ 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0079 0.201 0.260 0.176 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 8/12 74LVX174 Tape & Reel SO-16 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.45 10.3 2.1 3.9 7.9 12.8 20.2 60 22.4 6.65 10.5 2.3 4.1 8.1 0.254 0.406 0.082 0.153 0.311 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.262 0.414 0.090 0.161 0.319 MIN. TYP. MAX. 12.992 0.519 inch 9/12 74LVX174 Tape & Reel TSSOP16 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.7 5.3 1.6 3.9 7.9 12.8 20.2 60 22.4 6.9 5.5 1.8 4.1 8.1 0.264 0.209 0.063 0.153 0.311 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.272 0.217 0.071 0.161 0.319 MIN. TYP. MAX. 12.992 0.519 inch 10/12 74LVX174 Table 10: Revision History Date 27-Aug-2004 Revision 3 Description of Changes Ordering Codes Revision - pag. 1. 11/12 74LVX174 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 12/12