74LVX574TTR

74LVX574 LOW VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP (3-STATE NON INV.) WITH 5V TOLERANT INPUTS ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 125MHz (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC = 3V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC =3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4 mA (MIN) at VCC =3V BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 574 IMPROVED LATCH-UP IMMUNITY SOP Table 1: Order Codes t c u d o r P e t e l o s b O t e l o T&R 74LVX574MTR 74LVX574TTR s b O D inputs. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. The output control does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. ) (s DESCRIPTION The 74LVX574 is a low voltage CMOS OCTAL D-TYPE FLIP-FLOP with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. This 8 bit D-Type flip-flop is controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the u d o r P e PACKAGE SOP TSSOP ) s ( ct TSSOP Figure 1: Pin Connection And IEC Logic Symbols August 2004 Rev. 3 1/13 74LVX574 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N° SYMBOL 1 OE 2, 3, 4, 5, 6, 7, 8, 9 12, 13, 14, 15, 16, 17, 18, 19 11 D0 to D7 3-State Output Enable Input (Active LOW) Data Inputs Q0 to Q7 3-State Outputs 10 20 CK NAME AND FUNCTION Clock Input (LOW-to-HIGH Edge Triggered) Ground (0V) Positive Supply Voltage ) s ( ct GND VCC Table 3: Truth Table u d o INPUTS OUTPUT OE CK D H X X L X L L L H ) (s X : Don’t Care Z : High Impedance Figure 3: Logic Diagram t c u d o r P e t e l o s b O This logic diagram has not be used to estimate propagation delays 2/13 s b O t e l o r P e Q Z NO CHANGE L H 74LVX574 Table 4: Absolute Maximum Ratings Symbol VCC Parameter Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current Value Unit -0.5 to +7.0 V -0.5 to +7.0 V -0.5 to VCC + 0.5 - 20 V mA ± 20 mA ICC or IGND DC VCC or Ground Current Storage Temperature Tstg mA mA ) s ( ct -65 to +150 Lead Temperature (10 sec) TL ± 25 ± 50 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied Table 5: Recommended Operating Conditions Symbol VCC Value let Supply Voltage (note 1) Input Voltage VO Output Voltage Top Operating Temperature so Input Rise and Fall Time (note 2) (VCC = 3V) dt/dv ) (s 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2.0V b O t c u Table 6: DC Specifications od Test Condition Symbol Parameter VIH O VOH VOL IOZ II ICC e t e l High Level Input Voltage Pr o s b VIL r P e Parameter VI Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Quiescent Supply Current u d o VCC (V) 2 to 3.6 V 0 to 5.5 V 0 to VCC V -55 to 125 °C 0 to 100 ns/V Value TA = 25°C Min. 2.0 3.0 3.6 2.0 3.0 3.6 Unit Typ. Max. 1.5 2.0 2.4 -40 to 85°C -55 to 125°C Unit Min. Min. Max. 1.5 2.0 2.4 0.5 0.8 0.8 Max. 1.5 2.0 2.4 0.5 0.8 0.8 V 0.5 0.8 0.8 V 2.0 IO=-50 µA 1.9 2.0 1.9 1.9 3.0 IO=-50 µA 2.9 3.0 2.9 2.9 3.0 IO=-4 mA 2.58 2.0 IO=50 µA 0.0 3.0 IO=50 µA 0.0 0.1 0.1 0.1 3.0 IO=4 mA 0.36 0.44 0.55 3.6 VI = VIH or VIL VO = VCC or GND ±0.25 ± 2.5 ± 2.5 µA 3.6 VI = 5V or GND ± 0.1 ±1 ±1 µA 3.6 VI = VCC or GND 4 40 40 µA 2.48 0.1 V 2.4 0.1 0.1 V 3/13 74LVX574 Table 7: Dynamic Switching Characteristics Test Condition Symbol VOLP Parameter VOLV Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) VIHD VILD Value TA = 25°C VCC (V) Min. 3.3 -0.8 CL = 50 pF 3.3 Typ. Max. 0.3 0.8 -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. -0.3 V 2.0 3.3 ) s ( ct 0.8 u d o 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. r P e Table 8: AC Electrical Characteristics (Input tr = tf = 3ns) t e l o Test Condition Symbol tPLH tPHL Parameter tPZL tPZH Propagation Delay Time CK to Q Output Enable Time VCC (V) CL (pF) 2.7 2.7 15 50 3.3(*) 15 3.3(*) 2.7 2.7 50 e t e ol Output Disable Time bs tW CK pulse Width, HIGH O Setup Time D to CK HIGH or LOW th Hold Time D to CK HIGH or LOW tS fMAX tOSLH tOSHL Maximum Clock Frequency Output to Output Skew Time (note 1,2) Min. Pr ) (s ct s b O -40 to 85°C -55 to 125°C Typ. Max. Min. Max. Min. Max. 9.2 11.5 14.5 18.0 1.0 1.0 17.5 21.0 1.0 1.0 17.5 21.0 8.5 13.2 1.0 15.5 1.0 15.5 11.0 16.7 1.0 19.0 1.0 19.0 9.8 11.4 15.0 18.5 1.0 1.0 18.5 22.0 1.0 1.0 18.5 22.0 8.2 12.8 1.0 15.0 1.0 15.0 (*) 15 3.3(*) 2.7 50 10.7 16.3 1.0 18.5 1.0 18.5 50 12.1 19.1 1.0 22.0 1.0 22.0 3.3(*) 2.7 50 11.0 15.0 1.0 17.0 1.0 17.0 50 6.5 7.5 7.5 3.3(*) 2.7 50 5.0 5.0 5.0 50 5.0 5.0 5.0 3.3(*) 2.7 50 3.5 3.5 3.5 50 1.5 1.5 1.5 (*) 50 1.5 1.5 1.5 3.3 tPLZ tPHZ TA = 25°C u d o 15 50 Value 3.3 2.7 2.7 15 50 60 45 115 60 50 40 48 40 3.3(*) 15 80 125 65 60 3.3(*) 2.7 50 50 75 45 40 50 0.5 1.0 1.5 1.5 3.3(*) 50 0.5 1.0 1.5 1.5 Unit ns ns ns ns ns ns MHz ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V 4/13 74LVX574 Table 9: Capacitive Characteristics Test Condition Symbol Parameter CIN Input Capacitance COUT Output Capacitance Power Dissipation Capacitance (note 1) CPD Value TA = 25°C VCC (V) -55 to 125°C Min. Min. Max. 3.3 4 10 3.3 6 pF 27 pF fIN = 10MHz Max. Unit Typ. 3.3 Min. -40 to 85°C Max. 10 10 pF ) s ( ct 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per circuit) Figure 4: Test Circuit u d o r P e t e l o ) (s s b O t c u d o r let tPLH, tPHL tPZL, tPLZ o s b tPZH, tPHZ P e TEST SWITCH Open VCC GND O CL =15/50pF or equivalent (includes jig and probe capacitance) RL = R1 = 1KΩ or equivalent RT = ZOUT of pulse generator (typically 50Ω) 5/13 74LVX574 Figure 5: Waveform - Propagation Delays Setup And Hold Times (f=1MHz; 50% duty cycle) ) s ( ct u d o r P e t e l o ) (s s b O Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle) t c u d o r P e t e l o s b O 6/13 74LVX574 Figure 7: Waveform - CK Minimum Pulse Width (f=1MHz; 50% duty cycle) ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 7/13 74LVX574 SO-20 MECHANICAL DATA mm. DIM. MIN. inch TYP MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.1 0.30 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.60 13.00 0.496 0.512 E 7.4 7.6 0.291 e 1.27 ) s ( ct 0.299 o r P 0.050 e t e ol H 10.00 10.65 0.394 h 0.25 0.75 0.010 L 0.4 1.27 k 0° 8° (s) ddd 0.100 -O bs du 0.419 0.030 0.016 0.050 0° 8° 0.004 t c u d o r P e t e l o s b O 0016022D 8/13 74LVX574 TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 c 0.09 0.20 0.004 D 6.4 6.5 6.6 0.252 E 6.2 6.4 6.6 0.244 E1 4.3 4.4 4.48 0.169 1 e K 0˚ L 0.45 r P e let o s b 0.60 0.75 s ( t c r P e 0.256 t e l o 0.260 0.252 0.260 0.173 0.176 0.0256 BSC 0˚ 8˚ 0.018 0.024 0.030 u d o A2 A O ) 8˚ u d o 0.0079 bs 0.65 BSC ) s ( ct 0.012 A1 b O K e L E c D E1 PIN 1 IDENTIFICATION 1 0087225C 9/13 74LVX574 Tape & Reel SO-20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A TYP. MAX. 330 13.2 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 0.504 0.519 ) s ( ct 30.4 1.197 Ao 10.8 11 0.425 Bo 13.2 13.4 0.520 Ko 3.1 3.3 0.122 Po 3.9 4.1 0.153 P 11.9 12.1 0.468 ) (s t c u d o r P e t e l o s b O 10/13 MIN. 0.433 ro P e let so b O du 0.528 0.130 0.161 0.476 74LVX574 Tape & Reel TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 330 13.2 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 0.504 0.519 ) s ( ct 22.4 0.882 Ao 6.8 7 0.268 Bo 6.9 7.1 0.272 Ko 1.7 1.9 0.067 Po 3.9 4.1 0.153 P 11.9 12.1 0.468 ) (s 0.276 ro P e let so b O du 0.280 0.075 0.161 0.476 t c u d o r P e t e l o s b O 11/13 74LVX574 Table 10: Revision History Date Revision 27-Aug-2004 3 Description of Changes Ordering Codes Revision - pag. 1. ) s ( ct u d o r P e t e l o ) (s t c u d o r P e t e l o s b O 12/13 s b O 74LVX574 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. 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