74VHC16240
16-BIT BUS BUFFER
WITH 3-STATE OUTPUTS (INVERTED)
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■
■
■
■
■
■
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■
HIGH SPEED: tPD = 5.3 ns (TYP.) at VCC = 5V
LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
HIGH NOISE IMMUNITY
VNIH=VNIL= 28% VCC (MIN.)
POWER DOWN PROTECTION ON INPUTS
& OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 5.5V
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: VOLP = 0.9V (MAX.)
DESCRIPTION
The 74VHC16240 is an advanced high-speed
CMOS 16-BIT BUS BUFFER (3-STATE)
fabricated with sub-micron silicon gate and
double-layer metal wiring C2MOS technology.
Any nG output control governs four BUS
BUFFERS. Output Enable inputs (nG) tied
together give full 16 bit operation.
When nG is LOW, the outputs are on. When nG is
HIGH, the output are in high impedance state.
This device is designed to be used with 3 state
memory address drivers, etc.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
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TSSOP
PACKAGE
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TSSOP
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ORDER CODES
TUBE
T&R
74VHC16240TTR
PIN CONNECTION
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February 2003
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74VHC16240
INPUT EQUIVALENT CIRCUIT
IEC LOGIC SYMBOLS
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PIN DESCRIPTION
PIN No
SYMBOL
1
2, 3, 5, 6
8, 9, 11, 12
13, 14, 16, 17
19, 20, 22, 23
24
25
30, 29, 27, 26
36, 35, 33, 32
41, 40, 38, 37
47, 46, 44, 43
48
4, 10, 15, 21,
28, 34, 39, 45
1G
1Y1 to 1Y4
2Y1 to 2Y4
3Y1 to 3Y4
4Y1 to 4Y4
4G
3G
4A1 to 4A4
3A1 to 3A4
2A1 to 2A4
1A1 to 1A4
2G
Output Enable Input
Data Outputs
Data Outputs
Data Outputs
Data Outputs
Output Enable Input
Output Enable Input
Data Input
Data Input
Data Input
Data Input
Output Enable Input
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7, 18, 31, 42
GND
Ground (0V)
VCC
Positive Supply Voltage
TRUTH TABLE
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INPUTS
2/10
OUTPUT
G
An
Yn
L
L
H
L
H
X
H
L
Z
X : Don‘t Care
Z : High Impedance
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NAME AND FUNCTION
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74VHC16240
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
Unit
Supply Voltage
-0.5 to +7.0
V
VI
DC Input Voltage
-0.5 to +7.0
V
VO
DC Output Voltage
-0.5 to VCC + 0.5
V
IIK
DC Input Diode Current
- 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
± 25
mA
± 75
mA
-65 to +150
°C
ICC or IGND DC VCC or Ground Current
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
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300
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
ete
Supply Voltage
VI
Input Voltage
VO
Output Voltage
Top
Operating Temperature
dt/dv
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Input Rise and Fall Time (note 1) (VCC = 3.3 ± 0.3V)
(VCC = 5.0 ± 0.5V)
)
(s
1) VIN from 30% to 70% of VCC
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P
Value
Unit
2 to 5.5
V
0 to 5.5
V
0 to VCC
V
-55 to 125
°C
0 to 100
0 to 20
ns/V
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74VHC16240
DC SPECIFICATIONS
Test Condition
Symbol
VIH
Parameter
High Level Input
Voltage
VIL
Low Level Input
Voltage
VOH
VOL
Ioz
High Level Output
Voltage
Low Level Output
Voltage
II
High Impedance
Output Leakage
Current
Input Leakage
Current
Quiescent Supply
Current
ICC
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TA = 25°C
VCC
(V)
Min.
2.0
3.0 to
5.5
2.0
3.0 to
5.5
Typ.
Max.
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
1.5
1.5
1.5
0.7VCC
0.7VCC
0.7VCC
0.5
0.3VCC
0.3VCC
0.3VCC
V
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IO=-50 µA
1.9
2.0
1.9
1.9
3.0
IO=-50 µA
2.9
3.0
2.9
2.9
4.5
IO=-50 µA
4.4
4.5
4.4
4.4
3.0
IO=-4 mA
2.58
2.48
4.5
IO=-8 mA
3.94
3.8
2.0
IO=50 µA
0.0
0.1
3.0
IO=50 µA
0.0
4.5
IO=50 µA
0.0
ete
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V
0.5
0.1
Unit
Max.
0.5
2.0
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0.1
0.1
V
2.4
Pr
3.7
0.1
0.1
0.1
0.1
0.1
0.36
0.44
0.55
0.36
0.44
0.55
±0.25
± 2.5
± 2.5
µA
V
3.0
IO=4 mA
4.5
IO=8 mA
5.5
VI = VIH or VIL
VO = VCC or GND
0 to
5.5
VI = 5.5V or GND
± 0.1
±1
±1
µA
5.5
VI = VCC or GND
4
40
40
µA
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74VHC16240
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
Test Condition
Symbol
tPLH
tPHL
Parameter
Propagation Delay
Time
VCC
(V)
CL
(pF)
3.3(*)
3.3(*)
(**)
Output Enable
Time
Output Disable
Time
tOSLH
tOSHL
Output to Output
Skew time (note 1)
Min.
Max.
Min.
Max.
15
5.3
8.4
1.0
10.0
1.0
10.0
50
7.8
11.9
1.0
13.5
1.0
13.5
15
3.6
6.0
1.0
6.5
1.0
7.0
5.0(**)
50
5.1
8.0
1.0
8.5
1.0
9.0
(*)
1.0
12.5
1.0
12.5
15
RL = 1KΩ
6.6
10.6
3.3(*)
50
RL = 1KΩ
9.1
14.1
1.0
16.0
1.0
16.0
5.0(**)
15
RL = 1KΩ
4.7
7.3
1.0
8.5
1.0
8.5
5.0(**)
50
RL = 1KΩ
6.2
9.3
1.0
10.5
1.0
du
10.5
(*)
50
RL = 1KΩ
10.3
14.0
1.0
16.0
1.0
16.0
50
RL = 1KΩ
6.7
9.2
1.0
10.5
1.0
10.5
3.3(*)
50
5.0(**)
50
5.0
1.5
ete
1.0
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Output
Capacitance
Power Dissipation
Capacitance
(note 1)
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CPD
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Input Capacitance
COUT
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ns
1.5
1.5
1.0
1.0
ns
ns
ns
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Test Condition
Parameter
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Unit
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(**)
3.3
CAPACITIVE CHARACTERISTICS
CIN
-55 to 125°C
Min.
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
Note 1 : Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |tpHLm - tpHLn|
Symbol
-40 to 85°C
Max.
3.3
tPLZ
tPHZ
TA = 25°C
Typ.
5.0
tPZL
tPZH
Value
Value
TA = 25°C
Min.
Typ.
Max.
6
10
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
10
Unit
Max.
10
pF
8
pF
20
pF
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1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per
circuit)
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74VHC16240
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition
Symbol
VOLP
VOLV
VIHD
VILD
Parameter
Dynamic Low
Voltage Quiet
Output (note 1, 2)
Dynamic High
Voltage Input
(note 1, 3)
Dynamic Low
Voltage Input
(note 1, 3)
TA = 25°C
VCC
(V)
Min.
5.0
5.0
Value
Typ.
Max.
0.6
0.9
-0.9
CL = 50 pF
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
Unit
Max.
V
-0.6
3.5
5.0
V
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1.5
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V
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (V ILD), 0V to threshold
(VIHD), f=1MHz.
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TEST CIRCUIT
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TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
tPZH, tPHZ
VCC
CL =15/ 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω
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GND
74VHC16240
WAVEFORM 1 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
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WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
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74VHC16240
TSSOP48 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
A
MIN.
TYP.
MAX.
1.2
A1
0.05
0.047
0.15
A2
0.002
0.006
0.9
0.035
b
0.17
0.27
0.0067
c
0.09
0.20
0.0035
D
12.4
12.6
0.488
E
E1
0˚
L
0.50
0.236
bs
let
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b
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)
8˚
ro
0.0079
0.496
s
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c
0.75
0.244
0.0197 BSC
0˚
8˚
0.020
0.030
u
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P
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A
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6.2
0.5 BSC
K
du
0.318 BSC
6.0
e
0.011
P
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8.1 BSC
)
s
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A2
A1
b
K
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L
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D
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E1
PIN 1 IDENTIFICATION
1
7065588C
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74VHC16240
Tape & Reel TSSOP48 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
A
MAX.
MIN.
TYP.
330
MAX.
12.992
C
12.8
13.2
D
20.2
0.795
N
60
2.362
T
0.504
0.519
)
s
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30.4
1.197
Ao
8.7
8.9
0.343
Bo
13.1
13.3
0.516
Ko
1.5
1.7
0.059
Po
3.9
4.1
P
11.9
12.1
)
(s
let
0.153
so
b
O
P
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0.468
ro
du
0.350
0.524
0.067
0.161
0.476
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74VHC16240
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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