74VHC20MTR

74VHC20 DUAL 4-INPUT NAND GATE ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 3.3 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 20 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74VHC20 is an advanced high-speed CMOS DUAL 4-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which provides high noise immunity and stable output. SOP TSSOP Table 1: Order Codes PACKAGE T&R SOP TSSOP 74VHC20MTR 74VHC20TTR Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Figure 1: Pin Connection And IEC Logic Symbols November 2004 Rev. 4 1/10 74VHC20 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N° SYMBOL 1, 9 2, 10 3, 11 4, 12 5, 13 6, 8 7 1A to 2A 1B to 2B N.C. 1C to 2C 1D to 2D 1Y to 2Y GND VCC 14 NAME AND FUNCTION Data Inputs Data Inputs Not Connected Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage Table 3: Truth Table A B C D Y L X X X H X L X X H X X L X H X X X L H H H H H L X : Don‘t Care Table 4: Absolute Maximum Ratings Symbol VCC Parameter Supply Voltage VI DC Input Voltage VO DC Output Voltage Value Unit -0.5 to +7.0 V -0.5 to +7.0 V -0.5 to VCC + 0.5 - 20 V mA IIK DC Input Diode Current IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) ± 50 mA -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied Table 5: Recommended Operating Conditions Symbol Value Unit Supply Voltage 2 to 5.5 V VI Input Voltage 0 to 5.5 V VO Output Voltage Top Operating Temperature VCC dt/dv Parameter Input Rise and Fall Time (note 1) (VCC = 3.3 ± 0.3V) (VCC = 5.0 ± 0.5V) 1) VIN from 30% to 70% of VCC 2/10 0 to VCC V -55 to 125 °C 0 to 100 0 to 20 ns/V 74VHC20 Table 6: DC Specifications Test Condition Symbol VIH VIL VOH VOL II ICC Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Value TA = 25°C VCC (V) Min. 2.0 3.0 to 5.5 2.0 3.0 to 5.5 Typ. Max. -40 to 85°C -55 to 125°C Min. Min. Max. 1.5 1.5 1.5 0.7VCC 0.7VCC 0.7VCC Max. V 0.5 0.5 0.5 0.3VCC 0.3VCC 0.3VCC 2.0 IO=-50 µA 1.9 2.0 1.9 1.9 3.0 IO=-50 µA 2.9 3.0 2.9 2.9 4.5 IO=-50 µA 4.4 4.5 3.0 IO=-4 mA 2.58 3.94 4.4 4.4 2.48 2.4 Unit V V 4.5 IO=-8 mA 2.0 IO=50 µA 0.0 0.1 0.1 0.1 3.0 IO=50 µA 0.0 0.1 0.1 0.1 4.5 IO=50 µA 0.0 0.1 0.1 0.1 3.0 IO=4 mA 0.36 0.44 0.55 4.5 IO=8 mA 0.36 0.44 0.55 0 to 5.5 VI = 5.5V or GND ± 0.1 ±1 ±1 µA 5.5 VI = VCC or GND 2 20 20 µA 3.8 3.7 V Table 7: AC Electrical Characteristics (Input tr = tf = 3ns) Test Condition Symbol tPLH tPHL Parameter Propagation Delay Time VCC (V) CL (pF) 3.3(*) 3.3(*) (**) 5.0(**) 5.0 Value TA = 25°C Min. -40 to 85°C -55 to 125°C Typ. Max. Min. Max. Min. Max. 15 4.6 6.6 1.0 8.0 1.0 8.0 50 7.1 10.1 1.0 11.5 1.0 11.5 15 3.3 5.0 1.0 6.0 1.0 6.0 50 4.8 7.0 1.0 8.0 1.0 8.0 Unit ns (*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5.0V ± 0.5V 3/10 74VHC20 Table 8: Capacitive Characteristics Test Condition Symbol Parameter Value TA = 25°C Min. Typ. Max. 10 CIN Input Capacitance 6 CPD Power Dissipation Capacitance (note 1) 16 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per gate) Figure 3: Test Circuit CL =15/50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) Figure 4: Waveform - Propagation Delays (f=1MHz; 50% duty cycle) 4/10 74VHC20 SO-14 MECHANICAL DATA DIM. mm. MIN. TYP inch MAX. MIN. TYP. MAX. A 1.35 1.75 0.053 0.069 A1 0.1 0.25 0.004 0.010 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 8.55 8.75 0.337 0.344 E 3.8 4.0 0.150 0.157 e 1.27 0.050 H 5.8 6.2 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.4 1.27 0.016 0.050 k 0° 8° 0° 8° ddd 0.100 0.004 0016019D 5/10 74VHC20 TSSOP14 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0˚ L 0.45 A 0.60 0.0256 BSC 8˚ 0˚ 0.75 0.018 8˚ 0.024 0.030 A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080337D 6/10 74VHC20 Tape & Reel SO-14 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 22.4 0.519 0.882 Ao 6.4 6.6 0.252 0.260 Bo 9 9.2 0.354 0.362 Ko 2.1 2.3 0.082 0.090 Po 3.9 4.1 0.153 0.161 P 7.9 8.1 0.311 0.319 7/10 74VHC20 Tape & Reel TSSOP14 MECHANICAL DATA mm. inch DIM. MIN. A MAX. MIN. 330 13.2 TYP. MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 8/10 TYP 0.504 22.4 0.519 0.882 Ao 6.7 6.9 0.264 0.272 Bo 5.3 5.5 0.209 0.217 Ko 1.6 1.8 0.063 0.071 Po 3.9 4.1 0.153 0.161 P 7.9 8.1 0.311 0.319 74VHC20 Table 9: Revision History Date Revision 12-Nov-2004 4 Description of Changes Order Codes Revision - pag. 1. 9/10 74VHC20 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. 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