74VHC273

74VHC273 OCTAL D-TYPE FLIP FLOP WITH CLEAR s s s s s s s s s s HIGH SPEED: fMAX = 165 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.) SOP TSSOP Table 1: Order Codes PACKAGE SOP TSSOP T&R 74VHC273MTR 74VHC273TTR DESCRIPTION The 74VHC273 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse. When the CLEAR input is held low, the Q outputs are held low independently of the other inputs. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Figure 1: Pin Connection And IEC Logic Symbols November 2004 Rev. 5 1/14 74VHC273 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N° 1 2, 5, 6, 9, 12, 15, 16,19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 SYMBOL CLEAR Q0 to Q7 D0 to D7 CLOCK GND VCC NAME AND FUNCTION Asynchronous Master Reset (Active LOW) Flip-Flop Outputs Data Inputs Clock Input (LOW-to-HIGH Edge Triggered) Ground (0V) Positive Supply Voltage Table 3: Truth Table INPUTS CLEAR L H H H X : Don’t Care OUTPUT FUNCTION B X Q L L H Qn NO CHANGE CLEAR D X L H X Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/14 74VHC273 Table 4: Absolute Maximum Ratings Symbol VCC VI VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 ± 20 ± 25 ± 75 -65 to +150 300 Unit V V V mA mA mA mA °C °C ICC or IGND DC VCC or Ground Current Storage Temperature Tstg TL Lead Temperature (10 sec) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied Table 5: Recommended Operating Conditions Symbol VCC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time (note 1) (VCC = 3.3 ± 0.3V) (VCC = 5.0 ± 0.5V) Parameter Value 2 to 5.5 0 to 5.5 0 to VCC -55 to 125 0 to 100 0 to 20 Unit V V V °C ns/V 1) VIN from 30% to 70% of VCC 3/14 74VHC273 Table 6: DC Specifications Test Condition Symbol Parameter VCC (V) 2.0 3.0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 4.5 3.0 4.5 VOL Low Level Output Voltage 2.0 3.0 4.5 3.0 4.5 II ICC Input Leakage Current Quiescent Supply Current 0 to 5.5 5.5 IO=-50 µA IO=-50 µA IO=-50 µA IO=-4 mA IO=-8 mA IO=50 µA IO=50 µA IO=50 µA IO=4 mA IO=8 mA VI = 5.5V or GND VI = VCC or GND TA = 25°C Min. 1.5 0.7VCC 0.5 0.3VCC 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 ± 0.1 4 2.0 3.0 4.5 1.9 2.9 4.4 2.48 3.8 0.1 0.1 0.1 0.44 0.44 ±1 40 Typ. Max. Value -40 to 85°C Min. 1.5 0.7VCC 0.5 0.3VCC 1.9 2.9 4.4 2.4 3.7 0.1 0.1 0.1 0.55 0.55 ±1 40 µA µA V V Max. -55 to 125°C Min. 1.5 0.7VCC 0.5 0.3VCC V V Max. Unit VIH High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL VOH 4/14 74VHC273 Table 7: AC Electrical Characteristics (Input tr = tf = 3ns) Test Condition Symbol Parameter VCC (V) 3.3(*) 3.3 5.0 tPHL Propagation Delay Time CLEAR to Q (*) (**) Value TA = 25°C Min. Typ. 8.7 11.2 5.8 7.3 8.9 11.4 5.2 6.7 Max. 13.6 17.1 9.0 11.0 13.6 17.1 8.5 10.5 5.0 5.0 5.5 5.0 5.5 4.5 1.0 1.0 2.5 2.0 -40 to 85°C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max. 16.0 19.5 10.5 12.5 16.0 19.5 10.0 12.0 6.0 5.0 6.5 5.0 6.5 4.5 1.0 1.0 2.5 2.0 65 45 100 70 1.5 1.0 1.5 1.0 65 45 100 70 1.5 1.0 ns MHz -55 to 125°C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max. 16.0 19.5 10.5 12.5 16.0 19.5 10.0 12.0 6.0 5.0 6.5 5.0 6.5 4.5 1.0 1.0 2.5 2.0 ns ns ns ns ns ns Unit CL (pF) 15 50 15 50 15 50 15 50 tPLH tPHL Propagation Delay Time CLOCK to Q 5.0(**) 3.3(*) 3.3(*) 5.0(**) 5.0(**) tW tW CLEAR Pulse Width LOW CLOCK Pulse Width HIGH or LOW Setup Time D to CLOCK, HIGH or LOW Hold Time D to CLOCK, HIGH or LOW Removal Time CLEAR to CLOCK Maximum Clock Frequency 3.3 5.0 (*) (**) 3.3(*) 5.0 (**) ts 3.3(*) 5.0(**) 3.3(*) 5.0(**) 3.3(*) 5.0(**) 3.3(*) 3.3 (*) th tREM fMAX ns 15 50 15 50 50 50 75 50 120 80 120 75 165 110 5.0(**) 5.0(**) tOSLH tOSHL Output to Output Skew time (note 1) 3.3(*) 5.0(**) (*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5.0V ± 0.5V Note 1: Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |tpHLm - tpHLn| Table 8: Capacitive Characteristics Test Condition Symbol Parameter TA = 25°C Min. CIN CPD Input Capacitance Power Dissipation Capacitance (note 1) Typ. 7 31 Max. 10 Value -40 to 85°C Min. Max. 10 -55 to 125°C Min. Max. 10 pF pF Unit 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip-Flop) 5/14 74VHC273 Table 9: Dynamic Switching Characteristics Test Condition Symbol Parameter VCC (V) 5.0 TA = 25°C Min. Typ. 0.6 -0.9 CL = 50 pF 3.5 -0.6 Max. 0.9 V Value -40 to 85°C Min. Max. -55 to 125°C Min. Max. Unit VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 5.0 V 5.0 1.5 V 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. Figure 4: Test Circuit CL =15/50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) 6/14 74VHC273 Figure 5: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle) Figure 6: Waveform - Propagation Delays (f=1MHz; 50% duty cycle) 7/14 74VHC273 Figure 7: Waveform - Recovery Time (f=1MHz; 50% duty cycle) 8/14 74VHC273 SO-20 MECHANICAL DATA DIM. A A1 B C D E e H h L k ddd 10.00 0.25 0.4 0° mm. MIN. 2.35 0.1 0.33 0.23 12.60 7.4 1.27 10.65 0.75 1.27 8° 0.100 0.394 0.010 0.016 0° TYP MAX. 2.65 0.30 0.51 0.32 13.00 7.6 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 8° 0.004 inch TYP. MAX. 0.104 0.012 0.020 0.013 0.512 0.299 0016022D 9/14 74VHC273 TSSOP20 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0˚ 0.45 0.60 0.05 0.8 0.19 0.09 6.4 6.2 4.3 6.5 6.4 4.4 0.65 BSC 8˚ 0.75 0˚ 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 6.6 6.6 4.48 0.002 0.031 0.007 0.004 0.252 0.244 0.169 0.256 0.252 0.173 0.0256 BSC 8˚ 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0079 0.260 0.260 0.176 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0087225C 10/14 74VHC273 Tape & Reel SO-20 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 10.8 13.2 3.1 3.9 11.9 12.8 20.2 60 30.4 11 13.4 3.3 4.1 12.1 0.425 0.520 0.122 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.433 0.528 0.130 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch 11/14 74VHC273 Tape & Reel TSSOP20 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.8 6.9 1.7 3.9 11.9 12.8 20.2 60 22.4 7 7.1 1.9 4.1 12.1 0.268 0.272 0.067 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.276 0.280 0.075 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch 12/14 74VHC273 Table 10: Revision History Date 12-Nov-2004 Revision 5 Description of Changes Order Codes Revision - pag. 1. 13/14 74VHC273 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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