74VHC273TTR

74VHC273 OCTAL D-TYPE FLIP FLOP WITH CLEAR ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 165 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.) DESCRIPTION The 74VHC273 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse. SOP TSSOP ORDER CODES PACKAGE TUBE T&R SOP TSSOP 74VHC273M 74VHC273MTR 74VHC273TTR When the CLEAR input is held low, the Q outputs are held low independently of the other inputs. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS June 2001 1/11 74VHC273 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1 CLEAR 2, 5, 6, 9, 12, 15, 16,19 3, 4, 7, 8, 13, 14, 17, 18 11 Q0 to Q7 Asynchronous Master Reset (Active LOW) Flip-Flop Outputs D0 to D7 Data Inputs CLOCK 10 20 GND VCC Clock Input (LOW-to-HIGH Edge Triggered) Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS OUTPUT FUNCTION CLEAR D B Q L X X L H L H H H X Qn H X : Don’t Care LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/11 CLEAR L NO CHANGE 74VHC273 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Value Unit Supply Voltage -0.5 to +7.0 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage -0.5 to VCC + 0.5 V IIK DC Input Diode Current - 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ± 75 mA ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Value Unit Supply Voltage 2 to 5.5 V VI Input Voltage 0 to 5.5 V VO Output Voltage 0 to VCC V Top Operating Temperature -55 to 125 °C 0 to 100 0 to 20 ns/V dt/dv Input Rise and Fall Time (note 1) (VCC = 3.3 ± 0.3V) (VCC = 5.0 ± 0.5V) 1) VIN from 30% to 70% of V CC 3/11 74VHC273 DC SPECIFICATIONS Test Condition Symbol VIH VIL VOH VOL II ICC 4/11 Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Value TA = 25°C VCC (V) Min. 2.0 3.0 to 5.5 2.0 3.0 to 5.5 Typ. Max. -40 to 85°C -55 to 125°C Min. Min. Max. 1.5 1.5 1.5 0.7VCC 0.7VCC 0.7VCC Unit Max. V 0.5 0.5 0.5 0.3VCC 0.3VCC 0.3VCC V 2.0 IO=-50 µA 1.9 2.0 1.9 1.9 3.0 IO=-50 µA 2.9 3.0 2.9 2.9 4.5 IO=-50 µA 4.4 4.5 3.0 IO=-4 mA 2.58 4.5 IO=-8 mA 3.94 2.0 IO=50 µA 0.0 0.1 0.1 0.1 3.0 IO=50 µA 0.0 0.1 0.1 0.1 4.5 IO=50 µA 0.0 0.1 0.1 0.1 3.0 IO=4 mA 0.36 0.44 0.55 4.5 IO=8 mA 0.36 0.44 0.55 0 to 5.5 VI = 5.5V or GND ± 0.1 ±1 ±1 µA 5.5 VI = VCC or GND 4 40 40 µA 4.4 4.4 2.48 2.4 3.8 V 3.7 V 74VHC273 AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns) Test Condition Symbol tPLH tPHL tPHL tW tW ts th tREM fMAX tOSLH tOSHL Parameter Propagation Delay Time CLOCK to Q Propagation Delay Time CLEAR to Q CLEAR Pulse Width LOW CLOCK Pulse Width HIGH or LOW Setup Time D to CLOCK, HIGH or LOW Hold Time D to CLOCK, HIGH or LOW Removal Time CLEAR to CLOCK Maximum Clock Frequency Output to Output Skew time (note 1) VCC (V) CL (pF) 3.3(*) (*) (**) Value TA = 25°C -55 to 125°C Typ. Max. Min. Max. Min. Max. 15 8.7 13.6 1.0 16.0 1.0 16.0 50 11.2 17.1 1.0 19.5 1.0 19.5 5.0 15 5.8 9.0 1.0 10.5 1.0 10.5 5.0(**) 50 7.3 11.0 1.0 12.5 1.0 12.5 3.3(*) 15 8.9 13.6 1.0 16.0 1.0 16.0 (*) 50 11.4 17.1 1.0 19.5 1.0 19.5 (**) 5.0 15 5.2 8.5 1.0 10.0 1.0 10.0 5.0(**) 50 6.7 10.5 1.0 12.0 1.0 12.0 3.3 3.3 Min. -40 to 85°C 3.3(*) 5.0 6.0 6.0 5.0(**) 5.0 5.0 5.0 3.3(*) 5.5 6.5 6.5 5.0(**) 5.0 5.0 5.0 3.3(*) 5.5 6.5 6.5 5.0(**) 4.5 4.5 4.5 3.3(*) 1.0 1.0 1.0 5.0(**) 1.0 1.0 1.0 3.3(*) 2.5 2.5 2.5 (**) 2.0 2.0 2.0 5.0 3.3(*) 15 (*) 50 50 75 45 45 5.0(**) 15 120 165 100 100 5.0(**) 50 80 110 70 70 3.3(*) 50 1.5 1.5 1.5 (**) 50 1.0 1.0 1.0 3.3 5.0 75 120 65 Unit ns ns ns ns ns ns ns 65 MHz ns (*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5.0V ± 0.5V Note 1 : Parameter guaranteed by design. tsoLH = |t pLHm - t pLHn|, t soHL = |tpHLm - tpHLn | CAPACITIVE CHARACTERISTICS Test Condition Symbol Value TA = 25°C Parameter Typ. Max. CIN Input Capacitance Min. 7 10 CPD Power Dissipation Capacitance (note 1) 31 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip-Flop) 5/11 74VHC273 DYNAMIC SWITCHING CHARACTERISTICS Test Condition Symbol VOLP VOLV VIHD VILD Parameter Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) TA = 25°C VCC (V) Min. 5.0 5.0 Value -0.9 CL = 50 pF 5.0 Typ. Max. 0.6 0.9 -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. V -0.6 3.5 V 1.5 V 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. TEST CIRCUIT CL =15/50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) 6/11 74VHC273 WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 7/11 74VHC273 WAVEFORM 3: RECOVERY TIME (f=1MHz; 50% duty cycle) 8/11 74VHC273 SO-20 MECHANICAL DATA mm. inch DIM. MIN. TYP A a1 MAX. MIN. TYP. 2.65 0.1 0.104 0.2 a2 MAX. 0.004 0.008 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 C 0.5 0.020 c1 45° (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.300 L 0.50 1.27 0.020 0.050 M S 0.75 0.029 8° (max.) PO13L 9/11 74VHC273 TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0° L 0.45 A 0.0256 BSC 0.60 8° 0° 0.75 0.018 8° 0.024 0.030 A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 0087225C 10/11 74VHC273 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom © http://www.st.com 11/11