74VHC374MTR

74VHC374 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUTS NON INVERTING ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 270 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 374 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.) SOP SOP TSSOP t c u d o r P e t e l o e t e ol Pr T&R 74VHC374MTR 74VHC374TTR While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. The Output control does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. ) (s DESCRIPTION The 74VHC374 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs. u d o Table 1: Order Codes PACKAGE ) s ( ct TSSOP s b O s b O Figure 1: Pin Connection And IEC Logic Symbols November 2004 Rev. 4 1/14 74VHC374 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N° SYMBOL 1 OE 2, 5, 6, 9, 12, 15, 16,19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 Q0 to Q7 3 State Output Enable Input (Active LOW) 3-State Outputs D0 to D7 Data Inputs CK GND VCC NAME AND FUNCTION Clock Ground (0V) Positive Supply Voltage ) s ( ct Table 3: Truth Table u d o INPUTS OUTPUT OE CK D H X X L X L L o s b L H O ) X : Don’t Care Z : High Impedance Figure 3: Logic Diagram s ( t c u d o r P e t e l o s b O This logic diagram has not be used to estimate propagation delays 2/14 e t e l Pr Q Z NO CHANGE L H 74VHC374 Table 4: Absolute Maximum Ratings Symbol VCC Parameter Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current Unit -0.5 to +7.0 V -0.5 to +7.0 V -0.5 to VCC + 0.5 - 20 V mA ± 20 mA ICC or IGND DC VCC or Ground Current Storage Temperature Tstg TL Value ± 25 mA ± 75 mA ) s ( ct -65 to +150 Lead Temperature (10 sec) 300 °C °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied Table 5: Recommended Operating Conditions Symbol VCC Unit 0 to 5.5 V 0 to VCC V -55 to 125 °C 0 to 100 0 to 20 ns/V Value let Supply Voltage Input Voltage VO Output Voltage Top Operating Temperature dt/dv r P e Parameter VI O ) o s b Input Rise and Fall Time (note 1) (VCC = 3.3 ± 0.3V) (VCC = 5.0 ± 0.5V) u d o 2 to 5.5 V s ( t c 1) VIN from 30% to 70% of VCC u d o r P e t e l o s b O 3/14 74VHC374 Table 6: DC Specifications Test Condition Symbol VIH VIL VOH VOL IOZ II ICC Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Quiescent Supply Current s b O 4/14 TA = 25°C VCC (V) Min. 2.0 3.0 to 5.5 2.0 3.0 to 5.5 Typ. Max. -40 to 85°C -55 to 125°C Min. Min. Max. 1.5 1.5 1.5 0.7VCC 0.7VCC 0.7VCC Unit Max. V 0.5 0.5 0.5 0.3VCC 0.3VCC 0.3VCC 2.0 IO=-50 µA 1.9 2.0 1.9 1.9 3.0 IO=-50 µA 2.9 3.0 2.9 2.9 4.5 IO=-50 µA 4.4 4.5 4.4 4.4 3.0 IO=-4 mA 2.58 2.48 2.4 4.5 IO=-8 mA 3.94 3.8 2.0 IO=50 µA 0.0 0.1 3.0 IO=50 µA 0.0 0.1 4.5 IO=50 µA 0.0 3.0 IO=4 mA 4.5 IO=8 mA 5.5 VI = VIH or VIL VO = VCC or GND 0 to 5.5 5.5 t e l o V 3.7 0.1 0.1 0.1 0.1 0.1 0.1 0.44 0.55 0.36 0.44 0.55 ±0.25 ± 2.5 ± 2.5 µA VI = 5.5V or GND ± 0.1 ±1 ±1 µA VI = VCC or GND 4 40 40 µA t c u ) (s 0.1 ) s ( ct u d o r P e V 0.36 d o r P e t e l o Value s b O V 74VHC374 Table 7: AC Electrical Characteristics (Input tr = tf = 3ns) Test Condition Symbol Parameter VCC (V) CL (pF) tPLH tPHL Propagation Delay Time CK to Q 3.3(*) (*) (**) tPLZ tPHZ tw ts th fMAX tOSLH tOSHL Output Enable Time Output Disable Time Clock Pulse Width HIGH or LOW Setup Time D to CK HIGH or LOW Hold Time D to CK HIGH or LOW Maximum Clock Frequency Output to Output Skew time (note 1) TA = 25°C -55 to 125°C Max. Min. Max. Min. Max. 15 8.1 12.7 1.0 15.0 1.0 15.0 50 10.6 16.2 1.0 18.5 1.0 18.5 15 5.4 8.1 1.0 9.5 1.0 9.5 5.0(**) 50 6.9 10.1 1.0 11.5 1.0 11.5 3.3(*) 15 RL = 1KΩ 7.1 11.0 1.0 13.0 1.0 13.0 3.3(*) 50 RL = 1KΩ 9.6 14.5 1.0 16.5 1.0 16.5 5.0(**) 15 RL = 1KΩ 5.1 7.6 1.0 9.0 1.0 9.0 5.0(**) 3.3 Min. -40 to 85°C Typ. 5.0 tPZL tPZH Value RL = 1KΩ 6.6 9.6 1.0 11.0 1.0 15 RL = 1KΩ 10.2 14.0 1.0 16.0 1.0 16.0 (*) 50 RL = 1KΩ 6.1 8.8 1.0 10.0 1.0 10.0 3.3 3.3(*) 5.0 5.0(**) 5.0 3.3(*) ) (s 5.0(**) 3.3(*) 5.0 t c u (**) 3.3(*) 50 (**) 50 5.0 5.5 5.0 5.0 so 4.5 4.5 3.0 3.0 2.0 2.0 2.0 2.0 2.0 2.0 3.0 b O 3.3(*) 60 250 60 60 100 270 100 100 od r P e Pr 11.0 5.5 4.5 5.0(**) e t e l ns ) s ( ct u d o 50 (*) 3.3 Unit ns ns ns ns ns MHz 1.5 1.5 1.5 1.0 1.0 1.0 ns (*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5.0V ± 0.5V Note 1: Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |tpHLm - tpHLn| t e l o Table 8: Capacitive Characteristics s b O Symbol CIN COUT CPD Parameter Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) Test Condition Value TA = 25°C Min. Typ. Max. 7 10 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF 9 pF 32 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip-Flop) 5/14 74VHC374 Table 9: Dynamic Switching Characteristics Test Condition Symbol VOLP Parameter VIHD VILD TA = 25°C VCC (V) Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) VOLV Value Min. 5.0 5.0 -0.9 CL = 50 pF Typ. Max. 0.6 0.9 -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. V -0.6 3.5 5.0 V ) s ( ct 1.5 V u d o 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD ), 0V to threshold (VIHD), f=1MHz. r P e Figure 4: Test Circuit t e l o ) (s s b O t c u d o r P e t e l o bs TEST SWITCH O Open tPZL, tPLZ VCC tPZH, tPHZ GND tPLH, tPHL CL =15/50pF or equivalent (includes jig and probe capacitance) RL = R1 = 1KΩ or equivalent RT = ZOUT of pulse generator (typically 50Ω) 6/14 74VHC374 Figure 5: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle) ) s ( ct u d o r P e t e l o ) (s s b O t c u Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle) d o r P e t e l o s b O 7/14 74VHC374 Figure 7: Waveform - Pulse Width (f=1mhz; 50% Duty Cycle) ) s ( ct u d o r P e t e l o ) (s t c u d o r P e t e l o s b O 8/14 s b O 74VHC374 SO-20 MECHANICAL DATA mm. DIM. MIN. inch TYP MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.1 0.30 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.60 13.00 0.496 0.512 E 7.4 7.6 0.291 e 1.27 ) s ( ct 0.299 o r P 0.050 e t e ol H 10.00 10.65 0.394 h 0.25 0.75 0.010 L 0.4 1.27 k 0° 8° (s) ddd 0.100 -O bs du 0.419 0.030 0.016 0.050 0° 8° 0.004 t c u d o r P e t e l o s b O 0016022D 9/14 74VHC374 TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 c 0.09 0.20 0.004 D 6.4 6.5 6.6 0.252 E 6.2 6.4 6.6 0.244 E1 4.3 4.4 4.48 0.169 1 e K 0˚ L 0.45 r P e let o s b 0.60 0.75 s ( t c r P e 0.256 t e l o 0.260 0.252 0.260 0.173 0.176 0.0256 BSC 0˚ 8˚ 0.018 0.024 0.030 u d o A2 A O ) 8˚ u d o 0.0079 bs 0.65 BSC ) s ( ct 0.012 A1 b O K e L E c D E1 PIN 1 IDENTIFICATION 1 0087225C 10/14 74VHC374 Tape & Reel SO-20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 330 13.2 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 0.504 0.519 ) s ( ct 30.4 1.197 Ao 10.8 11 0.425 Bo 13.2 13.4 0.520 Ko 3.1 3.3 0.122 Po 3.9 4.1 0.153 P 11.9 12.1 0.468 ) (s 0.433 ro P e let so b O du 0.528 0.130 0.161 0.476 t c u d o r P e t e l o s b O 11/14 74VHC374 Tape & Reel TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A TYP. MAX. 330 13.2 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 0.504 0.519 ) s ( ct 22.4 0.882 Ao 6.8 7 0.268 Bo 6.9 7.1 0.272 Ko 1.7 1.9 0.067 Po 3.9 4.1 0.153 P 11.9 12.1 0.468 ) (s t c u d o r P e t e l o s b O 12/14 MIN. 0.276 ro P e let so b O du 0.280 0.075 0.161 0.476 74VHC374 Table 10: Revision History Date Revision 12-Nov-2004 4 Description of Changes Order Codes Revision - pag. 1. ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 13/14 74VHC374 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. 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