74VHC574TTR

74VHC574 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUTS NON INVERTING ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 180 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 574 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.) DESCRIPTION The 74VHC574 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type flip-flop is controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic states that were setup at the D inputs. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and SOP TSSOP Table 1: Order Codes PACKAGE T&R SOP TSSOP 74VHC574MTR 74VHC574TTR while high level the outputs will be in a high impedance state. The Output control does not affect the internal operation of flip flop; that is, the old data can be retained or the new data can be entered even while the outputs are off. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Figure 1: Pin Connection And IEC Logic Symbols November 2004 Rev. 4 1/14 74VHC574 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N° SYMBOL 1 OE 2, 3, 4, 5, 6, 7, 8, 9 12, 13, 14, 15, 16, 17, 18, 19 11 D0 to D7 3-State Output Enable Input (Active LOW) Data Inputs Q0 to Q7 3-State Outputs 10 20 CK GND VCC NAME AND FUNCTION Clock Input (LOW-to-HIGH Edge Triggered) Ground (0V) Positive Supply Voltage Table 3: Truth Table INPUTS OE CK D Q H X X Z L X NO CHANGE L L L L H H X : Don’t Care Z : High Impedance Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/14 OUTPUT 74VHC574 Table 4: Absolute Maximum Ratings Symbol VCC Parameter Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current ICC or IGND DC VCC or Ground Current Storage Temperature Tstg TL Lead Temperature (10 sec) Value Unit -0.5 to +7.0 V -0.5 to +7.0 V -0.5 to VCC + 0.5 - 20 V mA ± 20 mA ± 25 mA ± 75 mA -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied Table 5: Recommended Operating Conditions Symbol VCC Parameter Supply Voltage Value Unit 2 to 5.5 V VI Input Voltage 0 to 5.5 V VO Output Voltage 0 to VCC V Top Operating Temperature -55 to 125 °C 0 to 100 0 to 20 ns/V dt/dv Input Rise and Fall Time (note 1) (VCC = 3.3 ± 0.3V) (VCC = 5.0 ± 0.5V) 1) VIN from 30% to 70% of VCC 3/14 74VHC574 Table 6: DC Specifications Test Condition Symbol VIH VIL VOH VOL IOZ II ICC 4/14 Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Quiescent Supply Current Value TA = 25°C VCC (V) Min. 2.0 3.0 to 5.5 2.0 3.0 to 5.5 Typ. Max. -40 to 85°C -55 to 125°C Min. Min. Max. 1.5 1.5 1.5 0.7VCC 0.7VCC 0.7VCC Max. V 0.5 0.5 0.5 0.3VCC 0.3VCC 0.3VCC 2.0 IO=-50 µA 1.9 2.0 1.9 1.9 3.0 IO=-50 µA 2.9 3.0 2.9 2.9 4.5 IO=-50 µA 4.4 4.5 3.0 IO=-4 mA 2.58 3.94 4.4 4.4 2.48 2.4 Unit V V 4.5 IO=-8 mA 2.0 IO=50 µA 0.0 0.1 0.1 0.1 3.0 IO=50 µA 0.0 0.1 0.1 0.1 4.5 IO=50 µA 0.0 0.1 0.1 0.1 3.0 IO=4 mA 0.36 0.44 0.55 4.5 IO=8 mA 0.36 0.44 0.55 5.5 VI = VIH or VIL VO = VCC or GND ±0.25 ± 2.5 ± 2.5 µA 0 to 5.5 VI = 5.5V or GND ± 0.1 ±1 ±1 µA 5.5 VI = VCC or GND 4 40 40 µA 3.8 3.7 V 74VHC574 Table 7: AC Electrical Characteristics (Input tr = tf = 3ns) Test Condition Symbol Parameter VCC (V) CL (pF) tPLH tPHL Propagation Delay Time CH to Q 3.3(*) (*) (**) tPLZ tPHZ tw ts th fMAX Output Enable Time Output Disable Time Clock Pulse Width HIGH or LOW Setup Time D to CK HIGH or LOW Hold Time D to CK HIGH or LOW Maximum Clock Frequency Output to Output Skew time (note 1) -55 to 125°C Min. Max. Min. Max. 15 8.5 13.2 1.0 15.5 1.0 15.5 50 11.0 16.7 1.0 19.0 1.0 19.0 15 5.6 8.6 1.0 10.0 1.0 10.0 5.0(**) 50 7.1 10.6 1.0 12.0 1.0 12.0 3.3(*) 15 8.2 12.8 1.0 15.0 1.0 15.0 3.3(*) 50 10.7 16.3 1.0 18.5 1.0 18.5 5.0(**) 15 5.9 9.0 1.0 10.5 1.0 10.5 5.0(**) 50 7.4 11.0 1.0 12.5 1.0 12.5 (*) 50 11.0 15.0 1.0 17.0 1.0 17.0 (*) 50 7.1 10.1 1.0 11.5 1.0 11.5 3.3 3.3 3.3 Min. -40 to 85°C Max. 3.3(*) 5.0 5.0 5.0 5.0(**) 5.0 5.0 5.0 3.3(*) 3.5 3.5 3.5 5.0(**) 3.5 3.5 3.5 3.3(*) 1.5 1.5 1.5 5.0(**) 1.5 1.5 1.5 3.3(*) 15 80 125 65 65 (*) 50 50 75 45 45 (**) 15 130 180 110 110 5.0(**) 50 85 115 75 75 3.3(*) 50 1.5 1.5 1.5 5.0(**) 50 1.0 1.0 1.0 3.3 5.0 tOSLH tOSHL TA = 25°C Typ. 5.0 tPZL tPZH Value Unit ns ns ns ns ns ns MHz ns (*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5.0V ± 0.5V Note 1: Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |tpHLm - tpHLn| Table 8: Capacitive Characteristics Test Condition Symbol Parameter Value TA = 25°C Min. CIN Input Capacitance COUT Output Capacitance Power Dissipation Capacitance (note 1) CPD Typ. Max. 7 10 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF 9 pF 28 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip-Flop) 5/14 74VHC574 Table 9: Dynamic Switching Characteristics Test Condition Symbol VOLP VOLV VIHD VILD Parameter Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) TA = 25°C VCC (V) Min. 5.0 5.0 Value -0.9 CL = 50 pF 5.0 Typ. Max. 0.6 0.9 -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. V -0.6 3.5 V 1.5 V 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD ), 0V to threshold (VIHD), f=1MHz. Figure 4: Test Circuit TEST tPLH, tPHL SWITCH Open tPZL, tPLZ VCC tPZH, tPHZ GND CL =15/50pF or equivalent (includes jig and probe capacitance) RL = R1 = 1KΩ or equivalent RT = ZOUT of pulse generator (typically 50Ω) 6/14 74VHC574 Figure 5: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle) Figure 6: Waveform 2: Output Enable And Disable Times (f=1MHz; 50% duty cycle) 7/14 74VHC574 Figure 7: Waveform - Pulse Width (f=1MHz; 50% duty cycle) 8/14 74VHC574 SO-20 MECHANICAL DATA DIM. mm. MIN. TYP inch MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.1 0.30 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.60 13.00 0.496 0.512 E 7.4 7.6 0.291 0.299 e 1.27 0.050 H 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 k 0° 8° 0° 8° ddd 0.100 0.004 0016022D 9/14 74VHC574 TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0˚ L 0.45 A 0.0256 BSC 0.60 8˚ 0˚ 0.75 0.018 8˚ 0.024 0.030 A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 0087225C 10/14 74VHC574 Tape & Reel SO-20 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 30.4 0.519 1.197 Ao 10.8 11 0.425 0.433 Bo 13.2 13.4 0.520 0.528 Ko 3.1 3.3 0.122 0.130 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 11/14 74VHC574 Tape & Reel TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. A MAX. MIN. 330 13.2 TYP. MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 12/14 TYP 0.504 22.4 0.519 0.882 Ao 6.8 7 0.268 0.276 Bo 6.9 7.1 0.272 0.280 Ko 1.7 1.9 0.067 0.075 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 74VHC574 Table 10: Revision History Date Revision 12-Nov-2004 4 Description of Changes Order Codes Revision - pag. 1. 13/14 74VHC574 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. 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