74VHCT273AMTR

74VHCT273A OCTAL D-TYPE FLIP FLOP WITH CLEAR ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 170 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN.), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.) DESCRIPTION The 74VHCT273A is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. Information signals applied to D inputs are transferred to the Q outputs on the positive going SOP TSSOP Table 1: Order Codes PACKAGE T&R SOP TSSOP 74VHCT273AMTR 74VHCT273ATTR edge of the clock pulse. When the CLEAR input is held low, the Q outputs are held low independently of the other inputs. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V since all inputs are equipped with TTL threshold. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Figure 1: Pin Connection And IEC Logic Symbols December 2004 Rev. 3 1/13 74VHCT273A Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N° SYMBOL NAME AND FUNCTION 1 CLEAR 2, 5, 6, 9, 12, 15, 16,19 3, 4, 7, 8, 13, 14, 17, 18 11 Q0 to Q7 Asynchronous Master Reset (Active LOW) Flip-Flop Outputs D0 to D7 Data Inputs CLOCK 10 20 GND VCC Clock Input (LOW-to-HIGH Edge Triggered) Ground (0V) Positive Supply Voltage Table 3: Truth Table INPUTS OUTPUT FUNCTION CLEAR D CLOCK X L X H L L H H H H X Qn X: Don’t care Table 4: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/13 Q L CLEAR NO CHANGE 74VHCT273A Table 5: Absolute Maximum Ratings Symbol VCC Parameter Value Unit Supply Voltage -0.5 to +7.0 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage (see note 1) -0.5 to +7.0 V VO DC Output Voltage (see note 2) IIK DC Input Diode Current -0.5 to VCC + 0.5 - 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) V ± 50 mA -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) VCC = 0V 2) High or Low State Table 6: Recommended Operating Conditions Symbol VCC Parameter Supply Voltage Value Unit 4.5 to 5.5 V VI Input Voltage 0 to 5.5 V VO Output Voltage (see note 1) 0 to 5.5 V VO Output Voltage (see note 2) 0 to VCC V Top Operating Temperature -55 to 125 °C 0 to 20 ns/V dt/dv Input Rise and Fall Time (see note 3) (VCC = 5.0 ± 0.5V) 1) VCC = 0V 2) High or Low State 3) VIN from 0.8V to 2V 3/13 74VHCT273A Table 7: DC Specifications Test Condition Symbol VIH VIL VOH VOL II ICC +ICC IOPD Parameter TA = 25°C VCC (V) High Level Input Voltage Low Level Input Voltage High Level Output Voltage 4.5 to 5.5 4.5 to 5.5 Value Min. Typ. Max. 2 -40 to 85°C -55 to 125°C Min. Min. Max. 2 0.8 Max. 2 0.8 Unit V 0.8 V 4.5 IO=-50 µA 4.4 4.5 IO=-8 mA 3.94 Low Level Output Voltage 4.5 IO=50 µA 0.1 0.1 0.1 4.5 IO=8 mA 0.36 0.44 0.55 Input Leakage Current Quiescent Supply Current Additional Worst Case Supply Current 0 to 5.5 VI = 5.5V or GND ± 0.1 ± 1.0 ± 1.0 µA 5.5 VI = VCC or GND 4 40 40 µA 5.5 One Input at 3.4V, other input at VCC or GND 1.35 1.5 1.5 mA 0 VOUT = 5.5V 0.5 5.0 5.0 µA Output Leakage Current 4.5 0.0 4.4 4.4 3.8 3.7 V V Table 8: AC Electrical Characteristics (Input tr = tf = 3ns) Test Condition Value TA = 25°C Symbol Parameter VCC (V) CL (pF) tPLH tPHL Propagation Delay Time CLOCK to Q 5.0(**) (**) tPHL Propagation Delay Time CLEAR to Q CLR Pulse Width LOW CK Pulse Width HIGH or LOW Setup Time D to CLOCK, HIGH or LOW Hold Time D to CK, HIGH or LOW Removal Time CLR to CLOCK Maximum Clock Frequency 5.0(**) 5.0 5.0 5.0 ns 5.0(**) 5.0 5.0 5.0 ns 5.0(**) 2.0 2.0 2.0 ns 5.0(**) 2.0 2.0 2.0 ns 5.0(**) 1.0 1.0 1.0 ns tW tW ts th tREM fMAX tOSLH tOSHL Output to Output Skew time (note 1) Max. Min. Max. Min. Max. 15 5.8 8.2 1.0 10.0 1.0 10.0 50 6.8 9.2 1.0 11.0 1.0 11.0 5.0(**) 15 7.5 10.0 1.0 11.6 1.0 11.6 (**) 50 8.5 11.0 1.0 12.6 1.0 12.6 5.0 5.0(**) 15 75 170 65 65 5.0(**) 50 50 160 45 45 5.0(**) 50 (*) Voltage range is 5.0V ± 0.5V Note 1: Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |tpHLm - tpHLn| 4/13 -55 to 125°C Typ. 5.0 Min. -40 to 85°C 1.0 1.0 Unit ns ns MHz 1.0 ns 74VHCT273A Table 9: Capacitive Characteristics Test Condition Symbol Value TA = 25°C Parameter Min. Typ. Max. 10 CIN Input Capacitance 6 CPD Power Dissipation Capacitance (note 1) 16 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip-Flop) Table 10: Dynamic Switching Characteristics Test Condition Symbol VOLP VOLV VIHD VILD Parameter Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) TA = 25°C VCC (V) Min. 5.0 5.0 Value -0.9 CL = 50 pF 5.0 Typ. Max. 0.6 0.9 -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. -0.6 V 2.0 0.8 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.0V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.0V. Inputs under test switching: 3.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. Figure 3: Test Circuit CL =15/50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) 5/13 74VHCT273A Figure 4: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle) Figure 5: Waveform - Propagation Delays (f=1MHz; 50% duty cycle) 6/13 74VHCT273A Figure 6: Waveform - Recovery Time (f=1MHz; 50% duty cycle) 7/13 74VHCT273A SO-20 MECHANICAL DATA DIM. mm. MIN. TYP inch MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.1 0.30 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.60 13.00 0.496 0.512 E 7.4 7.6 0.291 0.299 e 1.27 0.050 H 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 k 0° 8° 0° 8° ddd 0.100 0.004 0016022D 8/13 74VHCT273A TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0˚ L 0.45 A 0.0256 BSC 0.60 8˚ 0˚ 0.75 0.018 8˚ 0.024 0.030 A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 0087225C 9/13 74VHCT273A Tape & Reel SO-20 MECHANICAL DATA mm. inch DIM. MIN. A MAX. MIN. 330 13.2 TYP. MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 10/13 TYP 0.504 30.4 0.519 1.197 Ao 10.8 11 0.425 0.433 Bo 13.2 13.4 0.520 0.528 Ko 3.1 3.3 0.122 0.130 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 74VHCT273A Tape & Reel TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 22.4 0.519 0.882 Ao 6.8 7 0.268 0.276 Bo 6.9 7.1 0.272 0.280 Ko 1.7 1.9 0.067 0.075 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 11/13 74VHCT273A Table 11: Revision History Date Revision 16-Dec-2004 3 12/13 Description of Changes Order Codes Revision - pag. 1. 74VHCT273A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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