74VHCT27A

® 74VHCT27A TRIPLE 3-INPUT NOR GATE PRELIMINARY DATA s s s s s s s s s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 27 IMPROVED LATCH-UP IMMUNITY SOP PACKAGE SOP TSSOP T UBE 74VHCT27AM TSSOP T&R 74VHCT27AMTR 74VHCT27ATTR ORDER CODES DESCRIPTION The 74VHCT27A is an advanced high-speed CMOS TRIPLE 3-INPUT NOR GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which provides high noise immunity and stable output. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS February 2000 1/7 74VHCT27A INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 3, 9 2, 4, 10 13, 5, 11 12, 6, 8 7 14 SYMBOL 1A to 3A 1B to 3B 1C to 3C 1Y to 3Y GND VCC NAME AND FUNCT ION Data Inputs Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A L H X X X:”H” or ”L” B L X H X C L X X H Y H L L L ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage (see note 1) DC Output Voltage (see note 2) DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 ± 20 ± 25 ± 50 -65 to +150 300 Unit V V V V mA mA mA mA o o ICC or IGND DC VCC or Ground Current C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. 1) VCC =0V 2) High or Low State RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO VO Top dt/dv Supply Voltage Input Voltage Output Voltage (see note 1) Output Voltage (see note 2) Operating Temperature Input Rise and Fall Time (see note 3) (V CC = 5.0 ± 0.5V) Parameter Valu e 4.5 to 5.5 0 to 5.5 0 to 5.5 0 to VCC -40 to +85 0 to 20 Unit V V V V o C ns/V 1) VCC =0V 2) High or Low State 3)VIN from0.8V to 2 V 2/7 74VHCT27A DC SPECIFICATIONS Symb ol Parameter T est Cond ition s V CC (V) VIH VIL VOH VOL II ICC ∆ICC High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Additional Worst Case Supply Current Output Leakage Current 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 0 to 5.5 5.5 5.5 I O =-50 µ A IO=-8 mA I O=50 µ A IO=8 mA VI = 5.5V or GND VI = VCC or GND One Input at 3.4V, other input at VCC or GND VOUT = 5.5V 4.4 3.94 0.0 0.1 0.36 ±0.1 2 1.35 4.5 Min. 2 0.8 4.4 3.8 0.1 0.44 ±1.0 20 1.5 Typ . Value T A = 25 o C Max. -40 to 85 o C Min . 2 0.8 Max. V V Un it V V µA µA mA IOPD 0 0.5 5.0 µA AC ELECTRICAL CHARACTERISTICS (Input t r = tf =3 ns) Symb ol Parameter Test Co ndition V CC (*) CL (pF ) (V) 5.0 5.0 15 50 Value T A = 25 o C Min. Typ . Max. 5.2 7.0 5.8 8.0 Un it -40 to 85 o C Min . Max. 1.0 8.0 1.0 9.0 tPLH tPHL Propagation Delay Time ns (*) Voltage range is 5V ± 0.5V CAPACITIVE CHARACTERISTICS Symb ol Parameter T est Cond ition s Min. C IN CPD Input Capacitance Power Dissipation Capacitance (note 1) Typ . 6 18 Value T A = 25 o C Max. 10 -40 to 85 o C Min . Max. 10 pF pF Un it 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/3 (per Gate) 3/7 74VHCT27A TEST CIRCUIT CL = 15/50 pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 4/7 74VHCT27A SO-14 MECHANICAL DATA DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 8.55 5.8 1.27 7.62 4.0 5.3 1.27 0.68 8 (max.) 0.149 0.181 0.019 8.75 6.2 0.35 0.19 0.5 45 (typ.) 0.336 0.228 0.050 0.300 0.157 0.208 0.050 0.026 0.344 0.244 0.1 mm TYP. MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 P013G 5/7 74VHCT27A TSSOP14 MECHANICAL DATA mm MIN. A A1 A2 b c D E E1 e K L 0o 0.50 0.05 0.85 0.19 0.09 4.9 6.25 4.3 5 6.4 4.4 0.65 BSC 4o 0.60 8o 0.70 0o 0.020 0.10 0.9 TYP. MAX. 1.1 0.15 0.95 0.30 0.20 5.1 6.5 4.48 0.002 0.335 0.0075 0.0035 0.193 0.246 0.169 0.197 0.252 0.173 0.0256 BSC 4o 0.024 8o 0.028 0.004 0.354 MIN. inch TYP. MAX. 0.433 0.006 0.374 0.0118 0.0079 0.201 0.256 0.176 DIM. A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 6/7 74VHCT27A Information furnished is believed to be accurate and reliable. However, STMicroelectronic s assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com . 7/7