A3G4250D
MEMS motion sensor:
3-axis digital output gyroscope
Features
■
Wide supply voltage: 2.4 V to 3.6 V
■
±245 dps full scale
■
I2C/SPI digital output interface
■
16-bit rate value data output
■
8-bit temperature data output
■
Two digital output lines (interrupt and data
ready)
■
Integrated low and high-pass filters with userselectable bandwidth
■
Ultra-stable over temperature and time
■
Low-voltage-compatible IOs (1.8 V)
■
Embedded power-down and sleep mode
■
Embedded temperature sensor
■
Embedded FIFO
■
High shock survivability
■
Extended operating temperature range (-40 °C
to +85 °C)
■
ECOPACK® RoHS and “Green” compliant
■
AEC-Q100 qualification
LGA-16 (4x4x1.1 mm3)
The A3G4250D is a low-power 3-axis angular rate
sensor able to provide unprecedented stability at
zero rate level and sensitivity over temperature
and time. It includes a sensing element and an IC
interface capable of providing the measured
angular rate to the external world through a
standard SPI digital interface. An I2C-compatible
interface is also available.
The sensing element is manufactured using a
dedicated micro-machining process developed by
STMicroelectronics to produce inertial sensors
and actuators on silicon wafers.
The IC interface is manufactured using a CMOS
process that allows a high level of integration to
design a dedicated circuit which is trimmed to
better match the sensing element characteristics.
Applications
■
In-dash car navigation
■
Telematics, e-Tolling
■
Motion control with MMI (man-machine
interface)
■
Appliances and robotics
Table 1.
Description
The A3G4250D has a full scale of ±245 dps and
is capable of measuring rates with a userselectable bandwidth.
The A3G4250D is available in a plastic land grid
array (LGA) package and can operate within a
temperature range of -40 °C to +85 °C.
Device summary
Order code
Temperature range (°C)
Package
A3G4250D
-40 to +85
LGA-16 (4x4x1.1 mm3)
-40 to +85
mm3)
A3G4250DTR
February 2012
LGA-16 (4x4x1.1
Doc 022768 Rev 3
Packing
Tray
Tape and reel
1/44
www.st.com
44
Contents
A3G4250D
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
2
Mechanical and electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.1
SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.2
I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7
3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.6.1
Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6.2
Zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6.3
Stability over temperature and time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Main digital blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.1
Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.2
FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.3
Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.4
Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1
I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.1
5.2
2/44
I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.1
SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.2
SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Doc 022768 Rev 3
A3G4250D
Contents
5.2.3
SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6
Output register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1
WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2
CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3
CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.4
CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.5
CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.6
CTRL_REG5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.7
REFERENCE/DATACAPTURE (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.8
OUT_TEMP (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.9
STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.10
OUT_X_L (28h), OUT_X_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.11
OUT_Y_L (2Ah), OUT_Y_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.12
OUT_Z_L (2Ch), OUT_Z_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.13
FIFO_CTRL_REG (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.14
FIFO_SRC_REG (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.15
INT1_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.16
INT1_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.17
INT1_THS_XH (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.18
INT1_THS_XL (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.19
INT1_THS_YH (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.20
INT1_THS_YL (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.21
INT1_THS_ZH (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.22
INT1_THS_ZL (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.23
INT1_DURATION (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Doc 022768 Rev 3
3/44
List of tables
A3G4250D
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
4/44
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Filter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Temp. sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PLL low-pass filter component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
I2C terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SAD+read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 23
Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 23
Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DR and BW configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power mode selection configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
High-pass filter cut-off frequency configuration [Hz] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CTRL_REG4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Self-test mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CTRL_REG5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Out_Sel configuration settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
INT_SEL configuration settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
OUT_TEMP register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
OUT_TEMP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STATUS_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FIFO_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FIFO_SRC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
INT1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Doc 022768 Rev 3
A3G4250D
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
List of tables
INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
INT1_THS_XH register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
INT1_THS_XH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
INT1_THS_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
INT1_THS_XL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
INT1_THS_YH register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
INT1_THS_YH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
INT1_THS_YL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
INT1_THS_YL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
INT1_THS_ZH register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
INT1_THS_ZH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
INT1_THS_ZL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
INT1_THS_ZL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
INT1_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Doc 022768 Rev 3
5/44
List of figures
A3G4250D
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
6/44
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
A3G4250D external low-pass filter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
FIFO access sequence in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
A3G4250D electrical connections and external component values . . . . . . . . . . . . . . . . . . 19
Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Multiple byte SPI read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Multiple byte SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
INT1_Sel and Out_Sel configuration block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Wait disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Wait enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
LGA-16: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Doc 022768 Rev 3
A3G4250D
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
Block diagram
+Ω
x,y,z
X+
CHARGE
AMP
Y+
MIXER
LOW-PASS
FILTER
D
I
G
I
T
A
L
Z+
A
D
C
1
M
U
X
ZYX-
T
E
M
P
E
R
A
T
U
R
E
DRIVING MASS
Feedback loop
REFERENCE
TRIMMING
CIRCUITS
FIFO
S
E
N
S
O
R
F
I
L
T
E
R
I
N
G
I2C
SPI
CS
SCL/SPC
SDA/SDO/SDI
SDO
A
D
C
2
INT1
CONTROL LOGIC
&
INTERRUPT GEN.
CLOCK
&
PHASE GENERATOR
DRDY/INT2
AM07225v1
The vibration of the structure is maintained by drive circuitry in a feedback loop. The sensing
signal is filtered and appears as a digital signal at the output.
1.1
Pin description
Figure 2.
Pin connection
13
RES
1
BOTTOM
VIEW
RES
X
RES
9
SDA/SDI/SDO
SDO/SA0
5
CS
DRDY/INT2
INT
Doc 022768 Rev 3
Vdd_IO
SCL/SPC
4
8
RES
(TOP VIEW)
DIRECTIONS OF THE
DETECTABLE
ANGULAR RATES
16
12
RES
+Ω
Vdd
+Ω
Y
RES
X
GND
1
Z
PLLFILT
+Ω
AM07226v1
7/44
Block diagram and pin description
Table 2.
A3G4250D
Pin description
Pin#
Name
1
Vdd_IO
2
SCL
SPC
I2C serial clock (SCL)
SPI serial port clock (SPC)
3
SDA
SDI
SDO
I2C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
4
SDO
SA0
SPI serial data output (SDO)
I2C least significant bit of the device address (SA0)
5
CS
6
DRDY/INT2
7
INT1
8
Reserved
Connect to GND
9
Reserved
Connect to GND
10
Reserved
Connect to GND
11
Reserved
Connect to GND
12
Reserved
Connect to GND
13
GND
14
PLLFILT
Phase-locked loop filter (see Figure 3)
15
Reserved
Connect to Vdd
16
Vdd
Figure 3.
Function
Power supply for I/O pins
SPI enable
I2C/SPI mode selection (1: SPI idle mode / I2C communication
enabled; 0: SPI communication mode / I2C disabled)
Data ready/FIFO interrupt
Programmable interrupt
0 V supply
Power supply
A3G4250D external low-pass filter values(a)
#APACITORFOR
,OW
PASSFILTER
TOPIN
#
#
2
'.$
!-V
a. Pin 14 PLLFILT maximum voltage level is equal to Vdd.
8/44
Doc 022768 Rev 3
A3G4250D
Block diagram and pin description
Table 3.
Filter values
Parameter
Typical value
C1
10 nF
C2
470 nF
R2
10 kΩ
Doc 022768 Rev 3
9/44
Mechanical and electrical characteristics
A3G4250D
2
Mechanical and electrical characteristics
2.1
Mechanical characteristics
@ Vdd = 3.0 V, T = -40... +85 °C, unless otherwise noted(b).
Table 4.
Symbol
Mechanical characteristics
Parameter
FS
Measurement range(2)
So
Sensitivity(3)
SoDr
Sensitivity change vs.
temperature
DVoff
Digital zero-rate level(3)
OffDr
Zero-rate level change
vs. temperature
NL
DST
Rn
Non linearity(2)
Test condition
Min.
Max.
Unit
10.1
mdps/digit
±245
7.4
8.75
dps
±2
-25
%
+25
±0.03
Best fit straight line
Self-test output change
Rate noise density
Typ.(1)
dps
dps/°C
-5
0.2
+5
% FS
55
130
245
dps
0.03
0.15
dps/
sqrt(Hz)
105/208/
420/840
121/239/
483/966
Hz
+85
°C
BW = 50 Hz
ODR
Digital output data rate
89/176/
357/714
Top
Operating temperature
range
-40
1. Typical specifications are not guaranteed; typical values at +25 °C.
2. Guaranteed by design.
3. Across temperature and after MSL3 preconditioning.
b. The product is factory calibrated at 3.0 V. The operational power supply range is specified in Table 5.
10/44
Doc 022768 Rev 3
A3G4250D
2.2
Mechanical and electrical characteristics
Electrical characteristics
@ Vdd = 3.0 V, T = -40... +85 °C, unless otherwise noted(c).
Table 5.
Symbol
Vdd
Vdd_IO
Idd
Electrical characteristics
Parameter
Test condition
Min.
Typ.(1)
Max.
Unit
2.4
3.0
3.6
V
Vdd+0.1
V
7.0
mA
Supply voltage
I/O pins supply voltage
(2)
1.71
Supply current
4.8
6.1
IddSL
Supply current
in sleep mode(3)
Selectable by digital
interface
1.5
IddPdn
Supply current in
power-down mode(4)
Selectable by digital
interface
5
Top
Operating temperature
range
-40
mA
10
µA
+85
°C
1. Typical specifications are not guaranteed; typical values at +25 °C.
2. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the
measurement chain is powered off.
3. Sleep mode introduces a faster turn-on time compared to power-down mode.
4. Verified at wafer level.
2.3
Temperature sensor characteristics
@ Vdd = 3.0 V, T = 25 °C, unless otherwise noted(d).
Table 6.
Symbol
Temp. sensor characteristics
Parameter
TSDr
Temperature sensor
output change vs.
temperature
TODR
Temperature refresh rate
Top
Test condition
Min.
-
Operating temperature
range
-40
Typ.(1)
Max.
Unit
-1
°C/digit
1
Hz
+85
°C
1. Typical specifications are not guaranteed; typical values at +25 °C.
c. The product is factory calibrated at 3.0 V.
d. The product is factory calibrated at 3.0 V.
Doc 022768 Rev 3
11/44
Mechanical and electrical characteristics
A3G4250D
2.4
Communication interface characteristics
2.4.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 7.
SPI slave timing values
Value(1)
Symbol
Parameter
Unit
Min.
tc(SPC)
SPI clock cycle
fc(SPC)
SPI clock frequency
tsu(CS)
CS setup time
5
th(CS)
CS hold time
8
tsu(SI)
SDI input setup time
5
th(SI)
SDI input hold time
15
tv(SO)
SDO valid output time
th(SO)
SDO output hold time
tdis(SO)
Max.
100
ns
10
MHz
ns
50
6
SDO output disable time
50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results; not
tested in production.
Figure 4.
&6
SPI slave timing diagram(e)
WF 63&
WVX &6
WK &6
63&
WVX 6,
6',
WK 6,
/6%,1
06%,1
WY 62
6'2
WGLV 62
WK 62
06%287
/6%287
!-V
e. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.
12/44
Doc 022768 Rev 3
A3G4250D
Mechanical and electrical characteristics
I2C - inter IC control interface
2.4.2
Subject to general operating conditions for Vdd and Top.
Table 8.
I2C slave timing values
I2C standard mode(1)
Symbol
f(SCL)
I2C fast mode(1)
Parameter
Unit
SCL clock frequency
Min.
Max.
Min.
Max.
0
100
0
400
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
th(SDA)
SDA data hold time
0
th(ST)
START condition hold time
4
0.6
tsu(SR)
Repeated START condition
setup time
4.7
0.6
tsu(SP)
STOP condition setup time
4
0.6
4.7
1.3
kHz
µs
3.45
ns
0
0.9
µs
µs
tw(SP:SR)
Bus free time between STOP
and START condition
1. Data based on standard I2C protocol requirement; not tested in production.
Figure 5.
I2C slave timing diagram(f)
5(3($7('
67$57
67$57
WVX 65
WZ 63 65
6'$
WI 6'$
WK 6'$
WVX 6'$
WU 6'$
67$57
WVX 63
6723
6&/
WK 67
f.
WZ 6&//
WZ 6&/+
WU 6&/
WI 6&/
!-V
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
Doc 022768 Rev 3
13/44
Mechanical and electrical characteristics
2.5
A3G4250D
Absolute maximum ratings
Any stress above that listed as “Absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 9.
Absolute maximum ratings
Symbol
Ratings
Maximum value
Unit
Vdd
Supply voltage
-0.3 to 4.8
V
TSTG
Storage temperature range
-40 to +125
°C
10,000
g
2 (HBM)
kV
Sg
ESD
Acceleration g for 0.1 ms
Electrostatic discharge protection
This is a mechanical shock sensitive device, improper handling can cause permanent
damage to the part
This is an ESD sensitive device, improper handling can cause permanent damage to
the part
14/44
Doc 022768 Rev 3
A3G4250D
Mechanical and electrical characteristics
2.6
Terminology
2.6.1
Sensitivity
An angular rate gyroscope is a device that produces a positive-going digital output for
counter-clockwise rotation around the sensitive axis considered. Sensitivity describes the
gain of the sensor and can be determined by applying a defined angular velocity to it. This
value changes very little over temperature and time.
2.6.2
Zero-rate level
The zero-rate level describes the actual output signal if there is no angular rate present. The
zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor
and, therefore, the zero-rate level can slightly change after mounting the sensor onto a
printed circuit board or after exposing it to extensive mechanical stress. This value changes
very little over temperature and time.
2.6.3
Stability over temperature and time
Thanks to the unique single-driving mass approach and optimized design, ST gyroscopes
are able to guarantee a perfect match of the MEMS mechanical mass and the ASIC
interface, and deliver unprecedented levels of stability over temperature and time.
With the zero-rate level and sensitivity performances, up to ten times better than equivalent
products currently available on the market, the A3G4250D allows the user to avoid any
further compensation and calibration during production for a faster time to market, easy
application implementation, higher performance, and cost saving.
2.7
Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Leave “pin 1 indicator” unconnected during soldering.
Land pattern and soldering recommendations are available at www.st.com/.
Doc 022768 Rev 3
15/44
Main digital blocks
A3G4250D
3
Main digital blocks
3.1
Block diagram
Figure 6.
Block diagram
/UT?3EL
,0&
!$#
,0&
(0&
(0EN
$ATA2EG
&)&/
XX
)#
30)
).4?3EL
)NTERRUPT
GENERATOR
3#22%'
#/.&2%'
).4
!-V
3.2
FIFO
The A3G4250D embeds a 32-slot, 16-bit data FIFO for each of the three output channels:
yaw, pitch, and roll. This allows consistent power saving for the system, as the host
processor does not need to continuously poll data from the sensor. Instead, it can wake up
only when needed and burst the significant data out from the FIFO. This buffer can work in
five different modes. Each mode is selected by the FIFO_MODE bits in FIFO_CTRL_REG.
Programmable watermark level, FIFO_empty or FIFO_Full events can be enabled to
generate dedicated interrupts on the DRDY/INT2 pin (configured through CTRL_REG3),
and event detection information is available in FIFO_SRC_REG. The watermark level can
be configured to WTM4: 0 in FIFO_CTRL_REG.
3.2.1
Bypass mode
In bypass mode, the FIFO is not operational and for this reason it remains empty. As
illustrated in Figure 7, only the first address is used for each channel. The remaining FIFO
slots are empty. When new data is available, the old data is overwritten.
16/44
Doc 022768 Rev 3
A3G4250D
Main digital blocks
Figure 7.
Bypass mode
XI YI ZI
EMPTY
X
Y I
Z
X
Y
Z
X
Y
Z
X
Y
Z
!-V
3.2.2
FIFO mode
In FIFO mode, data from the yaw, pitch, and roll channels are stored in the FIFO. A
watermark interrupt can be enabled (I2_WMK bit in CTRL_REG3), which is triggered when
the FIFO is filled to the level specified in the WTM 4: 0 bits of FIFO_CTRL_REG. The FIFO
continues filling until it is full (32 slots of 16-bit data for yaw, pitch, and roll). When full, the
FIFO stops collecting data from the input channels. To restart data collection, it is necessary
to write FIFO_CTRL_REG back to bypass mode.
FIFO mode is represented in Figure 8.
Doc 022768 Rev 3
17/44
Main digital blocks
Figure 8.
A3G4250D
FIFO mode
XI YI ZI
X
Y I
Z
X
Y
Z
X
Y
Z
X
Y
Z
!-V
3.2.3
Stream mode
In stream mode, data from yaw, pitch, and roll measurements are stored in the FIFO. A
watermark interrupt can be enabled and set as in FIFO mode. The FIFO continues filling
until full (32 slots of 16-bit data for yaw, pitch, and roll). When full, the FIFO discards the
older data as the new data arrives. Programmable watermark level events can be enabled to
generate dedicated interrupts on the DRDY/INT2 pin (configured through CTRL_REG3).
Stream mode is represented in Figure 9.
18/44
Doc 022768 Rev 3
A3G4250D
Main digital blocks
Figure 9.
Stream mode
XI YI ZI
X
Y
Z
X
Y
Z
X
Y
Z
X
Y
Z
X
Y
Z
!-V
3.2.4
Retrieve data from FIFO
FIFO data is read through the OUT_X, OUT_Y, and OUT_Z registers. When the FIFO is in
stream, trigger or FIFO mode, a read operation to the OUT_X, OUT_Y or OUT_Z registers
provides the data stored in the FIFO. Each time data is read from the FIFO, the oldest pitch,
roll, and yaw data are placed in the OUT_X, OUT_Y and OUT_Z registers, and both single
read and read_burst (X, Y & Z with auto-incremental address) operations can be used. In
read_burst mode, when data included in OUT_Z_H is read, the system again starts to read
information from addr OUT_X_L.
The reading from FIFO may be executed either in synchronous or asynchronous mode. For
correct data acquisition, the following points need to be followed:
1.
2.
If reading is synchronous, all data should be acquired within one ODR cycle
If reading is asynchronous, an appropriate FIFO access sequence must be applied:
a)
A single dummy read @ 28h (increment bit = 0) to update data out
b)
A burst read of 6 bytes from 2Ah (Y low) up to 29h:
–
Y(2A-2Bh)
–
Z(2C - 2Dh)
–
X(28-29h)
Figure 10 illustrates the correct sequence with a flow diagram:
Doc 022768 Rev 3
19/44
Main digital blocks
A3G4250D
Figure 10. FIFO access sequence in asynchronous mode
No
WTM = ‘1’
Yes
Read FIFO SRC (2Fh)
n = FSS
Dummy Read from ‘28h’
(increment bit =‘0’)
n--
Burst Read from ‘2Ah’ of
6 registers (Y, Z, X)
No
n=0
Yes
Example:
FSS = 1 read twice
FSS = 2 read 3 times
AM10248V1
If the above sequence is not followed, the acquisition from FIFO may lead to corrupted data.
20/44
Doc 022768 Rev 3
A3G4250D
Application hints
Figure 11. A3G4250D electrical connections and external component values
+Ω
Vdd
GND
GND
Z
+Ω
10 µF
Y
Vdd
X
PLLFILT
100 nF
1
16
+Ω
(TOP VIEW)
DIRECTIONS OF THE
DETECTABLE
ANGULAR RATES
X
Vdd_IO
13
1
12
TOP
VIEW
SCL/SPC
SDA_SDI_SDO
4
SDO/SA0
9
8
5
C1
10kOhm
GND
10nF
470nF
CS
C2
DR INT
Vdd I2C bus
Rpu
PLLFILT
R2
GND
4
Application hints
Rpu = 10kOhm
SCL/SPC
SDA_SDI_SDO
Pull-up to be added when I2C interface is used
AM07949V1
Power supply decoupling capacitors (100 nF ceramic or polyester +10 µF) should be placed
as near as possible to the device (common design practice).
If Vdd and Vdd_IO are not connected together, power supply decoupling capacitors
(100 nF and 10 µF between Vdd and common ground, 100 nF between Vdd_IO and
common ground) should be placed as near as possible to the device (common design
practice).
The A3G4250D IC includes a PLL (phase locked loop) circuit to synchronize driving and
sensing interfaces. Capacitors and resistors must be added at the PLLFILT pin (as shown in
Figure 11) to implement a second-order low-pass filter. Table 10 summarizes the PLL lowpass filter component values.
Table 10.
PLL low-pass filter component values
Component
Value
C1
10 nF ± 10%
Doc 022768 Rev 3
21/44
Application hints
Table 10.
22/44
A3G4250D
PLL low-pass filter component values
Component
Value
C2
470 nF ± 10%
R2
10 kΩ ± 10%
Doc 022768 Rev 3
A3G4250D
5
Digital interfaces
Digital interfaces
The registers embedded in the A3G4250D may be accessed through both the I2C and SPI
serial interfaces. The latter may be software-configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pins. To select/exploit the I2C interface, the
CS line must be tied high (i.e., connected to Vdd_IO).
Table 11.
Serial interface pin description
Pin name
Pin description
CS
SPI enable
I2C/SPI mode selection (1: SPI idle mode / I2C communication enabled; 0: SPI
communication mode / I2C disabled)
SCL/SPC
SDA/SDI/SDO
I2C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
SPI serial data output (SDO)
I2C least significant bit of the device address
SDO
5.1
I2C serial clock (SCL)
SPI serial port clock (SPC)
I2C serial interface
The A3G4250D I2C is a bus slave. The I2C is employed to write data to registers whose
content can also be read back.
The relevant I2C terminology is given in the table below.
Table 12.
I2C terminology
Term
Transmitter
Receiver
Description
The device which sends data to the bus
The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a
transfer
Slave
The device addressed by the master
There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial
data line (SDA). The latter is a bi-directional line used for sending and receiving the data
to/from the interface. Both lines must be connected to Vdd_IO through an external pull-up
resistor. When the bus is free both the lines are high.
The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with normal
mode.
Doc 022768 Rev 3
23/44
Digital interfaces
5.1.1
A3G4250D
I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first 7 bits after
a start condition with its address. If they match, the device considers itself addressed by the
master.
The slave address (SAD) associated with the A3G4250D is 110100xb. The SDO pin can be
used to modify the least significant bit (LSb) of the device address. If the SDO pin is
connected to the voltage supply, LSb is ‘1’ (address 1101001b). Otherwise, when the SDO
pin is connected to ground, the LSb value is ‘0’ (address 1101000b). This solution permits
the connection and addressing of two different gyroscopes to the same I2C bus.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I2C embedded in the A3G4250D behaves like a slave device, and the following protocol
must be adhered to. After the START (ST) condition, a slave address is sent. Once a slave
acknowledge (SAK) has been returned, an 8-bit sub-address is transmitted. The 7 LSb
represent the actual register address while the MSb enables address auto-increment. If the
MSb of the SUB field is 1, the SUB (register address) is automatically incremented to allow
multiple data read/write.
The slave address is completed with a read/write bit. If the bit is ‘1’ (read), a REPEATED
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (write)
the master transmits to the slave with the direction unchanged. Table 13 describes how the
SAD+read/write bit pattern is composed, listing all the possible configurations.
Table 13.
Command
SAD[6:1]
SAD[0] = SDO
R/W
Read
110100
0
1
11010001 (D1h)
Write
110100
0
0
11010000 (D0h)
Read
110100
1
1
11010011 (D3h)
Write
110100
1
0
11010010 (D2h)
Table 14.
Master
Slave
24/44
SAD+read/write patterns
SAD+R/W
Transfer when master is writing one byte to slave
ST
SAD + W
SUB
SAK
Doc 022768 Rev 3
DATA
SAK
SP
SAK
A3G4250D
Digital interfaces
Table 15.
Master
Transfer when master is writing multiple bytes to slave
ST
SAD + W
Slave
SAK
Table 16.
Master
ST
SAD + W
DATA
SAK
SUB
SAK
SAK
SP
SAK
SR
SAD + R
SAK
NMAK
SAK
SP
DATA
Transfer when master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W
Slave
DATA
Transfer when master is receiving (reading) one byte of data from slave
Slave
Table 17.
SUB
SUB
SAK
SR SAD+R
SAK
MAK
SAK DATA
MAK
DATA
NMAK
SP
DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit
(MSb) first. If a receiver cannot receive another complete byte of data until it has performed
some other function, it can hold the clock line SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver does not acknowledge the slave address (i.e., it is not able
to receive because it is performing some real-time function) the data line must be left HIGH
by the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA
line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1, while SUB(6-0) represents the
address of the first register to be read.
In the presented communication format, MAK is “master acknowledge” and NMAK is “no
master acknowledge”.
5.2
SPI bus interface
The SPI is a bus slave. The SPI allows writing and reading of the device registers. The serial
interface interacts with the external world through 4 wires: CS, SPC, SDI, and SDO.
Doc 022768 Rev 3
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Digital interfaces
A3G4250D
Figure 12. Read and write protocol
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the serial port enable and is controlled by the SPI master. It goes low at the start of the
transmission and returns to high at the end. SPC is the serial port clock and is controlled by
the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are,
respectively, the serial port data input and output. These lines are driven at the falling edge
of SPC and should be captured at the rising edge of SPC.
Both the read register and write register commands are completed in 16 clock pulses, or in
multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling
edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge
of CS while the last bit (bit 15, bit 23, etc.) starts at the last falling edge of SPC just before
the rising edge of CS.
Bit 0: RW bit. When 0, the data DI(7:0) is written to the device. When 1, the data DO(7:0)
from the device is read. In the latter case, the chip drives SDO at the start of bit 8.
Bit 1: MS bit. When 0, the address remains unchanged in multiple read/write commands.
When 1, the address is auto-incremented in multiple read/write commands.
Bit 2-7: address AD(5:0). This is the address field of the indexed register.
Bit 8-15: data DI(7:0) (write mode). This is the data that is written to the device (MSb first).
Bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands, further blocks of 8 clock periods are added. When the MS
bit is 0, the address used to read/write data remains the same for every block. When the MS
bit is 1, the address used to read/write data is incremented at every block.
The function and the behavior of SDI and SDO remain unchanged.
5.2.1
SPI read
Figure 13. SPI read protocol
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
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Doc 022768 Rev 3
A3G4250D
Digital interfaces
The SPI read command is performed with 16 clock pulses. A multiple byte read command is
performed by adding blocks of 8 clock pulses to the previous one.
Bit 0: READ bit. The value is 1.
Bit 1: MS bit. When 0, do not increment address; when 1, increment address in multiple
reading.
Bit 2-7: address AD(5:0). This is the address field of the indexed register.
Bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
Bit 16-...: data DO(...-8). Further data in multiple byte reading.
Figure 14. Multiple byte SPI read protocol (2-byte example)
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15DO14DO13DO12DO11DO10DO9 DO8
5.2.2
SPI write
Figure 15. SPI write protocol
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
The SPI write command is performed with 16 clock pulses. A multiple byte write command is
performed by adding blocks of 8 clock pulses to the previous one.
Bit 0: WRITE bit. The value is 0.
Bit 1: MS bit. When 0, do not increment address; when 1, increment address in multiple
writing.
Bit 2 -7: address AD(5:0). This is the address field of the indexed register.
Bit 8-15: data DI(7:0) (write mode). This is the data that is written to the device (MSb first).
Bit 16-...: data DI(...-8). Further data in multiple byte writing.
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Digital interfaces
A3G4250D
Figure 16. Multiple byte SPI write protocol (2-byte example)
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
5.2.3
SPI read in 3-wire mode
3-wire mode is entered by setting the SIM (SPI serial interface mode selection) bit to 1 in
CTRL_REG2.
Figure 17. SPI read protocol in 3-wire mode
CS
SPC
SDI/O
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
The SPI read command is performed with 16 clock pulses:
Bit 0: READ bit. The value is 1.
Bit 1: MS bit. When 0, do not increment address; when 1, increment address in multiple
reading.
Bit 2-7: address AD(5:0). This is the address field of the indexed register.
Bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
The multiple read command is also available in 3-wire mode.
Note:
If the A3G4250D is used in a multi-SPI slave environment (several devices sharing the
same SPI bus), the accelerometer can be forced by software to remain in SPI mode. This
objective can be achieved by sending, at the beginning of the SPI communication, the
following sequence to the device:
a = read(0x05)
write(0x05, (0x20 OR a))
The programming of this register makes it possible to enhance the robustness of the SPI
system.
28/44
Doc 022768 Rev 3
A3G4250D
6
Output register mapping
Output register mapping
Table 18 below provides a listing of the 8-bit registers embedded in the device and the
related addresses:
Table 18.
Register address map
Register address
Name
Type
Default
Hex
Binary
-
Reserved
-
00-0E
WHO_AM_I
r
0F
Reserved
-
10-1F
CTRL_REG1
rw
20
010 0000 00000111
CTRL_REG2
rw
21
010 0001 00000000
CTRL_REG3
rw
22
010 0010 00000000
CTRL_REG4
rw
23
010 0011 00000000
CTRL_REG5
rw
24
010 0100 00000000
REFERENCE
rw
25
010 0101 00000000
OUT_TEMP
r
26
010 0110
Output
STATUS_REG
r
27
010 0111
Output
OUT_X_L
r
28
010 1000
Output
OUT_X_H
r
29
010 1001
Output
OUT_Y_L
r
2A
010 1010
Output
OUT_Y_H
r
2B
010 1011
Output
OUT_Z_L
r
2C
010 1100
Output
OUT_Z_H
r
2D
010 1101
Output
FIFO_CTRL_REG
rw
2E
010 1110 00000000
FIFO_SRC_REG
r
2F
010 1111
INT1_CFG
rw
30
011 0000 00000000
INT1_SRC
r
31
011 0001
INT1_TSH_XH
rw
32
011 0010 00000000
INT1_TSH_XL
rw
33
011 0011 00000000
INT1_TSH_YH
rw
34
011 0100 00000000
INT1_TSH_YL
rw
35
011 0101 00000000
INT1_TSH_ZH
rw
36
011 0110 00000000
INT1_TSH_ZL
rw
37
011 0111 00000000
INT1_DURATION
rw
38
011 1000 00000000
Doc 022768 Rev 3
Comment
-
000 1111 11010011
-
-
Output
Output
29/44
Output register mapping
A3G4250D
Registers marked as Reserved must not be changed. Writing to those registers may change
calibration data and therefore lead to a non-proper working device.
The content of the registers that are loaded at boot should not be changed. They contain the
factory calibration values. Their content is automatically restored when the device is
powered up.
30/44
Doc 022768 Rev 3
A3G4250D
7
Register description
Register description
The device contains a set of registers which are used to control its behavior and to retrieve
rate data. The register addresses, made up of 7 bits, are used to identify them and to write
the data through the serial interface.
7.1
WHO_AM_I (0Fh)
Table 19.
WHO_AM_I register
1
1
0
1
0
0
1
1
BW0
PD
Zen
Yen
Xen
Device identification register.
7.2
CTRL_REG1 (20h)
Table 20.
DR1
Table 21.
CTRL_REG1 register
DR0
BW1
CTRL_REG1 description
DR1-DR0
Output data rate selection. Refer to Table 22
BW1-BW0
Bandwidth selection. Refer to Table 22
PD
Power-down mode enable. Default value: 0
(0: power-down mode, 1: normal mode or sleep mode)
Zen
Z-axis enable. Default value: 1
(0: Z-axis disabled; 1: Z-axis enabled)
Yen
Y-axis enable. Default value: 1
(0: Y-axis disabled; 1: Y-axis enabled)
Xen
X-axis enable. Default value: 1
(0: X-axis disabled; 1: X-axis enabled)
DR is used to set ODR selection. BW is used to set Bandwidth selection.
In the following table (Table 22) all frequencies resulting in a combination of DR / BW bits
are reported.
Table 22.
DR and BW configuration setting
DR
BW
ODR [Hz]
Cut-off
00
00
100
12.5
00
01
100
25
00
10
100
25
00
11
100
25
Doc 022768 Rev 3
31/44
Register description
Table 22.
A3G4250D
DR and BW configuration setting (continued)
DR
BW
ODR [Hz]
Cut-off
01
00
200
12.5
01
01
200
25
01
10
200
50
01
11
200
70
10
00
400
20
10
01
400
25
10
10
400
50
10
11
400
110
11
00
800
30
11
01
800
35
11
10
800
50
11
11
800
110
Combination of PD, Zen, Yen, and Xen are used to set the device in different modes
(power-down / normal / sleep mode) according to the following table.
Table 23.
Power mode selection configuration
Mode
7.3
PD
Zen
Yen
Xen
Power-down
0
-
-
-
Sleep
1
0
0
0
Normal
1
-
-
-
CTRL_REG2 (21h)
Table 24.
(1)
0
CTRL_REG2 register
0(1)
HPM1
HPM1
HPCF3
HPCF2
HPCF1
1. Value loaded at boot. This value must not be changed.
Table 25.
CTRL_REG2 description
HPM1HPM0
High-pass filter mode selection. Default value: 00
Refer to Table 26
HPCF3HPCF0
High-pass filter cut-off frequency selection
Refer to Table 28
Table 26.
High-pass filter mode configuration
HPM1
0
32/44
HPM0
0
High-pass filter mode
Normal mode (reset reading HP_RESET_FILTER)
Doc 022768 Rev 3
HPCF0
A3G4250D
Register description
Table 26.
0
1
Reference signal for filtering
1
0
Normal mode
1
1
Auto-reset on interrupt event
Table 27.
7.4
High-pass filter cut-off frequency configuration [Hz]
HPCF3
ODR= 100 Hz
ODR= 200 Hz
ODR= 400 Hz
ODR= 800 Hz
0000
8
15
30
56
0001
4
8
15
30
0010
2
4
8
15
0011
1
2
4
8
0100
0.5
1
2
4
0101
0.2
0.5
1
2
0110
0.1
0.2
0.5
1
0111
0.05
0.1
0.2
0.5
1000
0.02
0.05
0.1
0.2
1001
0.01
0.02
0.05
0.1
CTRL_REG3 (22h)
Table 28.
I1_Int1
Table 29.
7.5
High-pass filter mode configuration
CTRL_REG1 register
I1_Boot
H_Lactive
PP_OD
I2_DRDY
I2_WTM
I2_ORun
I2_Empty
CTRL_REG3 description
I1_Int1
Interrupt enable on the INT1 pin. Default value 0. (0: disable; 1: enable)
I1_Boot
Boot status available on INT1. Default value 0. (0: disable; 1: enable)
H_Lactive
Interrupt active configuration on INT1. Default value 0. (0: high; 1: low)
PP_OD
Push-pull / open drain. Default value: 0. (0: push-pull; 1: open drain)
I2_DRDY
Date ready on DRDY/INT2. Default value 0. (0: disable; 1: enable)
I2_WTM
FIFO watermark interrupt on DRDY/INT2. Default value: 0. (0: disable; 1: enable)
I2_ORun
FIFO overrun interrupt on DRDY/INT2 Default value: 0. (0: disable; 1: enable)
I2_Empty
FIFO empty interrupt on DRDY/INT2. Default value: 0. (0: disable; 1: enable)
CTRL_REG4 (23h)
Table 30.
0
CTRL_REG4 register
BLE
0
0
Doc 022768 Rev 3
-
ST1
ST0
SIM
33/44
Register description
A3G4250D
Table 31.
CTRL_REG4 description
BLE
Big/little endian data selection. Default value 0.
(0: data LSB @ lower address; 1: data MSB @ lower address)
ST1-ST0
Self-test enable. Default value: 00
(00: self-test disabled; Other: see Table )
SIM
SPI serial interface mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface).
Table 32.
Self-test mode configuration
ST1
ST0
Self-test mode
0
0
Normal mode
0
1
Self-test 0 (+)(1)
1
0
--
1
1
Self-test 1 (-)(1)
1. DST sign (absolute value in Table 4).
7.6
CTRL_REG5 (24h)
Table 33.
BOOT
Table 34.
34/44
CTRL_REG5 register
FIFO_EN
--
HPen
INT1_Sel1 INT1_Sel0
CTRL_REG5 description
BOOT
Reboot memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
FIFO_EN
FIFO enable. Default value: 0
(0: FIFO disable; 1: FIFO enable)
HPen
High-pass filter enable. Default value: 0
(0: HPF disabled; 1: HPF enabled (see Figure 19)
INT1_Sel1INT1_Sel0
INT1 selection configuration. Default value: 0
(see Figure 19)
Out_Sel1Out_Sel1
Out selection configuration. Default value: 0
(see Figure 19)
Doc 022768 Rev 3
Out_Sel1
Out_Sel0
A3G4250D
Register description
Figure 18. INT1_Sel and Out_Sel configuration block diagram
Out_Sel
00
01
0
LPF2
ADC
LPF1
HPF
10
11
DataReg
FIFO
32x16x3
1
INT1_Sel
HPen
10
11
01
Interrupt
generator
00
AM07949V2
Table 35.
Out_Sel configuration settings
Hpen
OUT_SEL1
OUT_SEL0
x
0
0
Data in DataReg and FIFO are non-highpass-filtered
x
0
1
Data in DataReg and FIFO are high-passfiltered
0
1
x
Data in DataReg and FIFO are low-passfiltered by LPF2
1
1
x
Data in DataReg and FIFO are high-pass and
low-pass-filtered by LPF2
Table 36.
Description
INT_SEL configuration settings
Hpen
INT_SEL1
INT_SEL2
x
0
0
Non-high-pass-filtered data are used for
interrupt generation
x
0
1
High-pass-filtered data are used for interrupt
generation
0
1
x
Low-pass-filtered data are used for interrupt
generation
1
1
x
High-pass and low-pass-filtered data are
used for interrupt generation
Doc 022768 Rev 3
Description
35/44
Register description
7.7
A3G4250D
REFERENCE/DATACAPTURE (25h)
Table 37.
Ref7
REFERENCE register
Ref6
Table 38.
Ref3
Ref2
Ref1
Ref0
Reference value for interrupt generation. Default value: 0
OUT_TEMP (26h)
Table 39.
Temp7
OUT_TEMP register
Temp6
Table 40.
Temp5
Temp4
Temp3
Temp2
Temp1
Temp0
OUT_TEMP register description
Temp7-Temp0
7.9
Ref4
REFERENCE register description
Ref 7-Ref0
7.8
Ref5
Temperature data.
STATUS_REG (27h)
Table 41.
ZYXOR
STATUS_REG register
ZOR
Table 42.
YOR
XOR
ZYXDA
ZDA
YDA
XDA
STATUS_REG description
X, Y, Z-axis data overrun. Default value: 0
ZYXOR (0: no overrun has occurred; 1: new data has overwritten the previous one before it was
read)
ZOR
Z-axis data overrun. Default value: 0
(0: no overrun has occurred; 1: a new data for the Z-axis has overwritten the previous one)
YOR
Y-axis data overrun. Default value: 0
(0: no overrun has occurred; 1: a new data for the Y-axis has overwritten the previous one)
XOR
X-axis data overrun. Default value: 0
(0: no overrun has occurred; 1: a new data for the X-axis has overwritten the previous one)
ZYXDA X, Y, Z-axis new data available. Default value: 0
(0: a new set of data is not yet available; 1: a new set of data is available)
36/44
ZDA
Z-axis new data available. Default value: 0
(0: a new data for the Z-axis is not yet available; 1: a new data for the Z-axis is available)
YDA
Y-axis new data available. Default value: 0
(0: a new data for the Y-axis is not yet available;1: a new data for the Y-axis is available)
XDA
X-axis new data available. Default value: 0
(0: a new data for the X-axis is not yet available; 1: a new data for the X-axis is available)
Doc 022768 Rev 3
A3G4250D
7.10
Register description
OUT_X_L (28h), OUT_X_H (29h)
X-axis angular rate data. The value is expressed as 2’s complement.
7.11
OUT_Y_L (2Ah), OUT_Y_H (2Bh)
Y-axis angular rate data. The value is expressed as 2’s complement.
7.12
OUT_Z_L (2Ch), OUT_Z_H (2Dh)
Z-axis angular rate data. The value is expressed as 2’s complement.
7.13
FIFO_CTRL_REG (2Eh)
Table 43.
REFERENCE register
FM2
FM1
Table 44.
WTM4
WTM3
WTM2
WTM1
WTM0
FSS1
FSS0
REFERENCE register description
FM2-FM0
FIFO mode selection. Default value: 00
WTM4-WTM0
FIFO threshold. Watermark level setting
Table 45.
FIFO mode configuration
FM2
7.14
FM0
FM1
FM0
FIFO mode
0
0
0
Bypass mode
0
0
1
FIFO mode
0
1
0
Stream mode
FIFO_SRC_REG (2Fh)
Table 46.
WTM
Table 47.
FIFO_SRC register
OVRN
EMPTY
FSS4
FSS3
FSS2
FIFO_SRC register description
WTM
Watermark status. (0: FIFO filling is lower than WTM level; 1: FIFO filling is equal
or higher than WTM level)
OVRN
Overrun bit status.
(0: FIFO is not completely filled; 1: FIFO is completely filled)
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37/44
Register description
Table 47.
7.15
A3G4250D
FIFO_SRC register description (continued)
EMPTY
FIFO empty bit.
(0: FIFO not empty; 1: FIFO empty)
FSS4-FSS1
FIFO stored data level
INT1_CFG (30h)
Table 48.
AND/OR
Table 49.
INT1_CFG register
LIR
ZHIE
ZLIE
YHIE
YLIE
XHIE
XLIE
INT1_CFG description
AND/OR
AND/OR combination of interrupt events. Default value: 0
(0: OR combination of interrupt events 1: AND combination of interrupt events
LIR
Latch interrupt request. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
Cleared by reading the INT1_SRC reg.
ZHIE
Enable interrupt generation on Z high event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured rate value
higher than preset threshold)
ZLIE
Enable interrupt generation on Z low event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured rate value lower
than preset threshold)
YHIE
Enable interrupt generation on Y high event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured rate value
higher than preset threshold)
YLIE
Enable interrupt generation on Y low event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured rate value lower
than preset threshold)
XHIE
Enable interrupt generation on X high event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured rate value
higher than preset threshold)
XLIE
Enable interrupt generation on X low event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured rate value lower
than preset threshold)
Configuration register for interrupt source.
7.16
INT1_SRC (31h)
Table 50.
0
38/44
INT1_SRC register
IA
ZH
ZL
Doc 022768 Rev 3
YH
YL
XH
XL
A3G4250D
Register description
Table 51.
INT1_SRC description
IA
Interrupt active. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
ZH
Z high. Default value: 0 (0: no interrupt, 1: Z high event has occurred)
ZL
Z low. Default value: 0 (0: no interrupt; 1: Z low event has occurred)
YH
Y high. Default value: 0 (0: no interrupt, 1: Y high event has occurred)
YL
Y low. Default value: 0 (0: no interrupt, 1: Y low event has occurred)
XH
X high. Default value: 0 (0: no interrupt, 1: X high event has occurred)
XL
X low. Default value: 0 (0: no interrupt, 1: X low event has occurred)
Interrupt source register. Read only register.
Reading at this address clears the INT1_SRC IA bit (and eventually the interrupt signal on
the INT1 pin) and allows the refreshment of data in the INT1_SRC register if the latched
option is chosen.
7.17
INT1_THS_XH (32h)
Table 52.
-
Table 53.
INT1_THS_XH register
THSX14
THSX11
THSX10
THSX9
THSX8
THSX1
THSX0
THSY9
THSY8
Interrupt threshold. Default value: 0000 0000
INT1_THS_XL (33h)
Table 54.
THSX7
Table 55.
INT1_THS_XL register
THSX6
THSX5
THSX4
THSX3
THSX2
INT1_THS_XL description
THSX7 - THSX0
7.19
THSX12
INT1_THS_XH description
THSX14 - THSX9
7.18
THSX13
Interrupt threshold. Default value: 0000 0000
INT1_THS_YH (34h)
Table 56.
-
Table 57.
INT1_THS_YH register
THSY14
THSY13
THSY12
THSY11
THSY10
INT1_THS_YH description
THSY14 - THSY9
Interrupt threshold. Default value: 0000 0000
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Register description
7.20
A3G4250D
INT1_THS_YL (35h)
Table 58.
THSR7
Table 59.
INT1_THS_YL register
THSY6
-
Table 61.
THSY2
THSY1
THSY0
THSZ9
THSZ8
THSZ1
THSZ0
D1
D0
Interrupt threshold. Default value: 0000 0000
INT1_THS_ZH register
THSZ14
THSZ13
THSZ12
THSZ11
THSZ10
INT1_THS_ZH description
THSZ14 - THSZ9
Interrupt threshold. Default value: 0000 0000
INT1_THS_ZL (37h)
Table 62.
THSZ7
Table 63.
INT1_THS_ZL register
THSZ6
THSZ5
THSZ4
THSZ3
THSZ2
INT1_THS_ZL description
THSZ7 - THSZ0
7.23
THSY3
INT1_THS_ZH (36h)
Table 60.
7.22
THSY4
INT1_THS_YL description
THSY7 - THSY0
7.21
THSY5
Interrupt threshold. Default value: 0000 0000
INT1_DURATION (38h)
Table 64.
WAIT
Table 65.
INT1_DURATION register
D6
D5
D4
D3
D2
INT1_DURATION description
WAIT
WAIT enable. Default value: 0 (0: disable; 1: enable)
D6 - D0
Duration value. Default value: 000 0000
D6 - D0 bits set the minimum duration of the interrupt event to be recognized. Duration steps
and maximum values depend on the ODR chosen.
WAIT bit has the following meaning:
Wait =’0’: the interrupt falls immediately if signal crosses the selected threshold.
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A3G4250D
Register description
Wait =’1’: if signal crosses the selected threshold, the interrupt falls only after the duration
has counted a number of samples at the selected data rate, written into the duration counter
register.
Figure 19. Wait disabled
Figure 20. Wait enabled
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Package information
8
A3G4250D
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at www.st.com.
ECOPACK is an ST trademark.
Figure 21. LGA-16: mechanical data and package dimensions
Dimensions
A1
1.100
A2
0.855
A3
0.200
d
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0.300
D1
3.850
4.000
4.150
E1
3.850
4.000
4.150
L2
1.950
M
0.100
N1
0.650
N2
0.975
P1
1.750
P2
1.525
T1
0.400
T2
0.300
k
0.050
Doc 022768 Rev 3
LGA-16 (4x4x1.1 mm3)
Land Grid Array Package
A3G4250D
9
Revision history
Revision history
Table 66.
Document revision history
Date
Revision
Changes
02-Feb-2012
1
Initial release.
08-Feb-2012
2
Updated notes in Table 4: Mechanical characteristics.
14-Feb-2012
3
Updated Figure 21: LGA-16: mechanical data and package
dimensions.
Doc 022768 Rev 3
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A3G4250D
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