A6986
38 V, 2 A synchronous step-down switching regulator with 30 µA
quiescent current
Datasheet - production data
Description
HTSSOP16 (RTH = 40 °C/W)
Features
AECQ100 qualification
2 A DC output current
4 V to 38 V operating input voltage
Low consumption mode or low noise mode
30 µA IQ at light-load (LCM VOUT = 3.3 V)
8 µA IQ-SHTDWN
Adjustable fSW (250 kHz - 2 MHz)
Output voltage adjustable from 0.85 V to VIN
Embedded output voltage supervisor
Synchronization
Adjustable soft-start time
Internal current limiting
The A6986 device is a step-down monolithic
switching regulator able to deliver up to 2 A DC.
The output voltage adjustability ranges from 0.85
V to VIN. The 100% duty cycle capability to
withstand the cold crank event and the wide input
voltage range make the A6986 device ideal for
battery powered automotive systems. The “Low
Consumption Mode” (LCM) is designed for
applications active during car parking, so it
maximizes the efficiency at the light-load with the
controlled output voltage ripple. The “Low Noise
Mode” (LNM) makes the switching frequency
constant and minimizes the output voltage ripple
overload current range, meeting the low noise
application specification like car audio. The output
voltage supervisor manages the reset phase for
any digital load (µC, FPGA). The RST open
collector output can also implement output
voltage sequencing during the power-up phase.
The synchronous rectification, designed for high
efficiency at the medium - heavy load, and the
high switching frequency capability makes the
size of the application compact. Pulse-by-pulse
current sensing on both power elements
implements effective constant current protection.
Overvoltage protection
Output voltage sequencing
Peak current mode architecture
RDSON HS = 180 m, RDSON LS = 150 m
Thermal shutdown
Applications
Designed for automotive systems
Battery powered applications
Car body applications (LCM)
Car audio and low noise applications (LNM)
August 2020
This is information on a product in full production.
DocID026211 Rev 8
1/68
www.st.com
Contents
A6986
Contents
1
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Datasheet parameters over the temperature range . . . . . . . . . . . . . . . 13
5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2
Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3
Soft-start and inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.1
Ratiometric startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3.2
Output voltage sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.4
Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.5
Light-load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.6
5.7
5.5.1
Low noise mode (LNM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.5.2
Low consumption mode (LCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.6.1
LCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.6.2
LNM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
OCP and switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6
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5.8
Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.9
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DocID026211 Rev 8
A6986
7
Contents
6.1
GCO(s) control to output transfer function . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2
Error amplifier compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3
Voltage divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.4
Total loop gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.5
Compensation network design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.1
Output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.2
Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.3
MLF pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.4
Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.5
Synchronization (LNM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.6
Design of the power components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.6.1
Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.6.2
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.6.3
Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8
Application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9
Efficiency curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.1
HTSSOP16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
11
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
DocID026211 Rev 8
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68
Application schematic
1
A6986
Application schematic
Figure 1. Application schematic
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VSS_L_CLMP SS discharge voltage
VSS START
SSGAIN
VSS_H_CLMP
VCC < VCCH OR
t < TSS SETUPOR
thermal fail
Start of internal error amplifier
ramp
SS/INH to internal error
amplifier gain
(2)
mV
1
A
(2)
4
855
900
945
mV
0.995
1.1
1.15
0
V
3.6
V
3
SS/INH voltage at the end of
SS phase
2.5
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68
Electrical characteristics
A6986
Table 5. Electrical characteristics (continued)
Symbol
Parameter
Test condition
Note Min. Typ. Max. Unit
Error amplifier
VFB
Voltage feedback
IFB
FB biasing current
Gm
Transconductance
AV
Error amplifier gain
ICOMP
0.85
9
V
50
500
nA
90
155
210
70
155
210
0.841 0.85
(4)
(2)
100
±6
EA output current capability
(4)
±12
S
dB
±25
±4
A
Inner current loop
gCS
V PP g CS
Current sense
transconductance (VCOMP to
inductor current gain)
Ipk = 1 A
(5)
(5)
Slope compensation
2.5
A/V
0.4
0.75
1.0
1.15
1.2
1.25
1
2
6
A
Overvoltage protection
VOVP
VOVP HYST
Overvoltage trip (VOVP/VREF)
Overvoltage hysteresis
%
Synchronization (fan out: 6 slave devices typ.)
fSYN MIN
VSYN TH
ISYN
VSYN OUT
Synchronization frequency
LNM; fSW = VCC
266.5
SYNCH input threshold
LNM, SYNCH rising
0.70
SYNCH pulldown current
LNM, VSYN = 1.2 V
high level output
LNM, 5 mA sinking load
low level output
LNM, 0.7 mA sourcing load
Selected RST threshold
MLF pinstrapping before SS
kHz
1.2
0.7
V
mA
1.40
0.6
V
Reset
VTHR
VTHR HYST
VRST
(2)
RST hysteresis
RST open collector output
see Table 7
2
%
VIN > VINH AND
VFB < VTH
4 mA sinking load
0.4
2 < VIN < VINH
4 mA sinking load
0.8
V
Delay
VTHD
RST open collector released
as soon as VDELAY > VTHD
VFB > VTHR
1.19
ID CH
CDELAY charging current
VFB > VTHR
1
10/68
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4
8
2
3
V
A
A6986
Electrical characteristics
Table 5. Electrical characteristics (continued)
Symbol
Parameter
Test condition
Note Min. Typ. Max. Unit
Thermal shutdown
TSHDWN
Thermal shutdown
temperature
(2)
165
THYS
Thermal shutdown hysteresis
(2)
30
°C
1. Parameter tested in static condition during testing phase. Parameter value may change over dynamic application condition.
2. Not tested in production.
3. LCM enables SLEEP mode at light-load.
4. TJ = -40 °C.
5. Measured at fSW = 250 kHz.
All the population tested at TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified.
Table 6. fSW selection
Symbol
fSW
RVCC (E24 series)
RGND (E24 series)
fSW min.
fSW typ.
fSW max.
Note
0
NC
225
250
275
(1)
1.8 k
NC
285
3.3 k
NC
330
5.6 k
NC
380
10 k
NC
435
NC
0
18 k
NC
575
33 k
NC
660
56 k
NC
755
NC
1.8 k
870
NC
3.3 k
NC
5.6 k
1150
NC
10 k
1310
NC
18 k
1500
NC
33 k
1575
1750
1925
NC
56 k
1800
2000
2200
450
900
500
1000
Unit
(2)
550
(1)
(2)
kHz
1100
(2)
(2) (3)
,
(3)
1. Preferred codifications don't require any external resistor.
2. Not tested in production.
3. No synchronization as slave in LNM.
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68
Electrical characteristics
A6986
All the population tested at TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified.
.
Symbol
VRST
Table 7. LNM / LCM selection
RVCC
(E24 series)
RGND
(E24 series)
0
NC
8.2 k ± 1%
NC
18 k ± 1%
NC
39 k ± 1%
Operating
mode
VRST/VOUT
(tgt value)
VRST min. VRST typ. VRST max. Unit
93%
0.779
0.791
0.802
80%
0.670
0.680
0.690
87%
0.728
0.740
0.751
NC
96%
0.804
0.816
0.828
NC
0
93%
0.779
0.791
0.802
NC
8.2 k ± 1%
80%
0.670
0.680
0.690
NC
18 k ± 1%
87%
0.728
0.740
0.751
NC
39 k ± 1%
96%
0.804
0.816
0.828
LCM
LNM
VRST = 0.791 V typical, LNM and LCM preferred codifications don't require any external
resistor.
12/68
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A6986
4
Datasheet parameters over the temperature range
Datasheet parameters over the temperature range
The 100% of the population in the production flow is tested at three different ambient
temperatures (-40 °C, +25 °C, +135 °C) to guarantee the datasheet parameters inside the
junction temperature range (-40 °C, +135 °C).
The device operation is guaranteed when the junction temperature is inside the (-40 °C,
+150 °C) temperature range. The designer can estimate the silicon temperature increase
respect to the ambient temperature evaluating the internal power losses generated during
the device operation.
However the embedded thermal protection disables the switching activity to protect the
device in case the junction temperature reaches the TSHTDWN (+165 °C typ.) temperature.
All the datasheet parameters can be guaranteed to a maximum junction temperature of
+135 °C to avoid triggering the thermal shutdown protection during the testing phase
because of self-heating.
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68
Functional description
5
A6986
Functional description
The A6986 device is based on a “peak current mode”, constant frequency control. As
a consequence, the intersection between the error amplifier output and the sensed inductor
current generates the PWM control signal to drive the power switch.
The device features LNM (low noise mode) that is forced PWM control, or LCM (low
consumption mode) to increase the efficiency at light-load.
The main internal blocks shown in the block diagram in Figure 3 are:
14/68
Embedded power elements. Thanks to the P-channel MOSFET as high-side switch the
device features low dropout operation
A fully integrated sawtooth oscillator with adjustable frequency
A transconductance error amplifier
The high-side current sense amplifier to sense the inductor current
A “Pulse Width Modulator” (PWM) comparator and the driving circuitry of the
embedded power elements
The soft-start blocks to ramp the error amplifier reference voltage and so decreases the
inrush current at power-up. The SS/INH pin inhibits the device when driven low.
The switchover capability of the internal regulator to supply a portion of the quiescent
current when the VBIAS pin is connected to an external output voltage
The synchronization circuitry to manage master / slave operation and the
synchronization to an external clock
The current limitation circuit to implement the constant current protection, sensing
pulse-by-pulse high-side / low-side switch current. In case of heavy short-circuit the
current protection is fold back to decrease the stress of the external components
A circuit to implement the thermal protection function
The OVP circuitry to discharge the output capacitor in case of overvoltage event
MLF pin strapping sets the LNM/LCM mode and the thresholds of the RST comparator
FSW pinstrapping sets the switching frequency
The RST open collector output
DocID026211 Rev 8
A6986
Functional description
Figure 3. Internal block diagram
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Equation 25
1
f PLF = ------------------------------------2 R0 Cc
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68
Closing the loop
A6986
Equation 26
whereas the zero is defined as:
1
f PHF = -------------------------------------------------------2 R0 C0 + Cp
Equation 27
1
f Z = ------------------------------------2 Rc Cc
6.3
Voltage divider
The contribution of a simple voltage divider is:
Equation 28
R2
G DIV s = -------------------R1 + R2
A small signal capacitor in parallel to the upper resistor (see Figure 26) of the voltage divider
implements a leading network (fzero < fpole), sometimes necessary to improve the system
phase margin:
Figure 26. Leading network example
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Equation 32
BW = 67kHz
phase margin = 53
40/68
DocID026211 Rev 8
0
A6986
Closing the loop
Figure 28. Phase plot
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The blue solid trace represents the transfer function including the sampling effect term (see
Equation 22 on page 36), the dotted blue trace neglects the contribution.
6.5
Compensation network design
The maximum bandwidth of the system can be designed up to fSW/6 to guarantee a valid
small signal model.
Equation 33
f SW
BW = --------6
Equation 34
2 BW C OUT V OUT
R C = ---------------------------------------------------------------0.85V g CS g m TYP
where:
Equation 35
p
f POLE = ----------2
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Closing the loop
A6986
p is defined by Equation 20 on page 36, gCS represents the current sense
transconductance (see Table 5: Electrical characteristics on page 8) and gm TYP the error
amplifier transconductance.
Equation 36
5
C C = -------------------------------------2 R C BW
Example 2
Considering VIN = 12 V, VOUT = 3.3 V, L = 6.8 H, COUT = 15 F, fSW = 500 kHz.
The maximum system bandwidth is 80 kHz. Assuming to design the compensation network
to achieve a system bandwidth of 70 kHz:
Equation 37
f POLE = 6kHz
Equation 38
V OUT
R LOAD = -------------- = 2.2
I OUT
so accordingly with Equation 34 and Equation 36:
Equation 39
R C = 68k
Equation 40
C C = 168pF 180pF
42/68
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A6986
Application notes
7
Application notes
7.1
Output voltage adjustment
The error amplifier reference voltage is 0.85 V typical.
The output voltage is adjusted accordingly with Equation 41 (see Figure 29):
Equation 41
R1
V OUT = 0.85 1 + -------
R 2
Cr1 capacitor is sometimes useful to increase the small signal phase margin (please refer to
Section 6.5: Compensation network design).
Figure 29. A6986 application circuit
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The graphical representation of the input RMS current of the input filter in the case of two
devices with 0° phase shift (synchronized to an external signal) or 180° phase shift
(synchronized connecting their SYNCH pins) regulating the same output voltage is provided
in Figure 31. To dimension the proper input capacitor please refer to Chapter 7.6.1: Input
capacitor selection.
Figure 31. Input RMS current
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7.5
Application notes
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DocID026211 Rev 8
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68
Application notes
A6986
Figure 32 shows two regulators not synchronized.
Figure 32. Two regulators not synchronized
Figure 33 shows the same regulators working synchronized. The MASTER regulator (LX2
trace) delivers the synchronization signal (SYNCH1, SYNCH2 pins are connected together)
to the SLAVE device (LX1). The SLAVE regulator works in phase with the synchronization
signal which is out of phase with the MASTER switching operation.
Figure 33. Two regulators synchronized
46/68
DocID026211 Rev 8
A6986
Application notes
Multiple A6986 can be synchronized to an external frequency signal fed to the SYNCH pin.
In this case the regulator set is phased to the reference and all the devices will work with 0°
phase shift.
The frequency range of the synchronization signal is 275 kHz - 1.4 MHz and the minimum
pulse width is 100 nsec (see Figure 34).
Figure 34. Synchronization pulse definition
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Since the slope compensation contribution that is required to prevent subharmonic
oscillations in peak current mode architecture depends on the switching frequency, it is
important to select the same oscillator frequency for all regulators (all of them operate as
SLAVE) as close as possible to the frequency of the reference signal (please refer to
Table 6: fSW selection on page 11). As a consequence all the regulators have the same
resistor value connected to the FSW pin, so the slope compensation is optimized
accordingly with the frequency of the synchronization signal. The slope compensation
contribution is latched at power-up and so fixed during the device operation.
The A6986 normally operates in MASTER mode, driving the SYNCH line at the selected
oscillator frequency as shown in Figure 35 and Figure 32.
In SLAVE mode the A6986 sets the internal oscillator at 250 kHz typ. (see Table 6 on
page 11 - first row) and drives the line accordingly.
Figure 35. A6986 synchronization driving capability
VCC INT
5 mA
fOSC
150nsec typ.
HIGH LEVEL
LOW LEVEL
0.7 mA
In order to safely guarantee that each regulator recognizes itself in SLAVE mode during the
normal operation, the external master must drive the SYNCH pin with a clock signal
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68
Application notes
A6986
frequency higher than the maximum oscillator spread (refer to Table 6 on page 11) for at
least 10 internal clock cycles.
For example: selecting RFSW = 0 to GND
Table 9. Example of oscillator frequency selection from Table 6
Symbol
RVCC (E24 series)
RGND (E24 series)
fSW min.
fSW typ.
fSW max.
fSW
NC
0
450
500
550
the device enters in slave mode after 10 pulses at frequency higher than 550 kHz and so it
is able to synchronize to a clock signal in the range 275 kHz - 1.4 MHz (see Figure 34).
Anyway it is suggested to limit the frequency range within ± 20% FSW resistor nominal
frequency (see details in text below). If not spread spectrum is required, all the regulators
synchronize to a frequency higher to the maximum oscillator spread (550 kHz in the
example).
The device keeps operating in slave mode as far as the master is able to drive the SYNCH
pin faster than 275 kHz (maximum oscillator spread for 250 kHz oscillator), otherwise it goes
back into MASTER mode at the nominal oscillator frequency after successfully driving one
pulse at 250 kHz (see Figure 36) in the SYNCH line.
Figure 36. Slave to master mode transition
switching node
SLAVE mode
250kHz typ. stand alone operation at nominal fsw
SYNCH signal
The external master can force a latched SLAVE mode driving the SYNCH pin low at powerup, before the soft-start starts the switching activity. So the oscillator frequency is 250 kHz
typ. fixed until a new UVLO event is triggered regardless FSW resistor value, that otherwise
counts to design the slope compensation. The same considerations above are also valid.
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A6986
Application notes
The master driving capability must be able to provide the proper signal levels at the SYNCH
pin (see Table 5 on page 8 - Synchronization section):
Low level < VSYN THL= 0.7 V sinking 5 mA
High level > VSYN THH = 1.2 V sourcing 0.7 mA
Figure 37. Master driving capability to synchronize the A6986
VCCM
5 mA
VSYN_TH_H
0.7 mA
VSYN_TH_L
RH
RL
As anticipated above, in SLAVE mode the internal oscillator operates at 250 kHz typ. but the
slope compensation is dimensioned accordingly with FSW resistors so, even if the A6986
supports synchronization over the 275 kHz - 1.4 MHz frequency range, it is important to limit
the switching operation around a working point close to the selected frequency (FSW
resistor).
As a consequence, to guarantee the full output current capability and to prevent the
subharmonic oscillations the master must limit the driving frequency range within ± 20% of
the selected frequency.
A wider frequency range may generate subharmonic oscillation for duty > 50% or limit the
peak current capability (see IPK parameter in Table 5) since the internal slope compensation
signal may be saturated.
In order to guarantee the synchronization as a slave over distribution, temperature and the
output load, the external clock frequency must be lower than 1.4 MHz.
7.6
Design of the power components
7.6.1
Input capacitor selection
The input capacitor voltage rating must be higher than the maximum input operating voltage
of the application. During the switching activity a pulsed current flows into the input capacitor
and so its RMS current capability must be selected accordingly with the application
conditions. Internal losses of the input filter depends on the ESR value so usually low ESR
capacitors (like multilayer ceramic capacitors) have higher RMS current capability. On the
other hand, given the RMS current value, lower ESR input filter has lower losses and so
contributes to higher conversion efficiency.
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Application notes
A6986
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 44
D D
I RMS = I OUT 1 – ---- ---
Where IOUT is the maximum DC output current, D is the duty cycles, is the efficiency. This
function has a maximum at D = 0.5 and, considering = 1, it is equal to Io/2.
In a specific application the range of possible duty cycles has to be considered in order to
find out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:
Equation 45
V OUT + V LOWSIDE
D MAX = -----------------------------------------------------------------------------------------------V INMIN + V LOWSIDE – V HIGHSIDE
Equation 46
V OUT + V LOWSIDE
D MIN = -------------------------------------------------------------------------------------------------V INMAX + V LOWSIDE – V HIGHSIDE
Where VHIGH_SIDE and VLOW_SIDE are the voltage drops across the embedded switches.
The peak to peak voltage across the input filter can be calculated as:
Equation 47
I OUT
D D
V PP = ------------------------- 1 – ---- ---- + ESR I OUT + I L
C IN f SW
In case of negligible ESR (MLCC capacitor) the equation of CIN as a function of the target
VPP can be written as follows:
Equation 48
I OUT
D D
C IN = -------------------------- 1 – ---- ---V PP f SW
Considering this function has its maximum in D = 0.5:
Equation 49
I OUT
C INMIN = ---------------------------------------------4 V PPMAX f SW
Typically CIN is dimensioned to keep the maximum peak-peak voltage across the input filter
in the order of 5% VIN_MAX.
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A6986
Application notes
Table 10. Input capacitors
Manufacturer
TDK
Taiyo Yuden
7.6.2
Series
Size
Cap value (F)
Rated voltage (V)
C3225X7S1H106M
1210
10
50
C3216X5R1H106M
1206
UMK325BJ106MM-T
1210
Inductor selection
The inductor current ripple flowing into the output capacitor determines the output voltage
ripple (please refer to Section 7.6.3). Usually the inductor value is selected in order to keep
the current ripple lower than 20% - 40% of the output current over the input voltage range.
The inductance value can be calculated by Equation 50:
Equation 50
V IN – V OUT
V OUT
I L = ------------------------------ T ON = -------------- T OFF
L
L
Where TON and TOFF are the on and off time of the internal power switch. The maximum
current ripple, at fixed VOUT, is obtained at maximum TOFF that is at minimum duty cycle
(see Section 7.6.1: Input capacitor selection to calculate minimum duty). So fixing IL = 20%
to 40% of the maximum output current, the minimum inductance value can be calculated:
Equation 51
V OUT 1 – D MIN
L MIN = ------------------- ----------------------I LMAX
F SW
where fSW is the switching frequency 1/(TON + TOFF).
For example for VOUT = 3.3 V, VIN = 12 V, IO = 2 A and FSW = 500 kHz the minimum
inductance value to have IL = 30% of IO is about 8.2 µH.
The peak current through the inductor is given by:
Equation 52
I L
I L PK = I OUT + -------2
So if the inductor value decreases, the peak current (that has to be lower than the current
limit of the device) increases. The higher is the inductor value, the higher is the average
output current that can be delivered, without reaching the current limit.
In Table 11 some inductor part numbers are listed.
Table 11. Inductors
Manufacturer
Series
Inductor value (H)
Saturation current (A)
Coilcraft
XAL50xx
2.2 to 22
6.5 to 2.7
XAL60xx
2.2 to 22
12.5 to 4
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Application notes
7.6.3
A6986
Output capacitor selection
The triangular shape current ripple (with zero average value) flowing into the output
capacitor gives the output voltage ripple, that depends on the capacitor value and the
equivalent resistive component (ESR). As a consequence the output capacitor has to be
selected in order to have a voltage ripple compliant with the application requirements.
The voltage ripple equation can be calculated as:
Equation 53
I LMAX
V OUT = ESR I LMAX + --------------------------------------8 C OUT f SW
Usually the resistive component of the ripple can be neglected if the selected output
capacitor is a multi layer ceramic capacitor (MLCC).
The output capacitor is important also for loop stability: it determines the main pole and the
zero due to its ESR. (see Section 6: Closing the loop on page 35 to consider its effect in the
system stability).
For example with VOUT = 3.3 V, VIN = 12 V, IL = 0.6 A, fSW = 500 kHz (resulting by the
inductor value) and COUT = 10 F MLCC:
Equation 54
V OUT
I LMAX
1
1
0 6
15mV
------------------ -------------- ------------------------------ = ------ -------------------------------------------------- = ---------------- = 0.45%
33 8 10F 500kHz
V OUT V OUT C OUT f SW
3.3
The output capacitor value has a key role to sustain the output voltage during a steep load
transient. When the load transient slew rate exceeds the system bandwidth, the output
capacitor provides the current to the load. In case the final application specifies high slew
rate load transient, the system bandwidth must be maximized and the output capacitor has
to sustain the output voltage for time response shorter than the loop response time.
In Table 12 some capacitor series are listed.
Table 12. Output capacitors
Manufacturer
Series
Cap value (F)
Rated voltage (V)
ESR (m)
GRM32
22 to 100
6.3 to 25
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