A7985ATR

A7985A 2 A step-down switching regulator for automotive applications Datasheet - production data Applications  Dedicated to automotive applications  Automotive LED driving HSOP8 exposed pad Description The A7985A is a step-down switching regulator with a 2.5 A (minimum) current limited embedded power MOSFET, so it is able to deliver up to 2 A current to the load depending on the application conditions. Features  AEC-Q100 qualified (see PPAP for more details)  2 A DC output current The input voltage can range from 4.5 V to 38 V, while the output voltage can be set starting from 0.6 V to VIN.  4.5 V to 38 V input voltage  Output voltage adjustable from 0.6 V  250 kHz switching frequency, programmable up to 1 MHz Requiring a minimum set of external components, the device includes an internal 250 kHz switching frequency oscillator that can be externally adjusted up to 1 MHz.  Internal soft-start and enable  Low dropout operation: 100% duty cycle The HSOP8 package with exposed pad allows the reduction of Rth(JA) down to 40 °C/W.  Voltage feed-forward  Zero load current operation  Overcurrent and thermal protection  HSOP8 package Figure 1. Application circuit / 9,1 9WR9 9&& (1 *1' &LQ 9RXW 9WR 9&& 287     $$  ' 6 0.6 V - - 0.1 Source COMP pin VFB = 0.5 V, VCOMP = 1 V - 19 - mA Sink COMP pin VFB = 0.7 V, VCOMP = 0.75 V - 30 - mA Open loop voltage gain (1) - 100 - dB IO SOURCE IO SINK GV 8/43 DocID023128 Rev 7 V A7985A Electrical characteristics Table 4. Electrical characteristics (continued) Values Symbol Parameter Test conditions Unit Min. Typ. Max. Synchronization function VS_IN,HI High input voltage - 2 - 3.3 VS_IN,LO Low input voltage - - - 1 tS_IN_PW Input pulse width VS_IN,HI = 3 V, VS_IN,LO = 0 V 100 - - VS_IN,HI = 2 V, VS_IN,LO = 1 V 300 - - ISYNCH,LO Slave sink current VSYNCH = 2.9 V - 0.7 1 mA VS_OUT,HI Master output amplitude ISOURCE = 4.5 mA 2 - - V tS_OUT_PW Output pulse width SYNCH floating - 110 - ns Thermal shutdown - - 150 - Hysteresis - - 30 - V ns Protection TSHDN °C 1. Guaranteed by design. DocID023128 Rev 7 9/43 43 Functional description 5 A7985A Functional description The A7985A device is based on a “voltage mode”, constant frequency control. The output voltage VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing an error signal that, compared to a fixed frequency sawtooth, controls the ON and OFF time of the power switch. The main internal blocks are shown in the block diagram in Figure 3. They are:  A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the synchronization signal. Its switching frequency can be adjusted by an external resistor. The voltage and frequency feed-forward are implemented  Soft-start circuitry to limit inrush current during the startup phase  Voltage mode error amplifier  Pulse width modulator and the relative logic circuitry necessary to drive the internal power switch  High-side driver for embedded P-channel power MOSFET switch  Peak current limit sensing block, to handle overload and short-circuit conditions  A voltage regulator and internal reference. It supplies internal circuitry and provides a fixed internal reference  A voltage monitor circuitry (UVLO) that checks the input and internal voltages  A thermal shutdown block, to prevent thermal runaway. Figure 3. Block diagram VCC REGULATOR TRIMMING EN & BANDGAP EN 1.254V 3.3V 0.6V COMP UVLO PEAK CURRENT LIMIT THERMAL SOFTSTART SHUTDOWN E/A PWM DRIVER S Q R OUT OSCILLATOR FB 10/43 FSW GND DocID023128 Rev 7 SYNCH & PHASE SHIFT SYNCH A7985A 5.1 Functional description Oscillator and synchronization Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides a constant frequency clock. Its frequency depends on the resistor externally connected to the FSW pin. If the FSW pin is left floating, the frequency is 250 kHz; it can be increased as shown in Figure 6 by an external resistor connected to ground. To improve the line transient performance, keeping the PWM gain constant versus the input voltage, the voltage feed-forward is implemented by changing the slope of the sawtooth according to the input voltage change (see Figure 5.a). The slope of the sawtooth also changes if the oscillator frequency is increased by the external resistor. In this way, a frequency feed-forward is implemented (Figure 5.b) in order to keep the PWM gain constant versus the switching frequency (see Section 6.4 on page 20 for PWM gain expression). On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of 180 ° with respect to the clock. This delay is useful when two devices are synchronized connecting the SYNCH pin together. When SYNCH pins are connected, the device with the higher oscillator frequency works as master, so the slave device switches at the frequency of the master but with a delay of half a period. This minimizes the RMS current flowing through the input capacitor (see the L5988D datasheet). Figure 4. Oscillator circuit block diagram Clock FSW Clock Generator Synchronization SYNCH Ramp Generator Sawtooth The device can be synchronized to work at a higher frequency feeding an external clock signal. The synchronization changes the sawtooth amplitude, changing the PWM gain (Figure 5.c). This change must be taken into account when the loop stability is studied. To minimize the change of the PWM gain, the free-running frequency should be set (with a resistor on the FSW pin) only slightly lower than the external clock frequency. This preadjusting of the frequency changes the sawtooth slope in order to render negligible the truncation of sawtooth, due to the external synchronization. DocID023128 Rev 7 11/43 43 Functional description A7985A Figure 5. Sawtooth: voltage and frequency feed-forward; external synchronization Figure 6. Oscillator frequency vs. the FSW pin resistor   )6:>N+]@             5)6:>N2KPV@ 12/43 DocID023128 Rev 7    A7985A Functional description where: Equation 1 9 28.5  10 3 R FSW = -----------------------------------------3 – 3.23  10 F SW – 250  10 FSW is desired switching frequency. 5.2 Soft-start Soft-start is essential to assure the correct and safe startup of the step-down converter. It avoids inrush current surge and makes the output voltage increase monothonically. The soft-start is performed by a staircase ramp on the non inverting input (VREF) of the error amplifier. So the output voltage slew rate is: Equation 2 R1 SR OUT = SR VREF   1 + --------  R2 where SRVREF is the slew rate of the non inverting input, while R1and R2 is the resistor divider to regulate the output voltage (see Figure 7). The soft-start staircase consists of 64 steps of 9.5 mV each, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles. So the soft-start time and then the output voltage slew rate depend on the switching frequency. Figure 7. Soft-start scheme Soft-start time results: Equation 3 32  64 SS TIME = ----------------Fsw For example, with a switching frequency of 250 kHz, the SSTIME is 8 ms. DocID023128 Rev 7 13/43 43 Functional description 5.3 A7985A Error amplifier and compensation The error amplifier (E/A) provides the error signal to be compared with the sawtooth to perform the pulse width modulation. Its non inverting input is internally connected to a 0.6 V voltage reference, while its inverting input (FB) and output (COMP) are externally available for feedback and frequency compensation. In this device the error amplifier is a voltage mode operational amplifier, so with high DC gain and low output impedance. The uncompensated error amplifier characteristics are shown in Table 5. Table 5. Uncompensated error amplifier characteristics Parameter Value Low frequency gain 100 dB GBWP 4.5 MHz Slew rate 7 V/s Output voltage swing 0 to 3.3 V Maximum source/sink current 17 mA/25 mA In continuous conduction mode (CCM), the transfer function of the power section has two poles due to the LC filter and one zero due to the ESR of the output capacitor. Different kinds of compensation networks can be used depending on the ESR value of the output capacitor. In case the zero introduced by the output capacitor helps to compensate the double pole of the LC filter, a Type II compensation network can be used. Otherwise, a Type III compensation network must be used (see Section 6.4 on page 20 for details of the compensation network selection). The methodology to compensate the loop is to introduce zeroes to obtain a safe phase margin. 5.4 Overcurrent protection The A7985A implements the overcurrent protection sensing current flowing through the power MOSFET. Due to the noise created by the switching activity of the power MOSFET, the current sensing is disabled during the initial phase of the conduction time. This avoids an erroneous detection of a fault condition. This interval is generally known as “masking time” or “blanking time”. The masking time is about 200 ns. If the overcurrent limit is reached, the power MOSFET is turned off, implementing the pulseby-pulse overcurrent protection. Under an overcurrent condition, the device can skip turn-on pulses in order to keep the output current constant and equal to the current limit. If, at the end of the “masking time”, the current is higher than the overcurrent threshold, the power MOSFET is turned off and one pulse is skipped. If, at the following switching-on, when the “masking time” ends, the current is still higher than the overcurrent threshold, the device skips two pulses. This mechanism is repeated and the device can skip up to seven pulses. While, if at the end of the “masking time” the current is lower than the over current threshold, the number of skipped cycles is decreased by one unit (see Figure 8). So the overcurrent/short-circuit protection acts by switching off the power MOSFET and reducing the switching frequency down to one eighth of the default switching frequency, in order to keep constant the output current around the current limit. 14/43 DocID023128 Rev 7 A7985A Functional description This kind of overcurrent protection is effective if the output current is limited. To prevent the current from diverging, the current ripple in the inductor during the ON-time must not be higher than the current ripple during the OFF-time. That is: Equation 4 V IN – V OUT – R DSON  I OUT – DCR  I OUT V OUT + V F + R DSON  I OUT + DCR  I OUT ------------------------------------------------------------------------------------------------------------  D = -----------------------------------------------------------------------------------------------------------   1 – D  L  F SW L  F SW If the output voltage is shorted, VOUT 0, IOUT = ILIM, D/FSW = TON_MIN, (1-D)/FSW 1/FSW. So from the above equation the maximum switching frequency that guarantees to limit the current results: Equation 5  V F + DCR  I LIM  1 F *SW = -------------------------------------------------------------------------------  --------------------- V IN –  R DSON + DCR   I LIM  T ON_MIN With RDS(on) = 300 m, DRC = 0.08 , the worst condition is with VIN = 38 V, ILIM = 2.5 A; the maximum frequency to keep the output current limited during the short-circuit results 74 kHz. Based on the pulse-by-pulse mechanism, that reduces the switching frequency down to one eighth, the maximum FSW, adjusted by the FSW pin, that assures a full effective output current limitation is 74 kHz * 8 = 592 kHz. If, with VIN = 38 V, the switching frequency is set higher than 592 kHz, during short-circuit condition the system finds a different equilibrium with higher current. For example, with FSW = 700 kHz and the output shorted to ground, the output current is limited around: Equation 6 V IN  F *SW – V F  T ON_MIN I OUT = ---------------------------------------------------------------------------------------------------------------- = 3.68A  DRC  T ON_MIN  +  R DSON + DCR   F *SW where FSW* is 700 kHz divided by eight. DocID023128 Rev 7 15/43 43 Functional description A7985A Figure 8. Overcurrent protection 5.5 Enable function The enable feature allows the device to be put into standby mode. With the EN pin lower than 0.3 V, the device is disabled and the power consumption is reduced to less than 30A. With the EN pin lower than 1.2 V, the device is enabled. If the EN pin is left floating, an internal pull-down ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also VCC compatible. 5.6 Hysteretic thermal shutdown The thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 °C. Once the junction temperature goes back to about 120 °C, the device restarts in normal operation. The sensing element is very close to the PDMOS area, so ensuring an accurate and fast temperature detection. 16/43 DocID023128 Rev 7 A7985A Application information 6 Application information 6.1 Input capacitor selection The capacitor connected to the input must be capable of supporting the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency. So the input capacitor must have an RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency. The maximum RMS input current flowing through the capacitor can be calculated as: Equation 7 2 2 2D D I RMS = I O  D – --------------- + ------2  where Io is the maximum DC output current, D is the duty cycle, is the efficiency. Considering = 1, this function has a maximum at D = 0.5 and it is equal to Io/2. In a specific application the range of possible duty cycles must be considered in order to find out the maximum RMS input current. The maximum and minimum duty cycles can be calculated as: Equation 8 V OUT + V F D MAX = ------------------------------------V INMIN – V SW and Equation 9 V OUT + V F D MIN = -------------------------------------V INMAX – V SW where VF is the forward voltage on the freewheeling diode and VSW is voltage drop across the internal PDMOS. The peak-to-peak voltage across the input capacitor can be calculated as: Equation 10 IO D D V PP = -------------------------   1 – ----  D + ----   1 – D  + ESR  I O C IN  F SW    where ESR is the equivalent series resistance of the capacitor. Given the physical dimension, ceramic capacitors can well meet the requirements of the input filter sustaining a higher input RMS current than electrolytic/tantalum types. DocID023128 Rev 7 17/43 43 Application information A7985A In this case, the equation of CIN as a function of the target VPP can be written as follows: Equation 11 IO D D C IN = ---------------------------   1 – ----  D + ----   1 – D  V PP  F SW    neglecting the small ESR of ceramic capacitors. Considering = 1, this function has its maximum in D = 0.5, therefore, given the maximum peak-to-peak input voltage (VPP_MAX), the minimum input capacitor (CIN_MIN) value is: Equation 12 IO C IN_MIN = -----------------------------------------------2  V PP_MAX  F SW Typically, CIN is dimensioned to keep the maximum peak-to-peak voltage in the order of 1% of VINMAX. In Table 6, some multi-layer ceramic capacitors suitable for this device are reported. Table 6. Input MLCC capacitors Manufacturer Taiyo Yuden muRata Series Cap value (F) Rated voltage (V) UMK325BJ106MM-T 10 50 GMK325BJ106MN-T 10 35 GRM32ER71H475K 4.7 50 A ceramic bypass capacitor, as close to the VCC and GND pins as possible, so that additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability on the output voltage due to noise. The value of the bypass capacitor can go from 100 nF to 1 µF. 6.2 Inductor selection The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value in order to have the expected current ripple must be selected. The rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current. In continuous current mode (CCM), the inductance value can be calculated by the following equation: Equation 13 V IN – V OUT V OUT + V F I L = ------------------------------  T ON = ----------------------------  T OFF L L where TON is the conduction time of the internal high-side switch and TOFF is the conduction time of the external diode [in CCM, FSW = 1/(TON + TOFF)]. The maximum current ripple, at fixed VOUT, is obtained at maximum TOFF, that is at minimum duty cycle (see Section 6.1 to calculate minimum duty). So by fixing IL = 20% to 30% of the maximum output current, the minimum inductance value can be calculated: 18/43 DocID023128 Rev 7 A7985A Application information Equation 14 V OUT + V F 1 – D MIN L MIN = ----------------------------  ----------------------I MAX F SW where FSW is the switching frequency, 1/(TON + TOFF). For example, for VOUT = 5 V, VIN = 24 V, IO = 2 A and FSW = 250 kHz, the minimum inductance value to have IL= 30% of IO is about 28 H. The peak current through the inductor is given by: Equation 15 I L I L PK = I O + -------2 So if the inductor value decreases, then the peak current (that must be lower than the minimum current limit of the device) increases. According to the maximum DC output current for this product family (2 A), the higher the inductor value, the higher the average output current that can be delivered, without triggering the overcurrent protection. In Table 7 some inductor part numbers are listed. Table 7. Inductors Manufacturer Coilcraft Wurth SUMIDA 6.3 Series Inductor value (H) Saturation current (A) MSS1038 3.8 to 10 3.9 to 6.5 MSS1048 12 to 22 3.84 to 5.34 PD Type L 8.2 to 15 3.75 to 6.25 PD Type M 2.2 to 4.7 4 to 6 CDRH6D226/HP 1.5 to 3.3 3.6 to 5.2 CDR10D48MN 6.6 to 12 4.1 to 5.7 Output capacitor selection The current in the capacitor has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge or discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements. The amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection. Equation 16 I MAX V OUT = ESR  I MAX + ------------------------------------8  C OUT  f SW Usually the resistive component of the ripple is much higher than the capacitive one, if the output capacitor adopted is not a multi-layer ceramic capacitor (MLCC) with very low ESR value. DocID023128 Rev 7 19/43 43 Application information A7985A The output capacitor is important also for loop stability: it fixes the double LC filter pole and the zero due to its ESR. In Section 6.4, how to consider its effect in the system stability is illustrated. For example, with VOUT = 5 V, VIN = 24 V, IL = 0.9 A (resulting by the inductor value), in order to have a VOUT = 0.01 · VOUT, if the multi-layer ceramic capacitors are adopted, 10 µF are needed and the ESR effect on the output voltage ripple can be neglected. In case of not-negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its ESR value. So, in the case of 330 µF with ESR = 70 mthe resistive component of the drop dominates and the voltage ripple is 43 mV The output capacitor is also important to sustain the output voltage when a load transient with high slew rate is required by the load. When the load transient slew rate exceeds the system bandwidth the output capacitor provides the current to the load. So if the high slew rate load transient is required by the application, the output capacitor and system bandwidth must be chosen in order to sustain the load transient. In Table 8 below some capacitor series are listed. Table 8. Output capacitors Manufacturer Series Cap value (F) Rated voltage (V) ESR (m) GRM32 22 to 100 6.3 to 25