A7987TR

A7987 Datasheet 61 V, 3 A asynchronous step-down switching regulator with adjustable current limitation for automotive Features • • • 3 A DC output current 4.5 V to 61 V operating input voltage Adjustable fsw (250 kHz to 1.5 MHz) • Output voltage adjustable from 0.8 V to VIN • • • • • • • • Synchronization Adjustable soft-start time Adjustable current limitation VBIAS improves efficiency at light load PGOOD open collector output Digital frequency fold-back in short-circuit Auto-recovery thermal shutdown Qualified following AEC-Q100 requirements Applications • • Designed for 24 V automotive battery systems Industrial and commercial vehicles Description Product status link A7987 The A7987 is a step-down monolithic switching regulator that can deliver up to 3 A DC. The adjustable output voltage ranges from 0.8 V to VIN. The wide input voltage range and the almost 100% duty cycle capability meet the fail-safe specifications for automotive systems. The embedded switch-over feature on the VBIAS pin maximizes efficiency at light load. The adjustable current limitation, designed to select the inductor RMS current in accordance with the nominal output current, and the high switching frequency capability make the size of the application compact. Pulse-bypulse current sensing with digital frequency fold-back implements an effective constant current protection over the different application conditions. The peak current fold-back decreases the stress of the power components in heavy short-circuit conditions. The PGOOD open collector output can also implement the output voltage sequencing during the power-up phase. Multiple devices can be synchronized sharing the SYNCH pin to prevent beating noise for low noise requirements such as in infotainment applications. DS12928 - Rev 3 - September 2020 For further information contact your local STMicroelectronics sales office. www.st.com A7987 Application schematic 1 Application schematic Figure 1. Application schematic R1 PGOOD U1 7 SYNCH PGOOD 2 VIN 3 VIN VIN 4 5 6 10 100 V 100 V 11 VCC VBIAS A7987 SS FSW TP GND COMP 17 C1 C4 C10 VOUT 15 C7 13 LX 14 LX 9 FB EN ILIM BOOT 12 1 16 L1 R5 R6 8 C9 C8 R7 C11 D1 R11 C5 GND DS12928 - Rev 3 GND page 2/36 A7987 Block diagram 2 Block diagram Figure 2. Block diagram VCC VBIAS VIN BOOT EN EN ENABLE VREG BOOT UVLO CHARGE ISNS CURRENT SENSING REF and BIAS VRAMP + FB FB - E/A HS - PWM DRIVER COMP + EN SOFT LOGIC and CONTROL TEMP OUT MONITOR START LS DRIVER ISS - PG SS COMP + FB PGOOD VRAMP COMP DS12928 - Rev 3 FSW OSCILLATOR MASTER ILIM & RAMP SLAVE FUNCTION SYNCH GND ILIM page 3/36 A7987 Pin settings 3 Pin settings 3.1 Pin connection Figure 3. Pin connection (top view) 1 16 GND VIN 2 15 BOOT VIN 3 14 LX VBIAS 3.2 VCC 4 EN 5 EXPOSED PAD TO SGND 13 LX 12 PGOOD SS 6 11 ILIM SYNCH 7 10 FSW COMP 8 9 FB Pin description Table 1. Pin description # DS12928 - Rev 3 Pin Description 1 VBIAS The auxiliary input can be used to supply part of the analog circuitry to increase the efficiency at light load. It is typically connected to the regulated output voltage or to an external voltage rail higher than 3 V. Connect to GND if it is not used or bypass with a 1 µF ceramic capacitor if supplied by the output voltage or by an auxiliary rail 2 VIN DC input voltage 3 VIN DC input voltage 4 VCC Filtered DC input voltage to the internal circuitry. Bypass to GND with a 1 µF ceramic capacitor 5 EN Active high enable pin. Connect to VCC pin if it is not used 6 SS Soft-start programming pin. An internal current generator (5 µA typ.) charges the external capacitor to implement the soft-start 7 SYNCH Master / slave synchronization 8 COMP 9 FB 10 FSW A pull-down resistor to GND selects the switching frequency 11 ILIM A pull-down resistor to GND selects the peak current limitation Output of the error amplifier. The designed compensation network is connected on this pin. Inverting input of the error amplifier 12 PGOOD The PGOOD open collector output is driven low when the output voltage, sensed on the FB pin, is out of regulation 13 LX Switching node 14 LX Switching node 15 BOOT 16 GND Connect an external capacitor (100 nF typ.) between BOOT and LX pins. The gate charge required to drive the internal n-DMOS is recovered by an internal regulator during the off-time Signal GND page 4/36 A7987 Maximum ratings 3.3 # Pin -- E.P. Description Exposed pad must be connected to signal GND Maximum ratings Table 2. Absolute maximum ratings Symbol Description Min. Max. Unit VIN -0.3 61 V VCC -0.3 61 V VBOOT - GND -0.3 65 V VBOOT – VLX -0.3 4 V VBIAS -0.3 VCC V EN -0.3 VCC V PGOOD -0.3 VCC V LX -0.3 VIN+0.3 V SYNCH -0.3 5.5 V SS -0.3 3.6 V FSW -0.3 3.6 V COMP -0.3 3.6 V ILIM -0.3 3.6 V FB -0.3 3.6 V BOOT 3.4 TJ Operating temperature range -40 150 °C TSTG Storage temperature range -65 150 °C TLEAD Lead temperature (soldering 10 s) 260 °C IHS High-side RMS current 3 A Thermal data Table 3. Thermal data Symbol RthJA 3.5 Parameter Thermal resistance junction-ambient (device soldered on the STMicroelectronics evaluation board) Value Unit 40 °C/W ESD protection Table 4. ESD protection Symbol ESD DS12928 - Rev 3 Test conditions Value Unit HBM 2 kV CDM 500 V page 5/36 A7987 Electrical characteristics 4 Electrical characteristics TJ = -40 °C to +125 °C, VIN = VCC = 24 V and VEN =3 V unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter VIN Operating input voltage range RDSON HS High- side RDS(on) Switching frequency fSW Test conditions Peak current limit Typ. 4.5 Max. Unit 61 V ISW=0.5 A; Tj = 25 °C 0.25 0.32 Ω ISW=0.5 A 0.25 0.46 Ω FSW floating; Tj = 25 °C 233 250 267 kHz FSW floating 225 250 275 kHz RFSW=10 kΩ 1350 1500 1650 kHz Selected switching frequency IPK Min. RLIM 20 kΩ; VFB = 0.6 V; TJ = 125 °C (1) 3.2 3.7 4.4 A RLIM 100 kΩ; VFB = 0.6 V (1) 0.69 0.84 1.0 A Ratio IPK_20k/IPK_100k (2) 4.7 ISKIP Pulse skipping peak current (2) 0.5 A VFOLD Feedback fold-back level (2) 400 mV TONMAX Maximum on-time 12 µs TONMIN Minimum on-time 120 TOFFMIN Minimum off-time (2) 150 360 ns ns VCC / VBIAS VCCH VCC UVLO rising threshold 3.85 4.10 4.30 V VCCHYST VCC UVLO hysteresis 150 250 380 mV 2.84 2.90 3.03 V VBIAS threshold Switch internal supply from VCC to VBIAS. VBIAS ramping up from 0 V Hysteresis SWO VCC -VBIAS threshold Switch internal supply from VCC to VBIAS. VIN=VCC=24 V, VBIAS falling from 24 V to GND 80 3.35 Hysteresis 4.05 mV 4.90 900 V mV Power consumption ISHTDWN Shutdown current from VIN IQUIESC Quiescent current from VIN and VCC IQOPVIN Quiescent current from VIN and VCC IQOPVBIAS Quiescent current from VBIAS VEN = GND; TJ = 25 °C 11 16 VEN = GND 23 45 LX floating, VFB=1 V, VBIAS=GND, FSW floating 2.5 3.0 mA 1.0 1.3 mA 1.6 2.2 mA LX floating, VFB=1 V, VBIAS=3.3 V, FSW floating µA Enable VEN Device OFF level 0.06 0.30 V Device ON level 0.35 0.90 V Soft-start DS12928 - Rev 3 page 6/36 A7987 Electrical characteristics Symbol Parameter Test conditions TSSSETUP Soft-start set-up time Delay from UVLO rising to switching activity ISS CH CSS charging current VSS=0 Min. (2) Typ. Max. Unit 640 4.3 5.0 µs 5.7 mA Error amplifier VFB Voltage feedback VFB Voltage feedback Tj = 25 °C VCOMPH VFB=GND; VSS=3.2 V VCOMPL VFB=1 V; VSS=3.2 V IFB 0.792 0.800 0.808 V 0.788 0.800 0.812 V 3.00 3.65 V 0.1 V 50 nA VFB=3.6 V FB biasing current 3.35 5 IOSOURCE VFB=GND; SS pin floating; VCOMP=2 V (2) 3.1 mA IOSINK Output stage sinking capability Unity gain buffer configuration (FB connected to COMP).COMP voltage variation due to IOSINK injection lower than ± 0.1·VFB (2) 5 mA AV0 Error amplifier gain (2) 100 dB (2) 23 MHz Unity gain buffer configuration (FB connected to COMP). No load on COMP pin GBWP Synchronization (fan out: 5 slave devices max.) fSYN MIN Synchronization frequency VSYNOUT Master output amplitude VSYNOW Output pulse width VSYNIH SYNCH slave high level input threshold VSYNIL SYNCH slave low level input threshold ISYN Slave SYNCH pull-down current VSYNIW Input pulse width FSW floating 280 ILOAD=4 mA 2.45 kHz ILOAD=0 A; pin SYNCH floating 4.0 ILOAD=0 A; pin SYNCH floating 150 225 275 2.0 VSYNCH = 5 V 400 V ns V 650 1.0 V 900 µA 150 ns PGOOD VPGDTH PGOOD rising threshold VFB rising VPGDHYST PGOOD hysteresis VFB falling VPGDLOW PGOOD low level IPGOOD=1 mA, VFB=GND 0.67 (2) 0.70 PGOOD leakage current V 30 mV 30 mV VPGOOD=61 V;VFB=0.8 V; IPGDLKG 0.74 0.1 Tj = 25 °C µA VPGOOD=61 V;VFB=0.8 V 20 Thermal shutdown TSHDWN THYS Thermal shutdown temperature (2) 170 °C Thermal shutdown hysteresis (2) 15 °C 1. Parameter tested in a static condition during the testing phase. The parameter value may change over dynamic application conditions. 2. Not tested in production. DS12928 - Rev 3 page 7/36 A7987 Functional description 5 Functional description The A7987 device is based on a voltage mode, constant frequency control loop. The output voltage VOUT, sensed by the feedback pin (FB), is compared to an internal reference (0.8 V) providing an error signal on the COMP pin. The COMP voltage level is then compared to a fixed frequency sawtooth ramp, which finally controls the on- and off-time of the power switch. The main internal blocks are shown in the block diagram in Figure 2. Block diagram and can be summarized as follows: The fully integrated oscillator provides the sawtooth ramp to modulate the duty cycle and the synchronization • signal. Its switching frequency can be adjusted by an external resistor. The input voltage feed-forward is implemented • The soft-start circuitry to limit the inrush current during the start-up phase • The voltage mode error amplifier • The pulse width modulator and the relative logic circuitry necessary to drive the internal power switch • The high-side driver for embedded N-channel power MOSFET switch and bootstrap circuitry. A dedicated high-resistance low-side MOSFET, for anti-boot discharge management purposes, is also present • The peak current limit sensing block, with programmable threshold, to handle overload and short-circuit conditions including current fold-back and a thermal shutdown block, to prevent thermal runaway • The voltage regulator and the internal reference to supply the internal circuitry and provide a fixed internal reference. The switchover function from VCC to VBIAS can be implemented for higher efficiency. This block also implements a voltage monitor circuitry (UVLO) that checks the input and internal voltages • The output voltage monitor circuitry releases the PGOOD signal if the sensed output voltage is above 87% of the target value 5.1 Oscillator and synchronization Figure 4. Oscillator and synchronization shows the block diagram of the oscillator circuit. The internal oscillator provides a constant frequency clock, whose frequency depends on the resistor externally connected between the FSW pin and ground. Figure 4. Oscillator and synchronization clock FSW 180° phase shift Clock Generator Synchronization Ramp Generator SYNCH Sawtooth If the FSW pin is left floating, the programmed frequency is 250 kHz (typ.); if FSW pin is connected to an external resistor the programmed switching frequency can be increased up to 1.5 MHz, as shown in Figure 5. Switching frequency programmability. The required RFSW value (expressed in kΩ) is estimated by the following equation: 12500 FSW = 250kHz + RFSW DS12928 - Rev 3 (1) page 8/36 A7987 Oscillator and synchronization Fsw [kHz] Figure 5. Switching frequency programmability 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 10 20 30 40 50 60 70 80 90 100 RFSW [kOhm] To improve the line transient performance, keeping the PWM gain constant versus the input voltage, the input voltage feed-forward is implemented by changing the slope of the sawtooth ramp, according to the input voltage change (Figure 6. Feed-forward6a). The slope of the sawtooth also changes if the oscillator frequency is programmed by the external resistor. In this manner, a frequency feed-forward is implemented (Figure 6. Feed-forward6b) in order to keep the PWM modulator gain constant versus the switching frequency. On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of 180 ° with respect to the clock. This delay is useful when two devices are synchronized connecting the SYNCH pins together. When SYNCH pins are connected, the device with a higher oscillator frequency works as master, so the slave device switches at the frequency of the master but with a delay of half period. This helps reducing the RMS current flowing through the input capacitor. Up to five A7987s can be connected to the same SYNCH pin; however, the clock phase shift from master switching frequency to slaves input clock is 180 °. The A7987 can be synchronized to work at a higher frequency, in the range 250 kHz-1500 kHz, providing the SYNCH pin with an external clock signal. The synchronization changes the sawtooth amplitude, also affecting the PWM gain (Figure 6. Feed-forward6c). This change must be taken into account when the loop stability is studied. In order to minimize the change of PWM gain, the free-running frequency should be set (with a resistor on the FSW pin) only slightly lower than the external clock frequency. This pre-adjusting of the slave IC switching frequency keeps the truncation of the ramp sawtooth negligible. In case two or more (up to five) A7987 SYNCH pins are tied together, the A7987 IC with higher programmed switching frequency is typically the master device; however, the SYNCH circuit is also able to synchronize with a slightly lower external frequency, so the frequency pre-adjustment with the same resistor on FSW pin, as suggested above, is required for a proper operation. DS12928 - Rev 3 page 9/36 A7987 Soft-start Figure 6. Feed-forward 5.2 Soft-start The soft-start is essential to ensure a correct and safe start-up of the step-down converter. It avoids inrush current surge and makes the output voltage increase monotonically. The soft-start is performed by charging an external capacitor, connected between SS pin and ground, with a constant current (5 µA typ.). The SS voltage is used as reference of the switching regulator and the output voltage of the converter tracks the ramp of the SS voltage. When the SS pin voltage reaches 0.8 V level, the error amplifier switches to the internal 0.8 V ±1% reference to regulate the output voltage. DS12928 - Rev 3 page 10/36 A7987 Soft-start Figure 7. Soft-start Vref 800 mV Iss SS Css + + ERROR COMP Vout AMPLIFIER - Rf Cp Ru FB Cf Rd During the soft-start period the current limit is set to the nominal value. The dVSS/dt slope is programmed in agreement with the following equation: CSS = ISS ⋅ TSS 5μA ⋅ TSS = VREF 0.8V (2) Before starting the CSS capacitor charge, the soft-start circuitry turns on the discharge switch shown in Figure 7. Soft-start for TSSDISCH minimum time, in order to completely discharge the CSS capacitor. As a consequence, the maximum value for the soft-start capacitor, which assures an almost complete discharge in case of EN signal toggle, is provided by: TSSDISCH ≅ 270nF CSS_MAX ≤ 5 ⋅ RSSDISCH (3) given TSSDISCH = 530 µs and RSSDISCH = 380 Ω typical values. The enable feature allows the device to be in standby mode. With the EN pin lower than device OFF level, the device is disabled and the power consumption is reduced to less than 11 μA (typ.). With the EN pin higher than device ON level, the device is enabled. If the EN pin is left floating, an internal pull-down current ensures that the voltage on the pin reaches the inhibit threshold and the device is disabled. The pin is also VCC compatible. DS12928 - Rev 3 page 11/36 A7987 Error amplifier and light-load management 5.3 Error amplifier and light-load management The error amplifier (E/A) provides the error signal to be compared with the sawtooth to perform the pulse width modulation. Its non-inverting input is internally connected to a 0.8 V voltage reference and its inverting input (FB) and output (COMP) are externally available for feedback and frequency compensation. In this device the error amplifier is a voltage mode operational amplifier, therefore, with high DC gain and low output impedance. The uncompensated error amplifier characteristics are summarized in Table 6. Error amplifier characteristics: Table 6. Error amplifier characteristics Characteristics Value Low frequency gain (A0) 100 dB GBWP 23 MHz Output voltage swing 0 to 3.5 V Source/sink current capability 3.1 mA / 5 mA In continuous conduction working mode (CCM), the transfer function of the power section has two poles due to the LC filter and one zero due to the ESR of the output capacitor. Different kinds of compensation networks can be used depending on the ESR value of the output capacitor. If the zero introduced by the output capacitor helps to compensate the double pole of the LC filter, a type II compensation network can be used. Otherwise, a type III compensation network must be used (see Section 6.4 Compensation network for details on the compensation network design). In case of light load (i.e. if the output current is lower than the half of the inductor current ripple) the A7987 enters pulse-skipping working mode. The HS MOS is kept off if the COMP level is below 200 mV (typ.); when this bottom level is reached the integrated switch is turned on until the inductor current reaches ISKIP value. So, in discontinuous conduction working mode (DCM), the HS MOS on-time is only related to the time necessary to charge the inductor up to ISKIP level. Due to current sensing comparator delay, the actual inductor charge current could be slightly impacted by VIN and inductance level. In order to let the bootstrap capacitor recharge, in case of extremely light load, the A7987 is able to pull down the LX net through an integrated small LS MOS. In this way the bootstrap recharge current can flow from VIN through CBOOT, LX and the LS MOS. This mechanism is activated if the HS MOS has been kept turned off for more than 3 ms (typ.). 5.4 Low VIN operation In normal operation (i.e. VOUT programmed lower than input voltage), when the HS MOS is turned off, a minimum off-time (TOFFMIN) interval is performed. In case the input voltage falls close or below the programmed output voltage (low-dropout, LDO), the A7987 control loop is able to increase the duty cycle up to 100%. However, in order to keep the boot capacitor properly recharged, a maximum HS MOS on-time is limited (TONMAX). When this limit is reached the HS MOS is turned off and a pull-down resistor between LX and GND is turned on until one of the following conditions is met: • A negative current limit (300 mA typ.) is reached • A time-out (1 µs typ.) is reached So the A7987 is able to work in low-dropout operation and recover the programmed output voltage as soon as the proper input voltage level is restored. 5.5 Overcurrent protection The A7987 implements an overcurrent protection by sensing the current flowing through the power MOSFET. Due to the noise created by the switching activity of the power MOSFET, the current sensing circuitry is disabled during the initial phase of the conduction time. This avoids an erroneous detection of a fault condition. This interval is generally known as “masking time” or “blanking time”. The masking time is 120 ns (typ.). DS12928 - Rev 3 page 12/36 A7987 Overcurrent protection If the overcurrent limit is reached, the power MOSFET is turned off implementing pulse-by-pulse overcurrent protection. In the overcurrent condition, the device can skip turn-on pulses in order to keep the inductor current constant and equal to the current limit, assuming only a slight drift due to input and output voltage variation. If, at the end of the “masking time”, the current is higher than the overcurrent threshold, the power MOSFET is turned off and one pulse is skipped. If, at the following switching on, when the “masking time” ends, the current is still higher than the overcurrent threshold, the device skips two pulses. This mechanism is repeated and the device can skip up to seven pulses (refer to Figure 8. OCP and frequency scaling). If at the end of the “masking time” the current is lower than the overcurrent threshold, the number of skipped cycles is decreased by one unit. As a consequence, the overcurrent/short-circuit protection acts by switching off the power MOSFET and reducing the switching frequency down to one-eighth of the default switching frequency, in order to keep constant the output current close to the current limit. Figure 8. OCP and frequency scaling I_LIM I_IND Ton Tmask Up to seven clock pulses can be skipped If the sensed output voltage, monitored through FB pin, falls below the VFOLD threshold (400 mV typ.) the peak current limit threshold is reduced to 1/3 of the nominal value. This additional feature helps to reduce the IC stress in case of output short-circuit. As soon as the FB pin increases above the VFOLD threshold, the full peak current limit threshold is restored. This fold-back protection is disabled during the soft-start. This kind of overcurrent protection is effective if the inductor can be completely discharged during HS MOS turnoff time, so the inductor current does not run away. In case of output short-circuit, the maximum switching frequency can be computed by the following equation: 8 ⋅ VF + RDCR ⋅ ILIM 1 FSW, MAX ≤ ⋅ VIN − RON + RDCR ⋅ ILIM TON, MIN (4) Assuming VF=0.6 V the free-wheeling diode direct voltage, RDCR=30 mΩ the inductor parasitic resistance, ILIM=IPK=1.3 A the peak current limit during fold-back protection, RON=0.24 Ω the HS MOS resistance and TON,MIN=160 ns the minimum HS MOS on duration, the maximum FSW frequency which prevents the inductor current from running away in case of output short-circuit and VIN=61 V is about 530 kHz. If the programmed switching frequency is higher than the above computed limit, an estimation of the inductor current in case of output short-circuit fault is provided by the following equation: FSW ⋅ TON ⋅ VIN − 8 ⋅ VF ILIM ≤ 8 ⋅ RDCR + FSW ⋅ TON, MIN(RON + RDCR) (5) The peak current limit threshold (ILIM) can be programmed in the range of 0.85 A-4 A by selecting the proper RILIM resistor, as suggested below: IPK RILIM = 20kΩ ⋅ ILIM DS12928 - Rev 3 (6) page 13/36 A7987 Overtemperature protection IPK is the default A7987 current limit in case of RILIM is not mounted, as shown in Table 5. Electrical characteristics Figure 9. Current limit and programming resistor 4.500 IPK threshold [A] 4.00 3.500 3.00 2.500 2.00 1.500 1.00 .500 20 30 40 50 60 70 80 90 100 RILIM [kΩ] The minimum programmed current limit cannot be lower than ISKIP=0.5 A (typical), also in case of fold-back detection. 5.6 Overtemperature protection It is recommended that the device should never exceed the maximum allowable junction temperature. This temperature increase is mainly caused by the total power dissipated from the integrated power MOSFET. To avoid any damage to the device when a high temperature is reached, the A7987 implements a thermal shutdown feature: when the junction temperature reaches 170 °C (typ.) the device turns off the power MOSFET and shuts down. When the junction temperature drops to 155 °C (typ.), the device restarts with a new soft-start sequence. DS12928 - Rev 3 page 14/36 A7987 Application information 6 Application information 6.1 Input capacitor selection The input capacitor must be rated for the maximum input operating voltage and the maximum RMS input current. Since the step-down converter input current is a sequence of pulses from 0 A to IOUT, the input capacitor must absorb the equivalent RMS current, which can be up to the load current divided by two (worst case, with duty cycle of 50%). For this reason, the quality of these capacitors must be very high to minimize the power dissipation generated by the internal ESR, thereby improving system reliability and efficiency. The RMS input current (flowing through the input capacitor) is roughly estimated by: ICIN, RMS ≅ IOUT ⋅ D ⋅ 1 − D (7) Actual DC/DC conversion duty cycle, D=VOUT/VIN, is influenced by a few parameters: VOUT + VF DMAX = VIN, MIN − VSW, MAX VOUT + VF DMIN = VIN, MAX − VSW, MIN (8) where VF is the freewheeling diode forward voltage and VSW the voltage drop across the internal high-side MOSFET. Considering the range DMIN to DMAX it is possible to determine the maximum ICIN,RMS flowing through the input capacitor. The input capacitor value must be dimensioned to safely handle the input RMS current and to limit the VIN and VCC ramp-up slew-rate to 0.5 V/µs maximum, in order to avoid the device active ESD protection turn-on. The amount of the input voltage ripple can be roughly overestimated by: VIN, PP = D ⋅ 1 − D ⋅ IOUT + RES, IN ⋅ IOUT CIN ⋅ FSW (9) In case of MLCC ceramic input capacitors, the equivalent series resistance (RES,IN) is negligible. In addition to the input RMS current handling consideration, a ceramic capacitor with appropriate voltage rating and with a value of 1 µF or higher should always be placed between VIN and ground and between VCC and the IC GND pin. This solution is necessary for noise filtering purposes. 6.2 Output capacitor selection The output capacitor is very important in order to satisfy the output voltage ripple requirements. Using a small inductor value is useful to reduce the size of the choke but increases the current ripple. So, to reduce the output voltage ripple, a low ESR capacitor is required. Nevertheless, the ESR of the output capacitor introduces a zero in the open loop gain, which helps to increase the phase margin of the system. If the zero goes to very high frequency, a typical drawback in case of ceramic output capacitor application, a type III compensation network must be designed. The current, in the output capacitor, has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge and discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements. The amount of the voltage ripple can be estimated starting from the current ripple obtained by the inductor selection. Assuming ∆IL the inductor current ripple, the output voltage ripple is roughly overestimated by the equation below: ΔIL ΔVOUT, PP ≅ ΔIL ⋅ RES, OUT + 8 ⋅ FSW ⋅ COUT (10) Usually the resistive component of the ripple is much higher than the capacitive one, if the output capacitor adopted is not a multi-layer ceramic capacitor (MLCC) with a very low ESR value. The output capacitor is also important for loop stability: it fixes the double LC filter pole and the zero due to its ESR. DS12928 - Rev 3 page 15/36 A7987 Inductor selection The output capacitor is the key component that provides the current to the load during a load transient which exceeds the system bandwidth. So, if the high slew rate load transient is required by the application, the output capacitor must be designed in order to sustain the load transient or absorbs the energy stored in the inductor until the converter reacts. In fact, even if the controller detects immediately the load variation and sets the duty cycle at 100% or 0%, the output current slope is limited by the inductor value, the input and output voltage. The output voltage has a drop or overshoot that depends on the ESR and capacitive charge/discharge, as roughly estimated in Eq. (11) L ⋅ ΔIOUT ΔVOUT_LT ≅ ΔIOUT ⋅ RES, OUT + ΔIOUT ⋅ 2 ⋅ COUT ⋅ ΔVL (11) where ∆VL is the voltage applied to the inductor during the load appliance or load release. ΔVL = VIN − VOUT VOUT (12) MLCC capacitors have a typically low ESR to minimize the ripple but also have a low capacitance that does not minimize the voltage deviation during dynamic load variations. Electrolytic capacitors, on the other hand, have a large capacitance which minimizes voltage deviation during load transients whereas they do not show the same ESR values as the MLCCs, resulting then in higher ripple voltages. A mix between an electrolytic and MLCC capacitor can be used to minimize ripple as well as reducing voltage deviation in dynamic mode. The high bandwidth error amplifier of the A7987 and the external compensation feature let design a wide range of output filter configurations (including all MLCC solutions) and perform a fast transient response. 6.3 Inductor selection The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value, in order to have the expected current ripple, must be selected. The rule to fix the current ripple value is to have a ripple at 20%-40% of the output current. In the continuous conduction mode (CCM), the required inductance value can be calculated by the following equation: VOUT VOUT ⋅ 1 − VIN L= ΔIL ⋅ FSW (13) In order to guarantee a maximum current ripple in every condition, Eq. (13) must be evaluated in case of maximum input voltage, assuming VOUT fixed. Increasing the value of the inductance helps reduce the current ripple but, at the same time, strongly impacts the converter response time to a dynamic load change. The response time is the time required by the inductor to change its current from the initial to the final value. Until the inductor has finished its charging (or discharging) time, the output current is supplied (or recovered) by the output capacitors. Further, if the compensation network is properly designed, during a load variation the device is able to properly change the duty cycle so improving the control loop transient response. When this condition is reached the response time is only limited by the time required to change the inductor current, basically by VIN, VOUT and L. Minimizing the response time, at the end, can help to decrease the output filter total cost and to reduce the application area. 6.4 Compensation network The compensation network must assure stability and good dynamic performance. The loop of the A7987 is based on the voltage mode control. The error amplifier is an operational amplifier with a high bandwidth. So, by selecting the compensation network the E/A is considered as ideal, that is, its bandwidth is much larger than the system one. DS12928 - Rev 3 page 16/36 A7987 Compensation network Figure 10. Switching regulator control loop simplified model The transfer function of the PWM modulator, from the error amplifier output (COMP pin) to the LX pin results in an almost constant gain, due to the voltage feed-forward which generates a sawtooth with amplitude VS directly proportional to the input voltage. VIN 1 GPWO = = = 30 VS kFF (14) The synchronization of the device with an external clock provided through the SYNCH pin can modify the PWM modulator gain (see Section 5.1 Oscillator and synchronization to understand how this gain changes and how to keep it constant in spite of the external synchronization). The transfer function of the power section (i.e. the L-C filters and the output load) is: 1 R0 / / RES + sC0 GLC(s) = 1 R0 / / RES + + sL + RDC sC0 = (15) R0 ⋅ 1 + sC0RES s2LC0 ⋅ R0 + RES + s(L + C0R0RDC + C0RESRDC + C0RESR0) + RDC + R0 given L, RDC, C0, RES and R0 the parameters shown in Figure 10. Switching regulator control loop simplified model. The power section transfer function can be rewritten as follows: GLC(s) = GLC0 ⋅ 1+ 2 s s 1+ + 2π ⋅ Q ⋅ fLC 2π ⋅ fLC 1 ;f = fzESR = 2π ⋅ C0RES LC Q= s 2π ⋅ fzESR ; GLC0 = R0 ≅1 R0 + RDC (16) 1 1 ≅ R0 + RES R0 + RES 2π LC0 2π LC0 R0 + RDC R0 LC0 ⋅ R0 + RDC ⋅ R0 + RES ≅ L + C0 ⋅ R0RDC + R0RES + RESRDC LC0 ⋅ R0 ⋅ (R0 + RES) L + C0R0RES (17) (18) with the assumption that the inductor parasitic resistance, RDC, is negligible compared to RO. The closed loop gain is then given by: GLOOP(s) = GLC(s) ⋅ GPWO(s) ⋅ GCOMP(s) DS12928 - Rev 3 (19) page 17/36 A7987 Compensation network As noted in Section 6.2 Output capacitor selection, two different kinds of network can compensate the loop, depending on the value of fzESR, lower or higher than the regulator required bandwidth. In the following two paragraphs the guidelines to select the type II and type III compensation network are illustrated. 6.4.1 Type II compensation network If the equivalent series resistance (RES) of the output capacitor introduces a zero with a frequency lower than the desired bandwidth (that is: 2π∗RES∗CO>1/BW), this zero helps stabilize the loop. Electrolytic capacitors show non-negligible ESR (>30 mΩ typically), so with this kind of output capacitor the type II network combined with the zero of the ESR allows the loop to be stabilized. Figure 11. Type II compensation network The type II compensation network transfer function, from VOUT to COMP, is computed in the equation below: ZF(s) 1 + sCFRF 1 = − GCOMPII(s) = − ⋅ RU RU s ⋅ (CF + CP) ⋅ (1 + sCF / /CPRF = −1⋅ 1+ (20) s 2π ⋅ fZ1 s s ⋅ 1+ 2π ⋅ fP0 2π ⋅ fP1 1 1 1 fZ1 = ;f = ;f = 2π ⋅ CFRF P0 2π ⋅ (CF + CP) ⋅ RU P1 2π ⋅ CF / /CPRF (21) The following suggestions can be followed for a quite common compensation strategy, assuming that CP