ADS6423

ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531 – MAY 2007 QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS FEATURES • • • • Maximum Sample Rate: 125 MSPS 14-Bit Resolution with No Missing Codes Simultaneous Sample and Hold 3.5dB Coarse Gain and up to 6dB Programmable Fine Gain for SFDR/SNR Trade-Off Serialized LVDS Outputs with Programmable Internal Termination Option Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude down to 400 mVPP Internal Reference with External Reference Support No External Decoupling Required for References 3.3-V Analog and Digital Supply • • • 64 QFN Package (9 mm × 9 mm) Pin Compatible 12-Bit Family (ADS642X SLAS532) Feature Compatible Dual Channel Family (ADS624X - SLAS542, ADS644X - SLAS543) APPLICATIONS • • • • Base-Station IF Receivers Diversity Receivers Medical Imaging Test Equipment Table 1. ADS64XX Quad Channel Family 125 MSPS ADS644X 14 Bit ADS642X 12 Bit ADS6445 ADS6425 105 MSPS ADS6444 ADS6424 80 MSPS ADS6443 ADS6423 65 MSPS ADS6442 ADS6422 • • • • • Table 2. Performance Summary ADS6445 SFDR, dBc SINAD, dBFS Fin = 10MHz (0 dB gain) Fin = 170MHz (3.5 dB gain) Fin = 10MHz (0 dB gain) Fin = 170MHz (3.5 dB gain) 87 79 73.4 68.3 420 ADS6444 91 83 73.4 69.3 340 ADS6443 92 84 74.2 69.4 300 ADS6442 93 84 74.3 70 265 Power, per channel, mW DESCRIPTION The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of high performance 14-bit 125/105/80/65 MSPS quad channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB. The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling frequencies. An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver. The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The ADS644X has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (–40°C to 85°C). AVDD AGND LVDD LGND CAP BIT Clock CLKP CLKM DCLKP DCLKM PLL FRAME Clock FCLKP FCLKM DA0_P DA0_M DA1_P DA1_M DB0_P DB0_M DB1_P DB1_M DC0_P DC0_M DC1_P DC1_M DD0_P DD0_M DD1_P DD1_M INA_P SHA INA_M 14-Bit ADC Digital Encoder and Serializer INB_P SHA INB_M 14-Bit ADC Digital Encoder and Serializer INC_P SHA INC_M 14-Bit ADC Digital Encoder and Serializer IND_P SHA IND_M 14-Bit ADC Digital Encoder and Serializer VCM ADS644x Reference REFM REFP Parallel Interface Serial Interface CFG1 PDN CFG2 CFG3 CFG4 SEN RESET SDATA SCLK B0199-03 2 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR RGC RGC RGC RGC SPECIFIED TEMPERATURE RANGE –40°C to 85°C –40°C to 85°C –40°C to 85°C –40°C to 85°C PACKAGE MARKING AZ6445 AZ6444 AZ6443 AZ6442 (1) ORDERING NUMBER ADS6445IRGCT ADS6445IRGCR ADS6444IRGCT ADS6444IRGCR ADS6443IRGCT ADS6443IRGCR ADS6442IRGCT ADS6442IRGCR TRANSPORT MEDIA, QUANTITY 250, Tape/reel 2000, Tape/reel 250, Tape/reel 2000, Tape/reel 250, Tape/reel 2000, Tape/reel 250, Tape/reel 2000, Tape/reel ADS6445 ADS6444 ADS6443 ADS6442 (1) (2) QFN-64 (2) QFN-64 (2) QFN-64 (2) QFN-64 (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 23.17 °C/W (0 LFM air flow), θJC = 22.1 °C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in. x 3 in. PCB. ABSOLUTE MAXIMUM RATINGS (1) VALUE AVDD LVDD Supply voltage range Supply voltage range Voltage between AGND and DGND Voltage between AVDD to LVDD Voltage applied to external pin, VCM Voltage applied to analog input pins TA TJ Tstg Operating free-air temperature range Operating junction temperature range Storage temperature range Lead temperature 1,6 mm (1/16") from the case for 10 seconds (1) –0.3 to 3.9 –0.3 to 3.9 –0.3 to 0.3 –0.3 to 3.3 –0.3 to 2.0 – 0.3V to minimum ( 3.6, AVDD + 0.3V) –40 to 85 125 –65 to 150 220 UNIT V V V V V V °C °C °C °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback 3 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN SUPPLIES AVDD LVDD Analog supply voltage LVDS Buffer supply voltage Differential input voltage range Input common-mode voltage Voltage applied on VCM in external reference mode CLOCK INPUT ADS6445 Input clock sample rate, Fsrated ADS6444 ADS6443 ADS6442 Sine wave, ac-coupled Input clock amplitude differential (VCLKP– VCLKM) LVPECL, ac-coupled LVDS, ac-coupled LVCMOS, ac-coupled Input Clock duty cycle DIGITAL OUTPUTS CLOAD RLOAD TA Maximum external load capacitance from each output pin to DGND Without internal termination With internal termination –40 5 10 100 85 pF Ω °C 35% 5 5 5 5 0.4 1.5 ± 0.8 ± 0.35 3.3 50% 65% Vpp 125 105 80 65 MSPS 1.45 3.0 3.0 3.3 3.3 2 1.5 ±0.1 1.50 1.55 3.6 3.6 V V Vpp V V NOM MAX UNIT ANALOG INPUTS Differential load resistance (external) between the LVDS output pairs Operating free-air temperature 4 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 ELECTRICAL CHARACTERISTICS Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted). PARAMETER RESOLUTION ANALOG INPUT Differential input voltage range Differential input capacitance Analog input bandwidth ADS6445 Analog input common mode current (per input pin of each ADC) ADS6444 ADS6443 ADS6442 REFERENCE VOLTAGES VREFB VREFT ∆VREF VCM Internal reference bottom voltage Internal reference top voltage Internal reference error (VREFT–VREFB) Common mode output voltage VCM output current capability DC ACCURACY No missing codes EO Offset error, across devices and across channels within a device Offset error temperature coefficient, across devices and across channels within a device There are two sources of gain error - internal reference inaccuracy and channel gain error EGREF EGCHAN Gain error due to internal reference inaccuracy alone, (∆VREF /2.0) % Reference gain error temperature coefficient Gain error of channel alone, across devices and across channels within a device (1) Channel gain error temperature coefficient, across devices and across channels within a device DNL INL PSRR Differential nonlinearity, Fin = 50 MHz Integral nonlinearity, Fin = 50 MHz DC power supply rejection ratio ADS6445 ICC Total supply current ADS6444 ADS6443 ADS6442 ADS6445 IAVDD Analog supply current ADS6444 ADS6443 ADS6442 ADS6445 ILVDD LVDS supply current ADS6444 ADS6443 ADS6442 (1) This is specified by design anad characterization; it is not tested in production. Submit Documentation Feedback 5 ADS6445 and ADS6444 ADS6443 and ADS6442 ADS6445 and ADS6444 ADS6443 and ADS6442 –0.9 –0.9 -5 4.5 –1 -0.75 0.1 0.0125 ±0.3 0.005 ±0.6 ±0.5 ±3 ±2 0.5 502 410 360 320 410 322 280 245 92 88 80 75 mA mA mA 2.0 1.8 5 4.5 1 0.75 % FS ∆%/°C % FS ∆%/°C LSB LSB mV/V –15 Assured ±2 0.05 15 mV mV/°C -15 1.0 2.0 ±2 1.5 ±4 15 V V mV V mA 2.0 7 500 155 130 100 81 µA VPP pF MHz MIN TYP 14 MAX UNIT Bits POWER SUPPLY ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com ELECTRICAL CHARACTERISTICS Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted). PARAMETER POWER SUPPLY (Continued) ADS6445 Total power ADS6444 ADS6443 ADS6442 Power down (with input clock stopped) DYNAMIC AC CHARACTERISTICS ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 SNR Signal to noise ratio ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 and ADS6443 ADS6442 3.5 dB Coarse gain Fin = 230 MHz 0 dB gain Fin = 170 MHz 3.5 dB Coarse gain 0 dB gain Fin = 100 MHz Fin = 70 MHz 69 Fin = 50 MHz 68.5 70 70.5 Fin = 10 MHz 73.7 73.8 74.4 74.5 73.1 73.2 73.8 74 72.7 73 73.4 73.6 72.1 72.2 72.7 72.8 69.9 70.2 70.5 70.7 69.4 69.7 69.7 70.2 68.7 68.8 68.1 69.2 68.1 68.2 68.9 dBFS 1.65 1.35 1.18 1.05 77 1.8 1.5 1.3 1.2 150 mW W TEST CONDITIONS MIN TYP MAX UNIT 6 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted). PARAMETER ADS6445 and ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 SINAD Signal to noise and distortion ratio ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 RMS Output noise Inputs tied to common-mode Fin = 230 MHz 3.5 dB Coarse gain 0 dB gain Fin = 170 MHz 3.5 dB Coarse gain 0 dB gain Fin = 100 MHz Fin = 70 MHz 68.5 Fin = 50 MHz 68 69.5 70 Fin = 10 MHz TEST CONDITIONS MIN TYP MAX 73.4 74.2 74.3 72.3 71.7 73.5 73.7 71.2 72 73 73.2 71.8 72 72.2 72 67.9 69.8 69.9 70.3 68.3 69.3 69.4 70 67.8 67.7 67.6 68.3 67.9 67.6 68.1 68.4 1.05 LSB dBFS UNIT Submit Documentation Feedback 7 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted). PARAMETER ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 and ADS6442 ADS6445 ADS6444 SFDR Spurious free dynamic range ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 and ADS6442 ADS6445 and ADS6444 ADS6443 ADS6442 ADS6445 and ADS6444 ADS6443 and ADS6442 Fin = 230 MHz 3.5 dB Coarse gain 0 dB gain 3.5 dB Coarse gain Fin = 170 MHz 0 dB gain Fin = 100 MHz Fin = 70 MHz 74 Fin = 50 MHz 73 77 79 Fin = 10 MHz TEST CONDITIONS MIN TYP MAX 87 91 92 93 81 80 87 88 78 81 86 86 88 84 82 76 79 80 81 79 83 84 77 78 79 80 82 dBc UNIT 8 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted). PARAMETER ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 HD2 Second harmonic ADS6443 and ADS6442 ADS6445 ADS6444 ADS6443 and ADS6442 ADS6445 ADS6444 ADS6443 and ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 Fin = 230 MHz 3.5 dB Coarse gain 0 dB gain Fin = 170 MHz 3.5 dB Coarse gain 0 dB gain Fin = 100 MHz Fin = 70 MHz 74 Fin = 50 MHz 73 77 79 Fin = 10 MHz TEST CONDITIONS MIN TYP MAX 93 94 96 97 87 88 90 92 87 88 90 92 89 90 87 83 84 86 85 86 88 80 81 82 83 82 83 84 85 dBc UNIT Submit Documentation Feedback 9 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted). PARAMETER ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 and ADS6442 ADS6445 ADS6444 HD3 Third harmonic ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 and ADS6442 ADS6445 and ADS6444 ADS6443 ADS6442 ADS6445 and ADS6444 ADS6443 and ADS6442 ADS6445 and ADS6444 ADS6443 ADS6442 ADS6445 and ADS6444 ADS6443 Worst harmonic (other than HD2, HD3) ADS6442 ADS6445 ADS6444 ADS6443 and ADS6442 ADS6445 and ADS6444 ADS6443 and ADS6442 All Fin = 170 MHz Fin = 230 MHz Fin = 100 MHz Fin = 50 MHz Fin = 10 MHz Fin = 230 MHz 3.5 dB Coarse gain 0 dB gain 3.5 dB Coarse gain Fin = 170 MHz 0 dB gain Fin = 100 MHz Fin = 70 MHz 74 Fin = 50 MHz 73 77 79 Fin = 10 MHz TEST CONDITIONS MIN TYP MAX 87 91 92 93 81 80 87.5 88 78 81 86 86 88 84 82 76 79 80 81 79 83 84 77 78 79 80 82 91 94 95 87 92 93 90 91 92 88 90 87 dBc dBc UNIT 10 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted). PARAMETER ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 THD Total harmonic distortion ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ENOB Effective number of bits ADS6443 ADS6442 ADS6444 ADS6445 ADS6444 ADS6443 IMD 2-tone intermodulation distortion ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 ADS6445 ADS6444 ADS6443 Cross-talk ADS6442 ADS6445 ADS6444 ADS6443 ADS6442 Input overload recovery AC PSRR Power Supply Rejection Ratio All All Recovery to within 1% (of final value) for 6 dB overload with sine wave input < 100 MHz signal, 100 mV pp on AVDD supply Far channel Cross-talk signal frequency = 10 MHz Near channel Cross-talk signal frequency = 10 MHz F1= 185.09 MHz, F2 = 190.09 MHz F1= 46.09 MHz, F2 = 50.09 MHz Fin = 70 MHz Fin = 50 MHz 11.0 11.1 11.4 11.3 Fin = 230 MHz Fin = 170 MHz Fin = 100 MHz 72 Fin = 50 MHz 71 75 77 Fin = 10 MHz TEST CONDITIONS MIN TYP MAX 86 89.5 90 91 80 78.5 85.5 85.6 84.5 86 83 80.5 73.5 77 78.5 79.5 74 75 76 77 11.7 11.9 12 11.7 88 90 96 100 86 88 93 96 90 92 94 100 103 105 106 108 1 35 Clock cycles dBc dBc dBFS Bits dBc UNIT Submit Documentation Feedback 11 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com DIGITAL CHARACTERISTICS The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1 AVDD = LVDD = 3.3V, IO = 3.5mA, RLOAD = 100Ω (1). All LVDS specifications are characterized, but not tested at production. PARAMETER DIGITAL INPUTS High-level input voltage Low-level input voltage High-level input current Low-level input current Input capacitance DIGITAL OUTPUTS High-level output voltage Low-level output voltage Output differential voltage |VOD| Output offset voltage VOS Output capacitance (1) Common-mode voltage of OUTP and OUTM Output capacitance inside the device, from either output to ground 250 1375 1025 350 1200 2 450 mV mV mV mV pF 10 10 4 2.4 0.8 V V µA µA pF TEST CONDITIONS MIN TYP MAX UNIT IO refers to the LVDS buffer current setting, RLOAD is the external differential load resistance between the LVDS output pair. 12 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 (1) TIMING SPECIFICATIONS Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted. PARAMETER tJ Aperture jitter All TEST CONDITIONS Uncertainty in the sampling instant MIN TYP 250 MAX UNIT fs rms INTERFACE: 2-wire, DDR bit clock, 14x serialization ADS6445 tsu Data setup time (4) (5) (6) ADS6444 ADS6443 ADS6442 ADS6445 th Data hold time (4) (5) (6) ADS6444 ADS6443 ADS6442 tpd_clk Clock propagation delay Bit clock cycle-cycle jitter (6) (5) (5) 0.35 From data cross-over to bit clock cross-over 0.45 0.65 0.8 0.35 From bit clock cross-over to data cross-over 0.5 0.7 0.8 Input clock rising edge cross-over to frame clock rising edge cross-over 3.4 0.55 0.65 0.85 1.1 0.58 0.7 0.9 1.1 4.4 350 75 5.4 ns ps pp ps pp ns ns All All All Frame clock cycle-cycle jitter Below specifications apply for 5 MSPS ≤ Fs ≤ 125 MSPS and all interface options. tA Aperture delay Aperture delay variation ADC Latency (7) All All All Delay from input clock rising edge to the actual sampling instant Channel-channel within same device Time for a sample to propagate to ADC outputs, see Figure 1 Time to valid data after coming out of global power down 1 –250 2 ±80 12 3 250 ns ps Clock cycles 100 100 200 50 50 50 50 45% 47% 100 100 100 100 50% 50% 200 200 200 200 55% 53% µs µs Clock cycles ps ps ps ps Wake up time All Time to valid data after input clock is re-started Time to valid data after coming out of channel standby tRISE tFALL tRISE tFALL Data rise time Data fall time Bit clock and frame clock rise time Bit clock and frame clock fall time LVDS Bit clock duty cycle LVDS Frame clock duty cycle All All All All All All From –100 mV to +100 mV From +100 mV to –100 mV From –100mV to +100mV From +100mV to –100mV (1) (2) (3) (4) (5) (6) (7) Timing parameters are ensured by design and characterization and not tested in production. CL is the external single-ended load capacitance between each output pin and ground. Io refers to the LVDS buffer current setting; RL is the external differential load resistance between the LVDS output pair. Timing parameters are measured at the end of a 2 inch pcb trace (100-Ω characteristic impedance) terminated by RLand CL. Setup and hold time specifications take into account the effect of jitter on the output data and clock. Refer to Output Timings in application section for timings at lower sampling frequencies and other interface options. Note that the total latency = ADC latency + internal serializer latency. The serializer latency depends on the interface option selected as shown in Table 27. Submit Documentation Feedback 13 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com Sample N+11 Sample N Input Signal tA Sample N+12 Sample N+13 Input Clock CLKM CLKP Latency 12 Clocks tPD_CLK Bit Clock DCLKP DCLKM Output Data DOP D13 D12 D11 D10 D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10 D6 D5 D4 D3 D2 D1 D0 DOM Sample N–1 Sample N Frame Clock FCLKM FCLKP T0105-04 Figure 1. Latency DCLKP Bit Clock DCLKM th tsu Output Data DOP, DOM tsu th Dn+1 Dn T0106-03 Figure 2. LVDS Timings 14 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 DEVICE PROGRAMMING MODES ADS644X offers flexibility with several programmable features that are easily configured. The device can be configured independently using either parallel interface control or serial interface programming. In addition, the device supports a third configuration mode, where both the parallel interface and the serial control registers are used. In this mode, the priority between the parallel and serial interfaces is determined by a priority table (refer to Table 4). If this additional level of flexibility is not required, the user can select either the serial interface programming or the parallel interface control. USING PARALLEL INTERFACE CONTROL ONLY To control the device using parallel interface, keep RESET tied to high (LVDD). Pins CFG1, CFG2, CFG3, CFG4, PDN, SEN, SCLK, and SDATA are used to directly control certain functions of the ADC. After power-up, the device will automatically get configured as per the parallel pin voltage settings (refer to Table 5 to Table 8) and no reset is required. In this mode, SEN, SCLK, and SDATA function as parallel interface control pins. Frequently used functions are controlled in this mode—output data interface and format, power down modes, coarse gain and internal/external reference. The parallel pins can be configured using a simple resistor string as illustrated in Figure 3. Table 3 has a description of the modes controlled by the parallel pins. Table 3. Parallel Pin Definition PIN SEN SCLK, SDATA PDN CFG1 CFG2 CFG3 CFG4 CONTROL FUNCTIONS Coarse gain and internal/external reference. Sync, deskew patterns and global power down. Dedicated pin for global power down 1-Wire/2-wire and DDR/SDR bit clock 14x/16x Serialization and SDR bit clock capture edge Reserved function. Tie CFG3 to Ground. MSB/LSB First and data format. USING SERIAL INTERFACE PROGRAMMING ONLY In this mode, SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC. The registers must first be reset to their default values either by applying a pulse on RESET pin or by a high setting on the bit (in register ). After reset, the RESET pin must be kept low. The serial interface section describes the register programming and register reset in more detail. Since the parallel pins (CFG1-4 and PDN) are not used in this mode, they must be tied to ground. The register override bit - D10 in register 0x0D has to be set high to disable the control of parallel interface pins in this serial interface control ONLY mode. USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS For increased flexibility, a combination of serial interface registers and parallel pin controls (CFG1-4 and PDN) can also be used to configure the device. The parallel interface control pins CFG1 to CFG4 and PDN are available. After power-up, the device will automatically get configured as per the parallel pin voltage settings (refer to Table 5 to Table 11) and no reset is required. A simple resistor string can be used as illustrated in Figure 3. SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC. The registers must first be reset to their default values either by applying a pulse on RESET pin or by a high setting on the bit (in register ). After reset, the RESET pin must be kept low. The Serial Interface section describes the register programming and register reset in more detail. Submit Documentation Feedback 15 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com Since some functions are controlled using both the parallel pins and serial registers, the priority between the two is determined by a priority table (refer to Table 4). Table 4. Priority Between Parallel Pins and Serial Registers PIN CFG1 to CFG4 PDN FUNCTIONS SUPPORTED As described in Table 8 to Table 11 Global Power Down PRIORITY Register bits can control the modes only if the register bit is high. If bit is low, then the control voltage on these parallel pins determines the function. Register bit controls global power down only if PDN pin is low. If PDN is high, device is in global power down. Coarse gain is controlled by register bit only if the bit is high. Else, device has 0 dB coarse gain. Internal/External Reference setting is determined by register bit . SCLK, SDATA Serial Interface Clock and Serial Interface Data pins Register bits control the sync and deskew output patterns. Power down is determined by bit SEN Serial Interface Enable AVDD 3R (5/8) AVDD (5/8) AVDD 2R (3/8) AVDD GND AVDD (3/8) AVDD 3R To Parallel Pin GND Figure 3. Simple Scheme to Configure Parallel Pins 16 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 DESCRIPTION OF PARALLEL PINS Table 5. SCLK, SDATA Control Pins SCLK LOW LOW HIGH HIGH SDATA LOW HIGH LOW HIGH NORMAL conversion. SYNC – ADC outputs sync pattern on all channels. This pattern can be used by the receiver to align the deserialized data to the frame boundary. See Capture Test Patterns for details. POWER DOWN – Global power down, all channels of the ADC are powered down, including internal references, PLL and output buffers. DESKEW – ADC outputs deskew pattern on all channels. This pattern can be used by the receiver to ensure deserializer uses the right clock edge. See Capture Test Patterns for details. DESCRIPTION Table 6. SEN Control Pin SEN 0 (3/8)LVDD (5/8)LVDD LVDD DESCRIPTION External reference and 0 dB coarse gain (full-scale = 2 VPP) External reference and 3.5 dB coarse gain (full-scale = 1.34 VPP) Internal reference and 3.5 dB coarse gain (full-scale = 1.34 VPP) Internal reference and 0 dB coarse gain (full-scale = 2 VPP) Independent of the programming mode used, after power-up the parallel pins PDN, CFG1 to CFG4 will automatically configure the device as per the voltage applied (refer to Table 7 to Table 11). Table 7. PDN Control Pin PDN 0 AVDD Normal operation Power down global DESCRIPTION Table 8. CFG1 Control Pin CFG1 0 (3/8)LVDD (5/8)LVDD LVDD DDR Bit clock and 1-wire interface Not used SDR Bit clock and 2-wire interface DDR Bit clock and 2-wire interface DESCRIPTION Table 9. CFG2 Control Pin CFG2 0 (3/8)LVDD (5/8)LVDD LVDD DESCRIPTION 14x Serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock mode) 16x Serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock mode) 16x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode) 14x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode) Table 10. CFG3 Control Pin CFG3 RESERVED - TIE TO GROUND Table 11. CFG4 Control Pin CFG4 0 (3/8)LVDD (5/8)LVDD LVDD MSB First and 2s complement MSB First and offset binary LSB First and offset binary LSB First and 2s complement DESCRIPTION Submit Documentation Feedback 17 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com SERIAL INTERFACE The ADC has a serial interface formed by pins SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data) and RESET. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiple of 16-bit words within a single active SEN pulse. The interface can work with SCLK frequency from 20 MHz down to very low speeds (few hertz) and even with non-50% duty cycle SCLK. The first 5-bits of the 16-bit word are the address of the register while the next 11 bits are the register data. Register Reset After power-up, the internal registers must be reset to their default values. This can be done in one of two ways: 1. Either by applying a high-going pulse on RESET (of width greater than 10ns) OR 2. By applying software reset. Using the serial interface, set the bit in register 0x00 to high– this resets the registers to their default values and then self-resets the bit to LOW. When RESET pin is not used, it must be tied to LOW. Register Address Register Data SDATA A4 A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 t(DH) D1 D0 t(SCLK) t(DSU) SCLK t(SLOADS) t(SLOADH) SEN RESET T0109-03 Figure 4. Serial Interface Timing 18 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 SERIAL INTERFACE TIMING CHARACTERISTICS Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, unless otherwise noted. PARAMETER fSCLK tSLOADS tSLOADH tDSU tDH SCLK Frequency, fSCLK = 1/tSCLK SEN to SCLK Setup time SCLK to SEN Hold time SDATA Setup time SDATA Hold time Time taken for register write to take effect after 16th SCLK falling edge MIN > DC 25 25 25 25 100 TYP MAX 20 UNIT MHz ns ns ns ns ns RESET TIMING Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, unless otherwise noted. PARMATER t1 t2 t3 tPO Power-on delay time Reset pulse width Power-up delay time CONDITIONS Delay from power-up of AVDD and LVDD to RESET pulse active Pulse width of active RESET signal Delay from power-up of AVDD and LVDD to output stable MIN 5 10 25 6.5 TYP MAX UNIT ms ns ns ms Register write delay time Delay from RESET disable to SEN active Power Supply AVDD, LVDD t1 RESET t2 t3 SEN T0108-03 Figure 5. Reset Timing Submit Documentation Feedback 19 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com SERIAL REGISTER MAP Table 12. Summary of Functions Supported By Serial Interface REGISTER ADDRESS A4 - A0 D10 D9 D8 D7 REGISTER FUNCTIONS (1) (2) D6 D5 INTERNAL OR EXTERNAL D4 POWER DOWN CH D D3 POWER DOWN CHC D2 POWER DOWN CH B D1 POWER DOWN CH A D0 GLOBAL POWER DOWN 0 00 S/W RESET 0 0 0 0 04 0 0 DATA FORMAT 2S COMP OR STRAIGHT BINARY 0 0 INPUT CLOCK BUFFER GAIN CONTROL 0 0A 0 0 TEST PATTERNS 0 0 0 0 0 0B 0C FINE GAIN CONTROL (1dB to 6 dB) OVERRIDE BIT 0 CUSTOM PATTERN (LOWER 11 BITS) 0 0 COURSE GAIN ENABLE 0 FALLING OR RISING BIT CLOCK CAPTURE EDGE 0 CUSTOM PATTERN (UPPER 3 BITS) 14-BIT OR 16-BIT SERIALIZE DDR OR SDR BIT CLOCK 1-WIRE OR 2-WIRE INTERFACE 0D 0 0 BYTE-WISE OR BIT-WISE MSB OR LSB FIRST 0 10 11 LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS WORD-WISE CONTROL 0 0 0 0 LVDS CURRENT SETTINGS LVDS CURRENT DOUBLE LVDS INTERNAL TERMINATION - DATA OUTPUTS (1) (2) The unused bits in each register (shown by blank cells in above table) must be programmed as 0. Multiple functions in a register can be programmed in a single write operation. 20 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 DESCRIPTION OF SERIAL REGISTERS Table 13. Serial Register A REGISTER ADDRESS A4 - A0 D10 S/W RESET D9 D8 D7 D6 BITS D5 INTERNAL OR EXTERNAL D4 POWER DOWN CH D D3 POWER DOWN CHC D2 POWER DOWN CH B D1 POWER DOWN CH A D0 GLOBAL POWER DOWN 00 0 0 0 0 D0 - D4 D0 0 1 D1 0 1 D2 0 1 D3 0 1 D4 0 1 D5 0 1 D10 1 Power down modes Normal operation Global power down, including all channels ADCs, internal references, internal PLL and output buffers CH A Powered up CH A ADC Powered down CH B Powered up CH B ADC Powered down CH C Powered up CH C ADC Powered down CH D Powered up CH D ADC Powered down Reference Internal reference enabled External reference enabled Software reset applied – resets all internal registers and self-clears to 0 Submit Documentation Feedback 21 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com Table 14. Serial Register B REGISTER ADDRESS A4 - A0 04 D10 0 D9 0 D8 0 D7 0 D6 BITS D5 D4 D3 D2 D1 0 D0 0 INPUT CLOCK BUFFER GAIN CONTROL D6 - D2 11000 00000 01100 01010 01001 01000 Input clock buffer gain control Gain 0, minimum gain Gain 1, default gain after reset Gain 2 Gain 3 Gain 4 Gain 5, maximum gain Table 15. Serial Register C REGISTER ADDRESS A4 - A0 D10 D9 DATA DORMAT 2S COMP OR STRAIGHT BINARY D8 D7 D6 BITS D5 D4 D3 D2 D1 D0 00 0 0 TEST PATTERNS 0 0 0 0 0 D7 - D5 000 001 010 011 100 101 110 111 D9 0 1 Capture test patterns Normal ADC operation Output all zeros Output all ones Output toggle pattern Unused Output custom pattern (contents of CUSTOM pattern registers 0x0B and 0x0C) Output DESKEW pattern (serial stream of 1010..) Output SYNC pattern Data format selection 2s Complement format Straight binary format 22 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 Table 16. Serial Register D REGISTER ADDRESS A4 - A0 0B D10 D9 D8 D7 D6 BITS D5 D4 D3 D2 D1 D0 CUSTOM PATTERN (LOWER 11 BITS) D10 - D0 Lower 11 bits of custom pattern … Table 17. Serial Register E REGISTER ADDRESS A4 - A0 0C D10 D9 D8 D7 0 D6 0 BITS D5 0 D4 0 D3 0 D2 D1 D0 FINE GAIN CONTROL (1 dB to 6 dB) CUSTOM PATTERN (UPPER 3 BITS) D4 - D0 D10-D8 000 001 010 011 100 101 110 Upper 3 bits of custom pattern … Fine gain control 0 dB Gain (full-scale range = 2.00 VPP) 1 dB Gain (full-scale range = 1.78 VPP) 2 dB Gain (full-scale range = 1.59 VPP) 3 dB Gain (full-scale range = 1.42 VPP) 4 dB Gain (full-scale range = 1.26 VPP) 5 dB Gain (full-scale range = 1.12 VPP) 6 dB Gain (full-scale range = 1.00 VPP) Table 18. Serial Register F REGISTER ADDRESS A4 - A0 D10 OVER-RIDE BITE D9 D8 D7 BYTE-WISE OR BIT-WISE D6 BITS D5 COURSE GAIN ENABLE D4 FALLING OR RISING BIT CLOCK CAPTURE EDGE D3 D2 14-BIT OR 16-BIT SERIALIZE D1 DDR OR SDR BIT CLOCK D0 1-WIRE OR 2-WIRE INTERFACE 0D 0 0 MSB OR LSB FIRST 0 D0 0 1 D1 0 1 D2 0 1 D4 0 1 Interface selection 1 Wire interface 2 Wire interface Bit clock selection (only in 2-wire interface) DDR Bit clock SDR Bit clock Serialization factor selection 14X Serialization 16X Serialization Bit clock capture edge (only when SDR bit clock is selected, D1 = 1) Capture data with falling edge of bit clock Capture data with rising edge of bit clock Submit Documentation Feedback 23 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com D5 0 1 D6 0 1 D7 0 1 D10 Coarse gain control 0 dB Coarse gain (full-scale range = 2.0 VPP) 3.5dB Coarse gain (full-scale range = 1.34 VPP) MSB or LSB First selection MSB First LSB First Byte/bit wise outputs (only when 2-wire is selected) Byte wise Bit wise Over-ride bit. All the functions in register 0x0D can also be controlled using the parallel control pins. By setting bit = 1, the contents of register 0x0D will over-ride the settings of the parallel pins. Disable over-ride Enable over-ride Table 19. Serial Register G 0 1 REGISTER ADDRESS A4 - A0 10 D10 D9 D8 D7 D6 BITS D5 D4 D3 D2 D1 D0 LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS LVDS CURRENT SETTINGS LVDS CURRENT DOUBLE D0 0 1 D1 0 1 D3-D2 00 01 10 11 D5-D4 00 01 10 11 D10-D6 00000 00001 LVDS current double for data outputs Nominal LVDS current, as set by Double the nominal value LVDS current double for bit and word clock outputs Nominal LVDS current, as set by Double the nominal value LVDS current setting for data outputs 3.5 mA 4 mA 2.5 mA 3 mA LVDS current setting for bit and word clock outputs 3.5 mA 4 mA 2.5 mA 3 mA LVDS internal termination for bit and word clock outputs No internal termination 166 Ω 24 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 00010 00100 01000 10000 200 Ω 250 Ω 333 Ω 500 Ω Any combination of above bits can also be programmed, resulting in a parallel combination of the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω 00101 100 Ω Table 20. Serial Register H REGISTER ADDRESS A4 - A0 11 D10 D9 D8 0 D7 0 D6 0 BITS D5 0 D4 D3 D2 D1 D0 WORD-WISE CONTROL LVDS INTERNAL TERMINATION - DATA OUTPUTS D4-D0 00000 00001 00010 00100 01000 10000 LVDS internal termination for data outputs No internal termination 166 Ω 200 Ω 250 Ω 333 Ω 500 Ω Any combination of above bits can also be programmed, resulting in a parallel combination of the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω 00101 D10-D9 00 11 01,10 100 Ω Only when 2-wire interface is selected Byte-wise or bit-wise output, 1x frame clock Word-wise output enabled, 0.5x frame clock Do not use Submit Documentation Feedback 25 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com PIN CONFIGURATION (2-WIRE INTERFACE) ADS644x RGC PACKAGE (TOP VIEW) DCLKM FCLKM DC0_M DC1_M DB0_M DB1_M DCLKP FCLKP DC0_P DC1_P DB0_P DB1_P LGND LGND LVDD DA1_P DA1_M DA0_P DA0_M CAP RESET LVDD AGND AVDD AGND INA_M INA_P AGND INB_M INB_P AGND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 2 3 4 5 6 7 8 47 46 45 44 43 42 41 LVDD DD0_M DD0_P DD1_M DD1_P SCLK SDATA SEN PDN AVDD AGND IND_M IND_P AGND INC_M INC_P AGND PAD 9 10 11 12 13 14 15 40 39 38 37 36 35 34 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CFG4 CFG3 CFG2 CFG1 VCM AGND AGND AGND AGND CLKP AVDD AVDD CLKM AVDD AVDD NC P0056-04 PIN ASSIGNMENTS (2-WIRE INTERFACE) PINS NAME NO. 9,17,19,27,3 2,40 8,10,13,16,1 8, 23, 26,31,33,36, 39 7,49,64 54,59 24,25 I SUPPLY AND GROUND PINS AVDD 6 Analog power supply I/O NO. OF PINS DESCRIPTION AGND LVDD LGND INPUT PINS CLKP, CLKM 26 11 3 2 2 Analog ground Digital power supply Digital ground Differential input clock pair Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 PIN ASSIGNMENTS (2-WIRE INTERFACE) (continued) PINS NAME INA_P, INA_M INB_P, INB_M INC_P, INC_M IND_P, IND_M CAP SCLK NO. 12,11 15,14 34,35 37,38 5 44 I I/O I I I I NO. OF PINS 2 2 2 2 1 1 DESCRIPTION Differential input signal pair, channel A. If unused, the pins should be tied to VCM. Do not float. Differential input signal pair, channel B. If unused, the pins should be tied to VCM. Do not float. Differential input signal pair, channel C If unused, the pins should be tied to VCM. Do not float. Differential input signal pair, channel D. If unused, the pins should be tied to VCM. Do not float. Connect 2-nF capacitor from pin to ground This pin functions as serial interface clock input when RESET is low. When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along with SDATA). Refer to Table 5 for description. This pin has an internal pull-down resistor. This pin functions as serial interface data input when RESET is low. When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along with SCLK). Refer to Table 5 for description. This pin has an internal pull-down resistor. This pin functions as serial interface enable input when RESET is low. When RESET is high, it controls coarse gain and internal/external reference modes. Refer to Table 6 for description. This pin has an internal pull-up resistor. Serial interface reset input. When using the serial interface mode, the user MUST initialize internal registers through hardware RESET by applying a high-going pulse on this pin or by using software reset option. Refer to the Serial Interface section. In parallel interface mode, tie RESET permanently high. (SCLK, SDATA and SEN function as parallel control pins in this mode). The pin has an internal pull-down resistor to ground. PDN CFG1 41 30 I I 1 1 Global power down control pin. Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock selection. Refer to Table 8 for description. Tie to AVDD for 2-wire interface with DDR bit clock. Parallel input pin. It controls 14x or 16x serialization and SDR bit clock capture edge. Refer to Table 9 for description. For 14x serialization with DDR bit clock, tie to ground or AVDD. RESERVED pin - Tie to ground. Parallel input pin. It controls data format and MSB or LSB first modes. Refer to Table 11 for description. Internal reference mode – common-mode voltage output External reference mode – reference input. The voltage forced on this pin sets the internal reference. Channel A differential LVDS data output pair, wire 0 Channel A differential LVDS data output pair, wire 1 Channel B differential LVDS data output pair, wire 0 Channel B differential LVDS data output pair, wire 1 Channel C differential LVDS data output pair, wire 0 Channel C differential LVDS data output pair, wire 1 Channel D differential LVDS data output pair, wire 0 Channel D differential LVDS data output pair, wire 1 Differential bit clock output pair Differential frame clock output pair Do Not Connect SDATA 43 I 1 SEN 42 I 1 RESET 6 I 1 CFG2 CFG3 CFG4 VCM OUTPUT PINS DA0_P,DA0_M DA1_P,DA1_M DB0_P,DB0_M DB1_P,DB1_M DC0_P,DC0_M DC1_P,DC1_M DD0_P,DD0_M DD1_P,DD1_M DCLKP,DCLKM FCLKP,FCLKM NC 29 28 21 22 I I I I/O 1 1 1 1 3,4 1,2 62,63 60,61 52,53 50,51 47,48 45,46 57,58 55,56 20 O O O O O O O O O O 2 2 2 2 2 2 2 2 2 2 1 Submit Documentation Feedback 27 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com PIN ASSIGNMENTS (2-WIRE INTERFACE) (continued) PINS NAME PAD NO. 0 I/O NO. OF PINS 1 DESCRIPTION Connect to ground plane using multiple vias. Refer to Board Design Considerations in the application section. 28 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 PIN CONFIGURATION (1-WIRE INTERFACE) ADS644x RGC PACKAGE (TOP VIEW) DCLKM FCLKM DCLKP FCLKP DC_M DD_M DA_M DB_M LGND LGND DC_P DD_P DA_P DB_P LVDD UNUSED UNUSED UNUSED UNUSED CAP RESET LVDD AGND AVDD AGND INA_M INA_P AGND INB_M INB_P AGND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 3 4 5 6 7 8 47 46 45 44 43 42 41 LVDD UNUSED UNUSED UNUSED UNUSED SCLK SDATA SEN PDN AVDD AGND IND_M IND_P AGND INC_M INC_P AGND PAD 9 10 11 12 13 14 15 40 39 38 37 36 35 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CFG3 CFG2 AGND CFG4 CFG1 AGND AGND AGND VCM CLKM NC AVDD AVDD CLKP AVDD AVDD P0056-05 PIN ASSIGNMENTS (1-WIRE INTERFACE) PINS NAME NO. 9,17,19,27,32, 40 8,10,13,16,18, 23, 26,31,33,36,39 7,49,64 54,59 24,25 I SUPPLY AND GROUND PINS AVDD AGND LVDD LGND INPUT PINS CLKP, CLKM 2 Differential input clock pair 6 11 3 2 Analog power supply Analog ground Digital power supply Digital ground I/O NO. OF PINS DESCRIPTION Submit Documentation Feedback 29 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com PIN ASSIGNMENTS (1-WIRE INTERFACE) (continued) PINS NAME INA_P, INA_M INB_P, INB_M INC_P, INC_M IND_P, IND_M CAP SCLK NO. 12,11 15,14 34,35 37,38 5 44 I I/O I I I I NO. OF PINS 2 2 2 2 1 1 DESCRIPTION Differential input signal pair, channel A. If unused, the pins should be tied to VCM. Do not float. Differential input signal pair, channel B.If unused, the pins should be tied to VCM. Do not float. Differential input signal pair, channel C. If unused, the pins should be tied to VCM. Do not float. Differential input signal pair, channel D. If unused, the pins should be tied to VCM. Do not float. Connect 2-nF capacitance from pin to ground This pin functions as serial interface clock input when RESET is low. When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along with SDATA). Refer to Table 5 for description. This pin has an internal pull-down resistor. This pin functions as serial interface data input when RESET is low. When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along with SCLK). Refer to Table 5 for description. This pin has an internal pull-down resistor. This pin functions as serial interface enable input when RESET is low. When RESET is high, it controls coarse gain and internal/external reference modes. Refer to Table 6 for description. This pin has an internal pull-up resistor. Serial interface reset input. When using the serial interface mode, the user MUST initialize internal registers through hardware RESET by applying a high-going pulse on this pin or by using software reset option. Refer to the Serial Interface section. In parallel interface mode, tie RESET permanently high. (SCLK, SDATA and SEN function as parallel control pins in this mode). The pin has an internal pull-down resistor to ground. PDN CFG1 41 30 I I 1 1 Global power down control pin. Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock selection. Refer to Table 8 for description. Tie to ground for 1-wire interface with DDR bit clock. Parallel input pin. It controls 14x or 16x serialization and SDR bit clock capture edge. Refer to Table 9 for description. For 14x serialization with DDR bit clock, tie to ground or AVDD. RESERVED pin - Tie to ground. Parallel input pin. It controls data format and MSB or LSB first modes. Refer to Table 11 for description. Internal reference mode – common-mode voltage output External reference mode – reference input. The voltage forced on this pin sets the internal reference. Channel A differential LVDS data output pair Channel B differential LVDS data output pair Channel C differential LVDS data output pair Channel D differential LVDS data output pair Differential bit clock output pair Differential frame clock output pair These pins are unused in the 1-wire interface. Do not connect Do not connect Connect to ground plane using multiple vias. Refer to Board Design Considerations in the application section. SDATA 43 I 1 SEN 42 I 1 RESET 6 I 1 CFG2 CFG3 CFG4 VCM OUTPUT PINS DA_P,DA_M DB_P,DB_M DC_P,DC_M DD_P,DD_M DCLKP,DCLKM FCLKP,FCLKM UNUSED NC PAD 29 28 21 22 I I I I/O 1 1 1 1 62,63 60,61 52,53 50,51 57,58 55,56 1-4,45-48 20 0 O O O O O O 2 2 2 2 2 2 8 1 1 30 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 TYPICAL CHARACTERISTICS All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless otherwise noted) ADS6445 (Fsrated = 125 MSPS) FFT for 10 MHz INPUT SIGNAL 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 0 10 20 30 40 50 60 G001 FFT for 100 MHz INPUT SIGNAL 0 SFDR = 86 dBc SINAD = 72.63 dBFS SNR = 72.76 dBFS THD = 85 dBc SFDR = 88 dBc SINAD = 74 dBFS SNR = 74.3 dBFS THD = 87.6 dBc −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 0 10 20 30 40 50 60 G002 f − Frequency − MHz f − Frequency − MHz Figure 6. FFT for 230 MHz INPUT SIGNAL 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 0 10 20 30 40 50 60 G003 Figure 7. INTERMODULATION DISTORTION (IMD) vs FREQUENCY 0 SFDR = 77.9 dBc SINAD = 68 dBFS SNR = 69.2 dBFS THD = 75.3 dBc fIN1 = 185.1 MHz, –7 dBFS fIN2 = 190.1 MHz, –7 dBFS 2-Tone IMD = –86 dBFS SFDR = –95 dBFS −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 0 10 20 30 40 50 60 G004 f − Frequency − MHz f − Frequency − MHz Figure 8. Figure 9. Submit Documentation Feedback 31 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com ADS6445 (Fsrated = 125 MSPS) (continued) SFDR vs INPUT FREQUENCY 92 90 88 SFDR − dBc 86 84 82 80 78 76 74 0 50 100 150 200 250 G005 SNR vs INPUT FREQUENCY 75 74 Gain = 3.5 dB SNR − dBFS 73 72 71 70 69 Gain = 3.5 dB Gain = 0 dB Gain = 0 dB 68 67 0 50 100 150 200 250 G006 fIN − Input Frequency − MHz fIN − Input Frequency − MHz Figure 10. SFDR vs INPUT FREQUENCY ACROSS GAINS 92 90 88 SFDR − dBc 86 84 82 80 78 76 74 10 30 50 70 90 110 130 150 170 190 210 230 G007 Figure 11. SINAD vs INPUT FREQUENCY ACROSS GAINS 75 74 73 5 dB 3 dB SINAD − dBFS 72 71 70 69 68 3 dB 0 dB 3.5 dB 2 dB 1 dB Input adjusted to get −1dBFS input 6 dB 4 dB 2 dB 0 dB 1 dB 67 66 65 20 40 60 80 100 120 140 160 180 200 220 G008 4 dB 5 dB 6 dB Fin − Input Frequency − MHz Fin − Input Frequency − MHz Figure 12. PERFORMANCE vs AVDD 88 86 84 SFDR − dBc 82 80 78 76 74 72 3.0 3.1 3.2 3.3 3.4 3.5 SNR fIN = 50.1 MHz LVDD = 3.3 V SFDR 78 77 94 76 75 74 73 72 71 70 3.6 G009 Figure 13. PERFORMANCE vs LVDD 98 fIN = 50.1 MHz AVDD = 3.3 V SNR SNR − dBFS 90 73 SNR − dBFS G010 75 74 SFDR − dBc 86 SFDR 82 72 71 78 3.0 3.1 3.2 3.3 3.4 3.5 70 3.6 AVDD − Supply Voltage − V LVDD − Supply Voltage − V Figure 14. Figure 15. 32 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 ADS6445 (Fsrated = 125 MSPS) (continued) PERFORMANCE vs TEMPERATURE 86 84 SFDR SNR − dBFS SFDR − dBc 82 80 SNR 78 76 fIN = 50.1 MHz 74 −40 71 −20 0 20 40 60 80 G011 PERFORMANCE vs INPUT AMPLITUDE 77 76 75 74 73 72 SFDR − dBc, dBFS 110 100 90 80 70 60 50 SFDR (dBc) 40 30 −60 fIN = 20 MHz −50 −40 −30 −20 −10 0 G012 78 77 SFDR (dBFS) 76 75 SNR (dBFS) 74 73 72 71 70 SNR − dBFS G014 T − Temperature − °C Input Amplitude − dBFS Figure 16. PERFORMANCE vs CLOCK AMPLITUDE (differential) 86 fIN = 50.1 MHz 84 SFDR 82 SFDR − dBc 80 78 76 74 72 0.5 75 SNR − dBFS 74 73 72 71 70 3.0 G013 Figure 17. PERFORMANCE vs CLOCK DUTY CYCLE 90 SFDR 76 89 88 87 86 SNR 85 fIN = 20.1 MHz 84 35 40 45 50 55 60 65 Input Clock Duty Cycle − % 72 73 77 76 75 74 78 77 SNR 1.0 1.5 2.0 2.5 Input Clock Amplitude − VPP Figure 18. Figure 19. OUTPUT NOISE HISTOGRAM WITH INPUTS TIED TO COMMON-MODE 40 RMS LSB = 1.064 35 30 Occurence − % 25 20 15 10 POWER DISSIPATION vs SAMPLING FREQUENCY 2.0 1.8 PD − Power Dissipation − W 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 75 100 125 G015 AVDD LVDD 5 0 fS − Sampling Frequency − MSPS 8187 8188 8189 8190 8191 8192 8193 8194 8195 8196 Output Code G016 Figure 20. Figure 21. Submit Documentation Feedback SNR − dBFS SFDR − dBc 33 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com ADS6445 (Fsrated = 125 MSPS) (continued) PERFORMANCE IN EXTERNAL REFERENCE MODE fIN = 50.1 MHz External Reference Mode 92 SFDR − dBc 76 SNR − dBFS CMRR vs FREQUENCY CMRR − Common-Mode Rejection Ratio − dBc 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 0 50 100 150 200 250 300 G018 94 78 90 SNR 74 88 SFDR 86 72 70 84 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 68 1.70 G017 VVCM − VCM Voltage − V f − Frequency − MHz Figure 22. Figure 23. 34 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 ADS6444 (Fsrated = 105 MSPS) FFT for 10 MHz INPUT SIGNAL 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 0 10 20 30 40 50 G019 FFT for 70 MHz INPUT SIGNAL 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 0 10 20 30 40 50 G020 SFDR = 91.2 dBc SINAD = 73.9 dBFS SNR = 74.1 dBFS THD = 89.7 dBc SFDR = 81.2 dBc SINAD = 71.6 dBFS SNR = 72.6 dBFS THD = 79.9 dBc f − Frequency − MHz f − Frequency − MHz Figure 24. FFT for 230 MHz INPUT SIGNAL 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 0 10 20 30 40 50 G021 Figure 25. INTERMODULATION DISTORTION (IMD) vs FREQUENCY 0 SFDR = 81 dBc SINAD = 68.6 dBFS SNR = 69 dBFS THD = 79 dBc fIN1 = 185.1 MHz, –7 dBFS fIN2 = 190.1 MHz, –7 dBFS 2-Tone IMD = –88 dBFS SFDR = –89 dBFS −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 0 10 20 30 40 50 G022 f − Frequency − MHz f − Frequency − MHz Figure 26. SFDR vs INPUT FREQUENCY 92 90 88 86 84 82 80 78 76 0 50 100 150 200 250 G023 Figure 27. SNR vs INPUT FREQUENCY 76 75 74 SNR − dBFS 73 72 71 70 69 68 Gain = 3.5 dB Gain = 0 dB SFDR − dBc Gain = 3.5 dB Gain = 0 dB 67 66 0 50 100 150 200 250 G024 fIN − Input Frequency − MHz fIN − Input Frequency − MHz Figure 28. Figure 29. Submit Documentation Feedback 35 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com ADS6444 (Fsrated = 105 MSPS) (continued) SFDR vs INPUT FREQUENCY ACROSS GAINS 92 90 88 SFDR − dBc 86 84 82 80 78 76 74 10 30 50 70 90 110 130 150 170 190 210 230 G025 SINAD vs INPUT FREQUENCY ACROSS GAINS 75 74 73 0 dB Input adjusted to get −1dBFS input 4 dB 5 dB 3 dB SINAD − dBFS 3.5 dB 1 dB 2 dB 3 dB 72 71 70 69 68 67 66 65 20 40 60 80 4 dB 5 dB 6 dB 6 dB 2 dB 0 dB 1 dB 100 120 140 160 180 200 220 G026 Fin − Input Frequency − MHz Fin − Input Frequency − MHz Figure 30. PERFORMANCE vs AVDD 88 86 84 SFDR − dBc SFDR 82 80 78 76 74 72 3.0 3.1 3.2 3.3 3.4 3.5 SNR 75 74 73 72 71 70 3.6 G027 Figure 31. PERFORMANCE vs LVDD 78 98 fIN = 70.1 MHz AVDD = 3.3 V 75 fIN = 70.1 MHz LVDD = 3.3 V 77 94 74 SNR SNR − dBFS G028 G030 76 SNR − dBFS SFDR − dBc 90 73 86 SFDR 72 82 71 78 3.0 3.1 3.2 3.3 3.4 3.5 70 3.6 AVDD − Supply Voltage − V LVDD − Supply Voltage − V Figure 32. PERFORMANCE vs TEMPERATURE 86 84 SFDR SNR − dBFS SFDR − dBc 82 80 SNR 78 76 fIN = 70.1 MHz 74 −40 71 −20 0 20 40 60 80 G029 Figure 33. PERFORMANCE vs INPUT AMPLITUDE 77 76 75 74 73 72 SFDR − dBc, dBFS 110 100 90 80 70 60 50 SFDR (dBc) 40 30 −60 fIN = 20 MHz −50 −40 −30 −20 −10 0 55 50 SNR (dBFS) SFDR (dBFS) 90 85 80 75 70 65 60 SNR − dBFS T − Temperature − °C Input Amplitude − dBFS Figure 34. Figure 35. 36 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 ADS6444 (Fsrated = 105 MSPS) (continued) PERFORMANCE vs CLOCK AMPLITUDE (differential) 92 90 88 SNR 86 84 82 80 78 76 0.5 1.0 1.5 2.0 2.5 SFDR 73 72 71 70 69 68 3.0 G031 PERFORMANCE vs CLOCK DUTY CYCLE 93 fIN = 20.1 MHz 91 SFDR 75 SNR − dBFS G032 76 fIN = 70.1 MHz 75 74 SNR − dBFS SFDR − dBc 76 SFDR − dBc 89 74 87 SNR 73 85 72 83 35 40 45 50 55 60 65 Input Clock Duty Cycle − % 71 Input Clock Amplitude − VPP Figure 36. Figure 37. OUTPUT NOISE HISTOGRAM WITH INPUTS TIED TO COMMON-MODE 40 RMS LSB = 1.054 35 30 Occurence − % 25 20 15 10 5 0 POWER DISSIPATION vs SAMPLING FREQUENCY 2.0 1.8 PD − Power Dissipation − W 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 20 40 60 80 100 G033 AVDD LVDD 8179 8180 8181 8182 8183 8184 8185 8186 8187 8188 Output Code G034 fS − Sampling Frequency − MSPS Figure 38. PERFORMANCE IN EXTERNAL REFERENCE MODE fIN = 70.1 MHz External Reference Mode 84 SFDR − dBc SNR 74 SNR − dBFS Figure 39. CMRR vs FREQUENCY CMRR − Common-Mode Rejection Ratio − dBc 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 0 50 100 150 200 250 300 G018 85 76 83 72 82 SFDR 70 81 68 80 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 66 1.70 G035 VVCM − VCM Voltage − V f − Frequency − MHz Figure 40. Figure 41. Submit Documentation Feedback 37 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com ADS6443 (Fsrated = 80 MSPS) FFT for 10 MHz INPUT SIGNAL 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 0 10 20 f − Frequency − MHz 30 40 G037 FFT for 70 MHz INPUT SIGNAL 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 0 10 20 f − Frequency − MHz 30 40 G038 SFDR = 91 dBc SINAD = 74.2 dBFS SNR = 74.4 dBFS THD = 88.5 dBc SFDR = 85.7 dBc SINAD = 73 dBFS SNR = 73.5 dBFS THD = 83.9 dBc Figure 42. FFT for 230 MHz INPUT SIGNAL 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 0 10 20 f − Frequency − MHz 30 40 G039 Figure 43. INTERMODULATION DISTORTION (IMD) vs FREQUENCY 0 SFDR = 82 dBc SINAD = 69.4 dBFS SNR = 69.7 dBFS THD = 83.4 dBc fIN1 = 185.1 MHz, –7 dBFS fIN2 = 190.1 MHz, –7 dBFS 2-Tone IMD = –93 dBFS SFDR = –98 dBFS −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 0 10 20 f − Frequency − MHz 30 40 G040 Figure 44. SFDR vs INPUT FREQUENCY 96 94 92 SNR − dBFS SFDR − dBc 90 88 86 84 82 80 78 76 0 50 100 150 200 250 G041 Figure 45. SNR vs INPUT FREQUENCY 76 75 74 73 72 71 70 69 68 67 66 0 50 100 150 200 250 G042 Gain = 0 dB Gain = 3.5 dB Gain = 3.5 dB Gain = 0 dB fIN − Input Frequency − MHz fIN − Input Frequency − MHz Figure 46. Figure 47. 38 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 ADS6443 (Fsrated = 80 MSPS) (continued) SFDR vs INPUT FREQUENCY ACROSS GAINS 94 92 90 SFDR − dBc 88 86 84 82 80 78 76 10 30 50 70 90 110 130 150 170 190 210 230 G043 SINAD vs INPUT FREQUENCY ACROSS GAINS 75 74 73 SINAD − dBFS 2 dB 1 dB 3 dB 3.5 dB 0 dB Input adjusted to get −1dBFS input 4 dB 5 dB 3 dB 72 71 70 69 68 6 dB 2 dB 1 dB 0 dB 67 66 65 20 4 dB 5 dB 6 dB 40 60 80 100 120 140 160 180 200 220 G044 Fin − Input Frequency − MHz Fin − Input Frequency − MHz Figure 48. PERFORMANCE vs AVDD 94 92 90 SFDR 88 86 84 82 3.0 SNR 75 74 73 72 3.6 G045 Figure 49. PERFORMANCE vs LVDD 78 92 91 90 89 88 SFDR 87 86 3.0 71 70 3.6 G046 76 fIN = 50.1 MHz AVDD = 3.3 V SNR 75 74 73 72 fIN = 50.1 MHz LVDD = 3.3 V 77 76 SNR − dBFS SFDR − dBc 3.1 3.2 3.3 3.4 3.5 3.1 3.2 3.3 3.4 3.5 AVDD − Supply Voltage − V LVDD − Supply Voltage − V Figure 50. PERFORMANCE vs TEMPERATURE 92 fIN = 50.1 MHz 90 SFDR − dBc SFDR 88 76 77 SFDR − dBc, dBFS Figure 51. PERFORMANCE vs INPUT AMPLITUDE 78 110 100 90 80 70 60 50 SFDR (dBc) 40 55 fIN = 20 MHz −50 −40 −30 −20 −10 0 G048 90 85 SFDR (dBFS) 80 75 SNR (dBFS) 70 65 60 SNR − dBFS 86 SNR 84 75 74 30 −60 G047 SNR − dBFS 82 −40 73 −20 0 20 40 60 80 T − Temperature − °C 50 Input Amplitude − dBFS Figure 52. Figure 53. Submit Documentation Feedback SNR − dBFS SFDR − dBc 39 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com ADS6443 (Fsrated = 80 MSPS) (continued) PERFORMANCE vs CLOCK AMPLITUDE (differential) 92 90 88 SFDR − dBc 86 84 82 80 78 76 0.5 1.0 1.5 2.0 2.5 SNR SFDR fIN = 50.1 MHz 78 77 76 SNR − dBFS SFDR − dBc 75 74 73 72 84 71 70 3.0 G049 PERFORMANCE vs CLOCK DUTY CYCLE 92 76 90 SFDR 75 SNR − dBFS G050 88 74 86 SNR 73 72 fIN = 20.1 MHz 82 35 40 45 50 55 60 Input Clock Duty Cycle − % 71 65 Input Clock Amplitude − VPP Figure 54. Figure 55. OUTPUT NOISE HISTOGRAM WITH INPUTS TIED TO COMMON-MODE 40 RMS LSB = 1.016 35 30 Occurence − % 25 20 15 10 POWER DISSIPATION vs SAMPLING FREQUENCY 2.0 1.8 PD − Power Dissipation − W 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 20 40 60 80 G051 AVDD LVDD 5 0 fS − Sampling Frequency − MSPS 8180 8181 8182 8183 8184 8185 8186 8187 8188 8189 Output Code G052 Figure 56. PERFORMANCE IN EXTERNAL REFERENCE MODE fIN = 50.1 MHz External Reference Mode 94 SFDR − dBc SNR 74 SNR − dBFS Figure 57. CMRR vs FREQUENCY CMRR − Common-Mode Rejection Ratio − dBc 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 0 50 100 150 200 250 300 G018 96 76 92 72 90 SFDR 70 88 68 86 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 66 1.70 G053 VVCM − VCM Voltage − V f − Frequency − MHz Figure 58. Figure 59. 40 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 ADS6442 (Fsrated = 65 MSPS) FFT for 10 MHz INPUT SIGNAL 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 0 10 20 30 G055 FFT for 50 MHz INPUT SIGNAL 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 0 10 20 30 G056 SFDR = 92.4 dBc SINAD = 74.3 dBFS SNR = 74.5 dBFS THD = 90 dBc SFDR = 88.8 dBc SINAD = 73.6 dBFS SNR = 73.9 dBFS THD = 86.6 dBc f − Frequency − MHz f − Frequency − MHz Figure 60. FFT for 230 MHz INPUT SIGNAL 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 0 10 20 30 G057 Figure 61. INTERMODULATION DISTORTION (IMD) vs FREQUENCY 0 fIN1 = 185.1 MHz, –7 dBFS fIN2 = 190.1 MHz, –7 dBFS 2-Tone IMD = –96 dBFS SFDR = –86 dBFS SFDR = 82.1 dBc SINAD = 69.3 dBFS SNR = 69.7 dBFS THD = 81.2 dBc −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 0 10 20 30 G058 f − Frequency − MHz f − Frequency − MHz Figure 62. SFDR vs INPUT FREQUENCY 96 94 92 SNR − dBFS SFDR − dBc 90 88 86 84 82 80 78 76 0 50 100 150 200 250 G059 Figure 63. SNR vs INPUT FREQUENCY 76 75 74 73 72 71 70 Gain = 3.5 dB Gain = 0 dB Gain = 3.5 dB Gain = 0 dB 69 68 67 0 50 100 150 200 250 G060 fIN − Input Frequency − MHz fIN − Input Frequency − MHz Figure 64. Figure 65. Submit Documentation Feedback 41 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com ADS6442 (Fsrated = 65 MSPS) (continued) SFDR vs INPUT FREQUENCY ACROSS GAINS 96 94 92 SFDR − dBc 90 88 86 84 82 80 78 76 10 30 50 70 90 110 130 150 170 190 210 230 G061 SINAD vs INPUT FREQUENCY ACROSS GAINS 75 74 73 SINAD − dBFS 72 71 70 69 68 67 Input adjusted to get −1dBFS input 5 dB 3 dB 4 dB 3.5 dB 1 dB 2 dB 3 dB 0 dB 6 dB 1 dB 2 dB 0 dB 4 dB 66 65 20 40 60 5 dB 6 dB 80 100 120 140 160 180 200 220 G062 Fin − Input Frequency − MHz Fin − Input Frequency − MHz Figure 66. PERFORMANCE vs AVDD 94 92 90 88 86 SNR 84 82 3.0 73 72 3.6 G063 Figure 67. PERFORMANCE vs LVDD 78 92 91 90 89 88 87 86 3.0 SFDR fIN = 50.1 MHz AVDD = 3.3 V SNR 76 75 74 73 72 71 70 3.6 G064 fIN = 50.1 MHz LVDD = 3.3 V 77 76 75 74 SNR − dBFS SFDR − dBc SFDR − dBc SFDR 3.1 3.2 3.3 3.4 3.5 3.1 3.2 3.3 3.4 3.5 AVDD − Supply Voltage − V LVDD − Supply Voltage − V Figure 68. PERFORMANCE vs TEMPERATURE 96 94 92 90 88 SNR 86 fIN = 50.1 MHz 84 −40 73 −20 0 20 40 60 80 G065 Figure 69. PERFORMANCE vs INPUT AMPLITUDE 79 78 77 76 75 74 SFDR − dBc, dBFS 110 100 90 80 70 60 50 SFDR (dBc) 40 30 −60 fIN = 20 MHz −50 −40 −30 −20 −10 0 G066 90 85 SFDR (dBFS) 80 75 SNR (dBFS) 70 65 60 55 50 SNR − dBFS SFDR T − Temperature − °C SNR − dBFS SFDR − dBc Input Amplitude − dBFS Figure 70. Figure 71. 42 Submit Documentation Feedback SNR − dBFS www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 ADS6442 (Fsrated = 65 MSPS) (continued) PERFORMANCE vs CLOCK AMPLITUDE (differential) 96 94 92 SFDR − dBc 90 88 86 84 82 80 0.5 1.0 1.5 2.0 2.5 SNR SFDR fIN = 50.1 MHz 80 79 93 75 SFDR SNR − dBFS G068 PERFORMANCE vs CLOCK DUTY CYCLE 95 76 78 77 76 75 74 73 72 3.0 G067 SNR − dBFS SFDR − dBc 91 74 89 SNR 87 fIN = 20.1 MHz 85 35 40 45 50 55 60 65 Input Clock Duty Cycle − % 73 72 71 Input Clock Amplitude − VPP Figure 72. Figure 73. OUTPUT NOISE HISTOGRAM WITH INPUTS TIED TO COMMON-MODE 40 RMS LSB = 1.027 35 30 Occurence − % 25 20 15 10 POWER DISSIPATION vs SAMPLING FREQUENCY 2.0 1.8 PD − Power Dissipation − W 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 10 20 30 40 50 60 G069 AVDD LVDD 5 0 fS − Sampling Frequency − MSPS 8189 8190 8191 8192 8193 8194 8195 8196 8197 Output Code G070 Figure 74. PERFORMANCE IN EXTERNAL REFERENCE MODE fIN = 50.1 MHz External Reference Mode 94 SNR 92 72 SNR − dBFS SFDR − dBc 74 Figure 75. CMRR vs FREQUENCY CMRR − Common-Mode Rejection Ratio − dBc 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 0 50 100 150 200 250 300 G018 96 76 90 SFDR 70 88 68 86 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 66 1.70 G071 VVCM − VCM Voltage − V f − Frequency − MHz Figure 76. Figure 77. Submit Documentation Feedback 43 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com Contour Plots across Input and Sampling Frequencies 125 120 110 86 89 80 83 92 89 65 86 83 80 74 77 86 80 83 86 89 80 83 89 86 30 10 50 100 83 150 80 200 250 300 77 74 350 400 450 71 68 65 500 77 65 74 71 68 71 68 fS - Sampling Frequency - MSPS 100 83 90 80 70 60 50 40 86 fIN - Input Frequency - MHz 65 70 75 80 85 90 SFDR - dBc M0049-13 Figure 78. SFDR Contour (no gain) 125 120 110 91 94 90 80 91 70 60 50 40 91 30 10 50 100 85 150 200 82 79 250 76 300 350 400 73 450 500 88 76 70 85 79 88 85 91 79 88 82 76 70 88 88 85 82 76 82 70 73 67 79 73 fS - Sampling Frequency - MSPS 100 fIN - Input Frequency - MHz 65 70 75 80 85 90 SFDR - dBc M0049-14 Figure 79. SFDR Contour (3.5dB coarse gain) 44 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 Contour Plots across Input and Sampling Frequencies (continued) 125 120 110 74 73 72 71 70 69 68 67 66 65 64 fS - Sampling Frequency - MSPS 100 90 80 70 60 50 67 40 74 30 10 50 73 72 100 71 70 150 69 68 200 250 66 300 65 350 64 400 63 450 62 500 73 72 71 70 69 66 65 64 68 67 66 64 65 74 fIN - Input Frequency - MHz 60 65 70 75 SNR - dBFS M0048-13 Figure 80. SNR Contour (no gain) 125 120 72 110 71 70 69 68 67 66 65 fS - Sampling Frequency - MSPS 100 90 67 80 72 70 60 50 72 40 30 10 70 50 100 150 200 71 67 69 68 250 66 65 64 300 350 64 63 400 62 450 63 61 500 71 70 69 68 65 66 64 fIN - Input Frequency - MHz 60 62 64 66 68 70 72 SNR - dBFS M0048-14 Figure 81. SNR Contour (3.5dB coarse gain) Submit Documentation Feedback 45 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of quad channel, 14-bit pipeline ADC based on switched capacitor architecture in CMOS technology. The conversion is initiated simultaneously by all the four channels at the rising edge of the external input clock. After the input signals are captured by the sample and hold circuit of each channel, the samples are sequentially converted by a series of low resolution stages. The stage outputs are combined in a digital correction logic block to form the final 14-bit word with a latency of 12 clock cycles. The 14-bit word of each channel is serialized and output as LVDS levels. In addition to the data streams, a bit clock and frame clock are also output. The frame clock is aligned with the 14-bit word boundary. ANALOG INPUT The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in Figure 82. This differential topology results in very good AC performance even for high input frequencies. The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V, available on VCM pin 13. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM + 0.5 V and VCM – 0.5 V, resulting in a 2-VPP differential input swing. The maximum swing is determined by the internal reference voltages REFP (2.0 V nominal) and REFM (1.0 V, nominal). The sampling circuit has a 3 dB bandwidth that extends up to 500 MHz (see Figure 83, shown by the transfer function from the analog input pins to the voltage across the sampling capacitors, TF_ADC). Sampling Switch Lpkg 6 nH INP Cbond 2 pF Resr 200 W 50 W 3.2 pF Cpar2 Ron 1 pF 15 W Csamp 4.0 pF Ron 10 W Csamp 4.0 pF RCR Filter Sampling Capacitor 25 W Cpar1 0.8 pF Lpkg 6 nH INM Cbond 2 pF Resr 200 W 50 W 25 W Cpar2 1 pF Ron 15 W Sampling Capacitor Sampling Switch S0237-01 Figure 82. Input Sampling Circuit 46 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 APPLICATION INFORMATION (continued) 1 0 Magnitude − dB −1 −2 −3 −4 −5 −6 0 100 200 300 400 500 600 700 G073 fIN − Input Frequency − MHz Figure 83. Analog Input Bandwidth (represented by magnitude of TF_ADC, see Figure 85 ) Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity and even order harmonic rejection. A 5-Ω resistor in series with each input pin is recommended to damp out ringing caused by the package parasitics. It is also necessary to present low impedance (< 50 Ω) for the common mode switching currents. For example, this is achieved by using two resistors from each input terminated to the common mode voltage (VCM). In addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. While doing this, the ADC input impedance has to be taken into account. Figure 84 shows that the impedance (Zin, looking into the ADC input pins) decreases at high input frequencies. The smith chart shows that the input impedance is capacitive and can be approximated by a series R-C upto 500 MHz. Submit Documentation Feedback 47 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com APPLICATION INFORMATION (continued) F1 Freq = 50 MHz S(1, 1) = 0.967 / –13.241 Impedance = 62.211 – j421.739 1000 900 800 F1 Frequency = 50 MHz Mag(Zin1) = 426.302 F2 Frequency = 400 MHz Mag(Zin1) = 65.193 S(1, 1) Magnitude of Zin -- W 700 600 500 400 300 200 100 0 0 50 100 150 200 250 300 F1 F2 F1 F2 350 400 450 500 fI -- Input Frequency -- MHz Frequency (100 kHz to 500 MHz) F2 Freq = 400 MHz S(1, 1) = 0.273 / –59.329 Impedance = 58.132 – j29.510 M0087-01 Figure 84. ADC Input Impedance, Zin Using RF-Transformers Based Drive Circuits Figure 85 shows a configuration using a single 1:1 turns ratio transformer (for example, Coilcraft WBC1-1) that can be used for low input frequencies up to 100 MHz. The single-ended signal is fed to the primary winding of the RF transformer. The transformer is terminated on the secondary side. Putting the termination on the secondary side helps to shield the kickbacks caused by the sampling circuit from the RF transformer’s leakage inductances. The termination is accomplished by two resistors connected in series, with the center point connected to the 1.5 V common mode (VCM pin). The value of the termination resistors (connected to common mode) has to be low (< 100 Ω) to provide a low-impedance path for the ADC common-mode switching current. 48 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 APPLICATION INFORMATION (continued) TF_ADC 0.1 mF 5W ADS6xxx INP 0.1 mF 25 W 25 W INM 1:1 5W VCM S0256-01 Figure 85. Single Transformer Drive Circuit At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch, and good performance is obtained for high frequency input signals. Figure 86 shows an example using two transformers (like Coilcraft WBC1-1). An additional termination resistor pair (enclosed within the shaded box in Figure 86) may be required between the two transformers to improve the balance between the P and M sides. The center point of this termination must be connected to ground. ADS6xxx 0.1 mF 5W INP 50 W 0.1 mF 50 W 50 W 50 W INM 1:1 1:1 5W VCM S0164-04 Figure 86. Two Transformer Drive Circuit Submit Documentation Feedback 49 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com APPLICATION INFORMATION (continued) Using Differential Amplifier Drive Circuits Figure 87 shows a drive ciruit using a differential amplifier (TI's THS4509) to convert a single-ended input to differential output that can be interfaced to the ADC input pins. In addition to the single-ended to differential conversion, the amplifier also provides gain (10 dB in Figure 87). As shown in the figure, RFIL helps to isolate the amplifier output from the switching inputs of the ADC. Together with CFIL, it also forms a low-pass filter that bandlimits the noise (and signal) at the ADC input. As the amplifier outputs are ac-coupled, the common-mode voltage of the ADC input spins is set using two resistors connected to VCM. The amplifier outputs can also be dc-coupled. Using the output common-mode control of the THS4509, the ADC input pins can be biased to 1.5 V. In this case, use +4 V and -1 V supplies for the THS4509 to ensure that it's output common-mode voltage (1.5 V) is at mid-supply. RF +VS 500 W RS 0.1 mF RG 0.1 mF RT RG CM THS4509 RFIL 500 W –VS CFIL 0.1 mF 200 W INM RS || RT 0.1 mF 5W VCM 0.1 mF 10 mF 0.1 mF ADS6xxx CFIL 200 W RFIL 0.1 mF 0.1 mF 10 mF 5W INP RF S0259-01 Figure 87. Drive Circuit using THS4509 Refer to the EVM User Guide (SLAU196) for more information. INPUT COMMON MODE To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1-µF low-inductance capacitor connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC sinks a common-mode current in the order of 155 µA at 125 MSPS (per input pin). Equation 1 describes the dependency of the common-mode current and the sampling frequency. 155 mAxFs 125 MSPS (1) This equation helps to design the output capability and impedance of the CM driving circuit accordingly. 50 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 APPLICATION INFORMATION (continued) REFERENCE The ADS644X has built-in internal references REFP and REFM, requiring no external components. Design schemes are used to linearize the converter load seen by the references; this and the on-chip integration of the requisite reference capacitors eliminates the need for external decoupling. The full-scale input range of the converter can be controlled in the external reference mode as explained below. The internal or external reference modes can be selected by programming the register bit (refer to Table 13). INTREF VCM Internal Reference 1 kW 4 kW INTREF EXTREF REFM REFP ADS6xxx S0165-04 Figure 88. Reference Section Internal Reference When the device is in internal reference mode, the REFP and REFM voltages are generated internally. Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog input pins. External Reference When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential input voltage corresponding to full-scale is given by Equation 2. Full−scale differential input pp + (Voltage forced on VCM) 1.33 (2) In this mode, the range of voltage applied on VCM should be 1.45 V to 1.55 V. The 1.5-V common-mode voltage to bias the input pins has to be generated externally. Submit Documentation Feedback 51 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com APPLICATION INFORMATION (continued) COARSE GAIN AND PROGRAMMABLE FINE GAIN ADS644X includes gain settings that can be used to get improved SFDR performance (compared to 0 dB gain mode). The gain settings are 3.5 dB coarse gain and programmable fine gain from 0 dB to 6 dB. For each gain setting, the analog input full-scale range scales proportionally, as listed in Table 21. The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR (as seen in Figure 10 and Figure 11). The fine gain is programmable in 1 dB steps from 0 to 6 dB. With fine gain also, SFDR improvement is achieved, but at the expense of SNR (there is about 1dB SNR degradation for every 1dB of fine gain). So, the fine gain can be used to trade-off between SFDR and SNR. The coarse gain makes it possible to get best SFDR but without losing SNR significantly. At high input frequencies, the gains are especially useful as the SFDR improvement is significant with marginal degradation in SINAD. The gains can be programmed using the register bits (refer to Table 18) and (refer to Table 17). Note that the default gain after reset is 0 dB. Table 21. Full-Scale Range Across Gains GAIN, dB 0 3.5 1 2 3 4 5 6 Fine setting (programmable) TYPE Default (after reset) Coarse setting (fixed) FULL-SCALE, VPP 2 1.34 1.78 1.59 1.42 1.26 1.12 1.00 CLOCK INPUT The ADS644X clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5-kΩ resistors as shown in Figure 89. This allows using transformer-coupled drive circuits for sine wave clock or ac-coupling for LVPECL, LVDS clock sources (see Figure 90 and Figure 92). 52 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 VCM VCM 5 kW 5 kW CLKP CLKM ADS6xxx S0166-04 Figure 89. Internal Clock Buffer 0.1 mF CLKP Differential Sine-Wave or PECL or LVDS Clock Input 0.1 mF CLKM ADS6xxx S0167-05 Figure 90. Differential Clock Driving Circuit Figure 91 shows a typical scheme using PECL clock drive from a CDCM7005 clock driver. SNR performance with this scheme is comparable with that of a low jitter sine wave clock source. Submit Documentation Feedback 53 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com VCC Reference Clock VCC REF_IN Y0 Y0B CDCM7005 ADS6xxx CLKP CLKM VCXO OUTP OUTM CTRL VCXO_INP CP_OUT VCXO_INM S0238-02 Figure 91. PECL Clock Drive Using CDCM7005 Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin) connected to ground with a 0.1-µF capacitor, as shown in Figure 92. 0.1 mF CMOS Clock Input CLKP 0.1 mF CLKM ADS6xxx S0168-07 Figure 92. Single-Ended Clock Driving Circuit For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a non-50% duty cycle clock input. CLOCK BUFFER GAIN When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is increased. Hence, it is recommended to use large clock amplitude. As shown by Figure 18, use clock amplitude greater than 1VPP to avoid performance degradation. In addition, the clock buffer has programmable gain to amplify the input clock to support very low clock amplitude. The gain can be set by programming the register bits (refer to Table 14) and increases monotonically from Gain 0 to Gain 4 settings. Table 22 lists the minimum clock amplitude supported for each gain setting. 54 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 Table 22. Minimum Clock Amplitude across gains CLOCK BUFFER GAIN Gain 0 (minimum gain) Gain 1 (default gain) Gain 2 Gain 3 Gain 4 (highest gain) MINIMUM CLOCK AMPLITUDE SUPPORTED mVPP differential 800 400 300 200 150 POWER DOWN MODES The ADS644X has three power down modes – global power down, channel standby and input clock stop. Global Power Down This is a global power down mode in which almost the entire chip is powered down, including the four ADCs, internal references, PLL and LVDS buffers. As a result, the total power dissipation falls to about 77 mW typical (with input clock running). This mode can be initiated by setting the register bit (refer to Table 13). The output data and clock buffers are in high impedance state. The wake-up time from this mode to data becoming valid in normal mode is 100 µs. Channel Standby In this mode, only the ADC of each channel is powered down and this helps to get very fast wake-up times. Each of the four ADCs can be powered down independently using the register bits (refer to Table 13). The output LVDS buffers remain powered up. The wake-up time from this mode to data becoming valid in normal mode is 200 clock cycles. Input Clock Stop The converter enters this mode: • If the input clock frequency falls below 1 MSPS or • If the input clock amplitude is less than 400 mVPP, differential with default clock buffer gain setting) at any sampling frequency. All ADCs and LVDS buffers are powered down and the power dissipation is about 235 mW. The wake-up time from this mode to data becoming valid in normal mode is 100 µs. Table 23. Power Down Modes Summary POWER DOWN MODE In power-up Global power down 1 Channel in standby 2 Channels in standby 3 Channels in standby 4 Channels in standby Input clock stop (1) Sampling frequency = 125 MSPS. AVDD POWER (mW) 1360 65 1115 825 532 245 (1) (1) (1) (1) LVDD POWER (mW) 297 12 297 297 297 297 35 (1) (1) (1) (1) WAKE UP TIME – 100 µs 200 Clocks 200 Clocks 200 Clocks 200 Clocks 100 µs 200 POWER SUPPLY SEQUENCING During power-up, the AVDD and LVDD supplies can come up in any sequence. The two supplies are separated inside the device. Externally, they can be driven from separate supplies or from a single supply. Submit Documentation Feedback 55 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com DIGITAL OUTPUT INTERFACE The ADS644X offers several flexible output options making it easy to interface to an ASIC or an FPGA. Each of these options can be easily programmed using either parallel pins or the serial interface. The output interface options are: • 1-Wire, 1× frame clock, 14× and 16× serialization with DDR bit clock • 2-Wire, 1× frame clock, 16× serialization, with DDR and SDR bit clock, byte wise/bit wise/word wise • 2-Wire, 1× frame clock, 14× serialization, with SDR bit clock, byte wise/bit wise/word wise • 2-Wire, (0.5 x) frame clock, 14× serialization, with DDR bit clock, byte wise/bit wise/word wise The maximum sampling frequency, bit clock frequency and output data rate will vary depending on the interface options selected (refer to Table 12). Table 24. Maximum Recommended Sampling Frequency for Different Output Interface Options MAXIMUM RECOMMENDED SAMPLING FREQUENCY, MSPS 65 65 125 125 65 65 BIT CLOCK FREQUENCY, MHZ 455 520 437.5 500 455 520 FRAME CLOCK FREQUENCY, MHZ 65 65 62.5 125 65 65 SERIAL DATA RATE, Mbps 910 1040 875 1000 910 1040 INTERFACE OPTIONS 1-Wire 2-Wire 2-Wire DDR Bit clock DDR Bit clock SDR Bit clock 14× Serialization 16× Serialization 14× Serialization 16× Serialization 14× Serialization 16× Serialization Each interface option is described in detail in the following sections. 1-WIRE INTERFACE - 14× AND 16× SERIALIZATION WITH DDR BIT CLOCK Here the device outputs the data of each ADC serially on a single LVDS pair (1-wire). The data is available at the rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at the rising edge of every frame clock, starting with the MSB. Optionally, it can also be programmed to output the LSB first. The data rate is 14 × sample frequency (14× serialization) and 16 × sample frequency (16× serialization). 56 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 Input Clock, CLKP/M Freq = Fs Frame Clock, FCLKP Freq = 1 ´ Fs 12-Bit Serialization Bit Clock – DDR, DCLKP/M Freq = 7 ´ Fs Output Data DA, DB, DC, DD Data Rate = 14 ´ Fs D13 (D0) D12 (D1) D11 (D2) D10 (D3) D9 (D4) D8 (D5) D7 (D6) D6 (D7) D5 (D8) D4 (D9) D3 D2 D1 D0 D13 (D0) D12 (D1) (D10) (D11) (D12) (D13) (1) 16-Bit Serialization Bit Clock – DDR, DCLKP/M Freq = 8 ´ Fs Output Data DA, DB, DC, DD Data Rate = 16 ´ Fs 0 (D0) 0 (D1) D13 (D2) D12 (D3) D11 (D4) D10 (D5) D9 (D6) D8 (D7) D7 (D8) D6 D5 D4 D3 D2 (D9) (D10) (D11) (D12) (D13) D1 (0) D0 (0) 0 (D0) 0 (D1) Sample N Data Bit in MSB First Mode D13 (D2) Sample N + 1 Data Bit in LSB First Mode (1) In 16-Bit serialization, two zero bits are padded to the 14-bit ADC data on the MSB side. T0225-02 Figure 93. 1-Wire Interface 2-WIRE INTERFACE - 16× SERIALIZATION WITH DDR/SDR BIT CLOCK The 2-wire interface is recommended for sampling frequencies above 65 MSPS. In 16× serialization, two zero bits are padded to the 14-bit ADC data on the MSB side and the combined 16-bit data is serialized and output over two LVDS pairs. The data rate is 8 × Sample frequency since 8 bits are sent on each wire every clock cycle. The data is available along with DDR bit clock or optionally with SDR bit clock. Each ADC sample is sent over the 2 wires as byte-wise or bit-wise or word-wise. Using the 16× serialization makes it possible to upgrade to a 16-bit ADC in the future seamlessly, without requiring any modification to the receiver capture logic design. Submit Documentation Feedback 57 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com Input Clock, CLKP/M Freq = Fs Frame Clock, FCLKP/M Freq = 1 ´ Fs Bit Clock – SDR, DCLKP/M Freq = 8 ´ Fs Bit Clock – DDR, DCLKP/M Freq = 4 ´ Fs In Byte-Wise Mode Output Data DA0, DB0, DC0, DD0 D7 (D0) D6 (D1) D5 (D2) D4 (D3) D3 (D4) D2 (D5) D1 (D6) D0 (D7) D7 (D0) D6 (D1) D5 (D2) D4 (D3) D3 (D4) D2 (D5) D1 (D6) D0 (D7) Output Data DA1, DB1, DC1, DD1 0 (D8) 0 (D9) D13 D12 D11 D10 (D10) (D11) (D12) (D13) D9 (0) D8 (0) 0 (D8) 0 (D9) D13 D12 D11 D10 (D10) (D11) (D12) (D13) D9 (0) D8 (0) Data Rate = 8 ´ Fs In Bit-Wise Mode Output Data DA0, DB0, DC0, DD0 0 (D0) D12 (D2) D10 (D4) D8 (D6) D6 (D8) D4 D2 (D10) (D12) D0 (0) 0 (D0) D12 (D2) D10 (D4) D8 (D6) D6 (D8) D4 D2 D0 (0) (D10) (D12) Output Data DA1, DB1, DC1, DD1 0 (D1) D13 (D3) D11 (D5) D9 (D7) D7 (D9) D5 D3 (D11) (D13) D1 (0) 0 (D1) D13 (D3) D11 (D5) D9 (D7) D7 (D9) D5 D3 (D11) (D13) D1 (0) In Word-Wise Mode Output Data DA0, DB0, DC0, DD0 0 (D0) 0 (D1) D13 (D2) D12 (D3) D11 (D4) D10 (D5) D9 (D6) D8 (D7) D7 (D8) D6 (D9) D5 D4 D3 D2 (D10) (D11) (D12) (D13) D1 (0) D0 (0) Output Data DA1, DB1, DC1, DD1 0 (D0) 0 (D1) D13 (D2) D12 (D3) D11 (D4) D10 (D5) D9 (D6) D8 (D7) D7 (D8) D6 (D9) D5 D4 D3 D2 (D10) (D11) (D12) (D13) D1 (0) D0 (0) Data Bit in MSB First Mode D13 (D3) White Cells – Sample N Data Bit in LSB First Mode Grey Cells – Sample N + 1 T0226-02 Figure 94. 2-Wire Interface 16× Serialization 58 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 2-WIRE INTERFACE - 14× SERIALIZATION The 14-bit ADC data is serialized and output over two LVDS pairs. A frame clock at 1× sample frequency is also available with an SDR bit clock. With DDR bit clock option, the frame clock frequency is 0.5× sample frequency. The output data rate will be 7 × sample frequency as 7 data bits are output every clock cycle on each wire. Each ADC sample is sent over the 2 wires as byte-wise or bit-wise or word-wise. Submit Documentation Feedback 59 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com Input Clock, CLK Freq = Fs Frame Clock, FCLK Freq = 1 ´ Fs Bit Clock – SDR, DCLK Freq = 7 ´ Fs In Byte-Wise Mode Output Data DA0, DB0, DC0, DD0 D6 (D0) D5 (D1) D4 (D2) D3 (D3) D2 (D4) D1 (D5) D0 (D6) D6 (D0) D5 (D1) D4 (D2) D3 (D3) D2 (D4) D1 (D5) D0 (D6) D6 (D0) D5 (D1) Output Data DA1, DB1, DC1, DD1 D13 (D7) D12 (D8) D11 (D9) D10 D9 D8 D7 (D10) (D11) (D12) (D13) D13 (D7) D12 (D8) D11 (D9) D10 D9 (D10) (D11) D8 (0) D7 (0) D13 (D7) D12 (D8) Data Rate = 7 ´ Fs In Bit-Wise Mode Output Data DA0, DB0, DC0, DD0 D12 (D0) D10 (D2) D8 (D4) D6 (D6) D4 (D8) D2 D0 (D10) (D12) D12 (D0) D10 (D2) D8 (D4) D6 (D6) D4 (D8) D2 D0 (D10) (D12) D12 (D0) D10 (D2) Output Data DA1, DB1, DC1, DD1 D13 (D1) D11 (D3) D9 (D5) D7 (D7) D5 (D9) D3 D1 (D11) (D13) D13 (D1) D11 (D3) D9 (D5) D7 (D7) D5 (D9) D3 D1 (D11) (D13) D13 (D1) D11 (D3) In Word-Wise Mode Output Data DA0, DB0, DC0, DD0 D13 (D0) D12 (D1) D11 (D2) D10 (D3) D9 (D4) D8 (D5) D7 (D6) D6 (D7) D5 (D8) D4 (D9) D3 D2 D1 D0 (D10) (D11) (D12) (D13) D13 (D0) D12 (D1) Output Data DA1, DB1, DC1, DD1 D13 (D0) D12 (D1) D11 (D2) D10 (D3) D9 (D4) D8 (D5) D7 (D6) D6 (D7) D5 (D8) D4 (D9) D3 D2 D1 D0 (D10) (D11) (D12) (D13) D13 (D0) D12 (D1) Data Bit in MSB First Mode D6 (D0) White Cells – Sample N Data Bit in LSB First Mode Grey Cells – Sample N + 1 T0227-02 Figure 95. 2-Wire Interface 14× Serialization - SDR Bit Clock 60 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 Input Clock, CLK Freq = Fs Frame Clock, FCLK Freq = 0.5 ´ Fs Bit Clock – DDR, DCLK Freq = 3.5 ´ Fs In Byte-Wise Mode Output Data DA0, DB0, DC0, DD0 D6 (D0) D5 (D1) D4 (D2) D3 (D3) D2 (D4) D1 (D5) D0 (D6) D6 (D0) D5 (D1) D4 (D2) D3 (D3) D2 (D4) D1 (D5) D0 (D6) D6 (D0) D5 (D1) Output Data DA1, DB1, DC1, DD1 D13 (D7) D12 (D8) D11 (D9) D10 D9 (D10) (D11) D8 (0) D7 (0) D13 (D7) D12 (D8) D11 (D9) D10 D9 (D10) (D11) D8 (0) D7 (0) D13 (D7) D12 (D8) Data Rate = 7 ´ Fs In Bit-Wise Mode Output Data DA0, DB0, DC0, DD0 D12 (D0) D10 (D2) D8 (D4) D6 (D6) D4 (D8) D2 (D10) D0 (0) D12 (D0) D10 (D2) D8 (D4) D6 (D6) D4 (D8) D2 D0 (D10) (D12) D12 (D0) D10 (D2) Output Data DA1, DB1, DC1, DD1 D13 (D1) D11 (D3) D9 (D5) D7 (D7) D5 (D9) D3 (D11) D1 (0) D13 (D1) D11 (D3) D9 (D5) D7 (D7) D5 (D9) D3 D1 (D11) (D13) D13 (D1) D11 (D3) In Word-Wise Mode Output Data DA0, DB0, DC0, DD0 D13 (D0) D12 (D1) D11 (D2) D10 (D3) D9 (D4) D8 (D5) D7 (D6) D6 (D7) D5 (D8) D4 (D9) D3 D2 D1 D0 (D10) (D11) (D12) (D13) 0 (D0) 0 (D1) Output Data DA1, DB1, DC1, DD1 D13 (D0) D12 (D1) D11 (D2) D10 (D3) D9 (D4) D8 (D5) D7 (D6) D6 (D7) D5 (D8) D4 (D9) D3 D2 D1 D0 (D10) (D11) (D12) (D13) D13 (D0) D12 (D1) Data Bit in MSB First Mode D6 (D0) White Cells – Sample N Data Bit in LSB First Mode Grey Cells – Sample N + 1 T0228-02 Figure 96. 2-Wire interface 14× Serialization - DDR Bit Clock Submit Documentation Feedback 61 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com OUTPUT BIT ORDER In the 2-wire interface, three types of bit order are supported - byte-wise, bit-wise and word-wise. Byte-wise: Each 14-bit sample is split across the 2 wires. Wires DA0, DB0, DC0 and DD0 carry the 7 LSB bits D6 - D0 and wires DA1, DB1, DC1 and DD1 carry the 7 MSB bits. Bit-wise: Each 14-bit sample is split across the 2 wires. Wires DA0, DB0, DC0 and DD0 carry the 7 even bits (D0,D2,D4..) and wires DA1, DB1, DC1 and DD1 carry the 7 odd bits (D1,D3,D5...). Word-wise: In this case, all 14-bits of a sample are sent over a single wire. Successive samples are sent over the 2 wires. For example sample N is sent on wires DA0, DB0, DC0 and DD0, while sample N+1 is sent over wires DA1, DB1, DC1 and DD1. The frame clock frequency is 0.5x sampling frequency, with the rising edge aligned with the start of each word. MSB/LSB FIRST By default after reset, the 14-bit ADC data is output serially with the MSB first (D13, D12, D11,...D1,D0). The data can be output LSB first also by programming the register bit . In the 2-wire mode, the bit order in each wire is flipped in the LSB first mode. OUTPUT DATA FORMATS Two output data formats are supported – 2s complement (default after reset) and offset binary. They can be selected using the serial interface register bit . In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive overdrive, the output code is 0x3FFF in offset binary output format, and 0x1FFF in 2s complement output format. For a negative input overdrive, the output code is 0x0000 in offset binary output format and 0x2000 in 2s complement output format. LVDS CURRENT CONTROL The default LVDS buffer current is 3.5 mA. With an external 100-Ω termination resistance, this develops ±350-mV logic levels at the receiver. The LVDS buffer currents can also be programmed to 2.5 mA, 3.0 mA and 4.5 mA using the register bits . In addition, there exists a current double mode, where the LVDS nominal current is doubled (register bits , refer to Table 19). LVDS INTERNAL TERMINATION An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially terminated inside the device. Five termination resistances are available – 166, 200, 250, 333, and 500 Ω (nominal with ±20% variation). Any combination of these terminations can be programmed; the effective termination will be the parallel combination of the selected resistances. The terminations can be programmed separately for the clock and data buffers (bits and , refer to Table 20). The internal termination helps to absorb any reflections from the receiver end, improving the signal integrity. This makes it possible to drive up to 10 pF of load capacitance, compared to only 5 pF without the internal termination. Figure 97 and Figure 98 show the eye diagram with 5 pF and 10 pF load capacitors (connected from each output pin to ground). With 100-Ω internal and 100-Ω external termination, the voltage swing at the receiver end will be halved (compared to no internal termination). The voltage swing can be restored by using the LVDS current double mode (bits , refer to Table 19). 62 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 C001 Figure 97. LVDS Data Eye Diagram with 5-pF Load Capacitance (No Internal Termination) C002 Figure 98. LVDS Data Eye Diagram with 10-pF Load Capacitance (100 Ω Internal Termination) Submit Documentation Feedback 63 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com CAPTURE TEST PATTERNS ADS644X outputs the bit clock (DCLK), positioned nearly at the center of the data transitions. It is recommended to route the bit clock, frame clock and output data lines with minimum relative skew on the PCB. This ensures sufficient setup/hold times for a reliable capture by the receiver. The DESKEW is a 1010... or 0101... pattern output on the serial data lines that can be used to verify if the receiver capture clock edge is positioned correctly. This may be useful in case there is some skew between DCLK and serial data inside the receiver. Once deserialized, it is required to ensure that the parallel data is aligned to the frame boundary. The SYNC test pattern can be used for this. For example, in the 1-wire interface, the SYNC pattern is 7 '1's followed by 7 '0's (from MSB to LSB). This information can be used by the receiver logic to shift the deserialized data till it matches the SYNC pattern. In addition to DESKEW and SYNC, the ADS644X includes other test patterns to verify correctness of the capture by the receiver such as all zeros, all ones and toggle. These patterns are output on all four channel data lines simultaneously. Some patterns like custom and sync are affected by the type of interface selected, serialization and bit order. Table 25. Test Patterns PATTERN All zeros All ones Toggle Custom Sync Deskew Outputs logic low. Outputs logic high. Outputs toggle pattern - alternates between 10101010101010 and 01010101010101 every clock cycle. Outputs a 14-bit custom pattern. The 14-bit custom pattern can be specified into two serial interface registers. In the 2-wire interface, each code is sent over the 2 wires depending on the serialization and bit order. Outputs a sync pattern. Outputs deskew pattern. Either = 10101010101010 or = 01010101010101 every clock cycle. DESCRIPTION Table 26. SYNC Pattern INTERFACE OPTION 1-Wire 2-Wire SERIALIZATION 14 X 16 X 14 X 16 X SYNC PATTERN ON EACH WIRE MSB-11111110000000-LSB MSB-111111111000000000-LSB MSB-1111000-LSB MSB-11110000-LSB 64 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES Setup, hold, and other timing parameters are specified across sampling frequencies and for each type of output interface in the following tables. Table 28 to Table 31: Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, CL = 5 pF, IO = 3.5 mA, RL = 100 Ω, no internal termination, unless otherwise noted. Timing parameters are ensured by design and characterization and not tested in production. Ts = 1/ Sampling frequency = 1/Fs Table 27. Clock Propagation Delay for Different Interface Options INTERFACE 1-Wire with DDR bit clock SERIALIZATION 14x 16x CLOCK PROPAGATION DELAY, tpd_clk tpd_clk = 0.428xTs + tdelay tpd_clk = 0.375xTs + tdelay SERIALIZER LATENCY clock cycles 0 2 (when tpd_clk ≥ Ts) 1 (when tpd_clk < Ts) 0 1 (when tpd_clk ≥ Ts) 0 (when tpd_clk < Ts) 0 (1) 2-Wire with DDR bit clock 14x tpd_clk = 0.857xTs + tdelay 2-Wire with SDR bit clock tpd_clk = 0.428xTs + tdelay 2-Wire with DDR bit clock 16x tpd_clk = 0.75xTs + tdelay 2-Wire with SDR bit clock tpd_clk = 0.375xTs + tdelay (1) Note that the total latency = ADC latency + internal serializer latency. The ADC latency is 12 clock cycles. Table 28. Timings for 1-Wire Interface SERIALIZATION SAMPLING FREQUENCY MSPS 65 14× 40 20 10 65 16× DATA SETUP TIME, tsu ns MIN 0.3 0.65 1.3 3.2 0.22 TYP 0.5 0.85 1.65 3.5 0.42 MAX MIN 0.4 0.7 1.6 3.2 0.35 DATA HOLD TIME, th ns TYP 0.6 0.9 1.9 3.6 0.55 3 3 3 MAX MIN tdelay ns TYP Fs ≥ 40 MSPS 4 Fs < 40 MSPS 4.5 Fs ≥ 40 MSPS 4 Fs < 40 MSPS 3 4.5 6 5 6 5 MAX Table 29. Timings for 2-Wire Interface, DDR Bit Clock SERIALIZATION SAMPLING FREQUENCY MSPS 105 92 14× 80 65 40 105 92 16× 80 65 40 DATA SETUP TIME, tsu ns MIN 0.45 0.55 0.65 0.8 1.4 0.35 0.45 0.55 0.6 1.1 TYP 0.65 0.75 0.85 1.1 1.7 0.55 0.65 0.75 0.9 1.4 MAX MIN 0.5 0.6 0.7 0.8 1.5 0.4 0.5 0.6 0.7 1.3 DATA HOLD TIME, th ns TYP 0.7 0.8 0.9 1.1 1.9 0.6 0.7 0.8 1 1.7 3.7 3.4 3.7 3.4 MAX MIN tdelay ns TYP Fs ≥ 45 MSPS 4.4 Fs < 45 MSPS 5.2 Fs ≥ 45 MSPS 4.4 Fs < 45 MSPS 5.2 6.7 5.4 6.7 5.4 MAX Submit Documentation Feedback 65 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com Table 30. Timings for 2-Wire Interface, SDR Bit Clock SERIALIZATION SAMPLING FREQUENCY MSPS 65 14× 40 20 10 65 16× 40 20 10 DATA SETUP TIME, tsu ns MIN 0.8 1.5 3.4 6.9 0.65 1.3 2.8 6.0 TYP 1 1.7 3.6 7.2 0.85 1.5 3.0 6.3 MAX MIN 1 1.6 3.3 6.6 0.8 1.4 2.8 5.8 DATA HOLD TIME, th ns TYP 1.2 1.8 3.5 6.9 1.0 1.6 3.0 6.1 3.7 3.4 3.7 3.4 MAX MIN tdelay ns TYP Fs ≥ 40 MSPS 4.4 Fs < 40 MSPS 5.2 Fs ≥ 40 MSPS 4.4 Fs < 40 MSPS 5.2 6.7 5.4 6.7 5.4 MAX Table 31. Output Jitter (applies to all interface options) SAMPLING FREQUENCY MSPS ≥ 65 BIT CLOCK JITTER, CYCLE-CYCLE ps, peak-peak MIN TYP 350 MAX FRAME CLOCK JITTER, CYCLE-CYCLE ps, peak-peak MIN TYP 75 MAX 66 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 BOARD DESIGN CONSIDERATIONS Grounding A single ground plane is sufficient to give optimum performance, provided the analog, digital and clock sections of the board are cleanly partitioned. Refer to the EVM User Guide (SLAU196) for board layout schemes. Supply Decoupling As the ADS644X already includes internal decoupling, minimal external decoupling can be used without loss in performance. Note that the decoupling capacitors can help to filter external power supply noise, so the optimum number of decoupling capacitors would depend on actual application. It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching noise from sensitive analog circuitry. In case only a single 3.3-V supply is available, it should be routed first to AVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before being routed to LVDD. Exposed Thermal Pad It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122A) and QFN/SON PCB Attachment (SLUA271A). Submit Documentation Feedback 67 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 www.ti.com DEFINITION OF SPECIFICATIONS Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low frequency value. Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay will be different across channels. The maximum variation is specified as aperture delay variation (channel-channel). Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle. Maximum Conversion Rate – The maximum sampling rate at which certified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate –The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs. Integral Nonlinearity (INL) – The INL is the deviation of the ADC's transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Gain Error – The gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. The gain error does not include the error caused by the internal reference deviation from ideal value. This is specifed separately as internal reference error. The maximum variation of the gain error across devices and across channels within a device is specified separately. Offset Error – The offset error is the difference, given in number of LSBs, between the ADC's actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV. Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference TMAX–TMIN. Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at DC and the first nine harmonics. P SNR + 10Log10 S PN (3) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. PS SINAD + 10Log10 PN ) PD (4) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's full-scale range. Effective Number of Bits (ENOB) – The ENOB is a measure of a converter’s performance as compared to the theoretical limit based on quantization noise. ENOB + SINAD * 1.76 6.02 (5) Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD). 68 Submit Documentation Feedback www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 THD + 10Log10 PS PD (6) THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. DC Power Supply Rejection Ratio (DC PSRR) – The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is typically given in units of mV/V. AC Power Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the supply voltage by the ADC. If ∆Vsup is the change in supply voltage and ∆Vout is the resultant change of the ADC output code (referred to the input), then PSRR + 20Log10 DVout , expressed in dBc DVsup (7) Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and negative overload. The deviation of the first few samples after the overload (from their expected values) is noted. Common Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input common-mode by the ADC. If ∆Vcm_in is the change in the common-mode voltage of the input pins and ∆Vout is the resultant change of the ADC output code (referred to the input), then CMRR + 20Log10 DVout , expressed in dBc DVcm_in (8) Cross-Talk (only for multi-channel ADC)– This is a measure of the internal coupling of a signal from adjacent channel into the channel of interest. It is specified separately for coupling from the immediate neighbouring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured by applying a full-scale signal in the adjacent channel. Cross-talk is the ratio of the power of the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel input. It is typically expressed in dBc. Submit Documentation Feedback 69 PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 PACKAGING INFORMATION Orderable Device ADS6442IRGCR ADS6442IRGCT ADS6443IRGCR ADS6443IRGCT ADS6444IRGCR ADS6444IRGCT ADS6445IRGCR ADS6445IRGCT (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type QFN QFN QFN QFN QFN QFN QFN QFN Package Drawing RGC RGC RGC RGC RGC RGC RGC RGC Pins Package Eco Plan (2) Qty 64 64 64 64 64 64 64 64 Lead/Ball Finish MSL Peak Temp (3) 2000 Green (RoHS & 4204878-0001 Level-3-260C-168 HR no Sb/Br) 250 Green (RoHS & 4204878-0001 Level-3-260C-168 HR no Sb/Br) 2000 Green (RoHS & 4204878-0001 Level-3-260C-168 HR no Sb/Br) 250 Green (RoHS & 4204878-0001 Level-3-260C-168 HR no Sb/Br) 2500 Green (RoHS & 4204878-0001 Level-3-260C-168 HR no Sb/Br) 250 Green (RoHS & 4204878-0001 Level-3-260C-168 HR no Sb/Br) 2000 Green (RoHS & 4204878-0001 Level-3-260C-168 HR no Sb/Br) 250 Green (RoHS & 4204878-0001 Level-3-260C-168 HR no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2007 Device Package Pins Site Reel Diameter (mm) 330 330 330 330 330 330 330 330 Reel Width (mm) 16 16 16 16 16 16 16 16 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 12 12 12 12 12 12 12 12 W Pin1 (mm) Quadrant 16 16 16 16 16 16 16 16 Q2 Q2 Q2 Q2 Q2 Q2 Q2 Q2 ADS6442IRGCR ADS6442IRGCT ADS6443IRGCR ADS6443IRGCT ADS6444IRGCR ADS6444IRGCT ADS6445IRGCR ADS6445IRGCT RGC RGC RGC RGC RGC RGC RGC RGC 64 64 64 64 64 64 64 64 TAI TAI TAI TAI TAI TAI TAI TAI 9.3 9.3 9.3 9.3 9.3 9.3 9.3 9.3 9.3 9.3 9.3 9.3 9.3 9.3 9.3 9.3 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 TAPE AND REEL BOX INFORMATION Device ADS6442IRGCR ADS6442IRGCT ADS6443IRGCR ADS6443IRGCT ADS6444IRGCR ADS6444IRGCT ADS6445IRGCR ADS6445IRGCT Package RGC RGC RGC RGC RGC RGC RGC RGC Pins 64 64 64 64 64 64 64 64 Site TAI TAI TAI TAI TAI TAI TAI TAI Length (mm) 342.9 342.9 342.9 342.9 342.9 342.9 342.9 342.9 Width (mm) 336.6 336.6 336.6 336.6 336.6 336.6 336.6 336.6 Height (mm) 28.58 28.58 28.58 28.58 28.58 28.58 28.58 28.58 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2007 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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