AEK-AUD-C1D9031
Data brief
AVAS solution based on SPC582B60E1 Chorus family MCU and FDA903D Class
D audio amplifier
Features
Product summary
AVAS solution based
on SPC582B60E1
Chorus family MCU
and FDA903D Class
D audio amplifier
AEK-AUDC1D9031
32-bit power
architecture MCU for
automotive general
SPC582B60E1
purpose applications Chorus family
Class D digital input
automotive power
amplifier
FDA903D
AutoDevKit library
plugin for SPC5STUDIO
STSWAUTODEVKIT
In-Vehicle
Infotainment
Applications
•
Embeds two FDA903D class D automotive grade audio amplifiers and an
SPC582B60E1 Chorus family MCU with 1 Mb flash
•
Supports audio stream via I2S interface
•
•
•
•
•
•
Configurable through dedicated I2C bus
Supports CAN bus interface for remote control and diagnostics
Dedicated DC diagnostic interrupt pin to signal malfunctions
Dedicated MUTE pin
Open load in play detection
Short to VCC/GND diagnostics
•
•
•
•
•
Output voltage and current detection
Thermal protection
Compact size: 110 mm x 90 mm
WEEE and RoHS compliant
Included in AutoDevKit initiative
Description
The AEK-AUD-C1D9031 is a very compact AVAS solution based on SPC582B60E1
Chorus family MCU and FDA903D Class D audio amplifiers that emits warning
sounds to alert pedestrians of the presence of e-vehicles.
The AEK-AUD-C1D9031 integrates two audio amplifiers in stereo mode or two
separate audio channels. The board compact size allows the designer to strategically
place different modules around the vehicle to ensure that warning sounds can be
heard along the entire vehicle length. All the modules can be controlled by a central
MCU via CAN interface.
The embedded SPC582B60E1 microcontroller monitors and controls the two Class-D
FDA903D power amplifiers driving the loudspeakers; the MCU sends the audio
samples via I2S bus and programs the amplifiers via I2C interface.
Acoustic Vehicle
Alerting System
(AVAS)
DB4411 - Rev 1 - February 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
AEK-AUD-C1D9031
Block diagram
1
Block diagram
Figure 1. AEK-AUD-C1D9031 block diagram
DB4411 - Rev 1
page 2/10
DB4411 - Rev 1
2
Schematic diagrams
Figure 2. AEK-AUD-C1D9031 circuit schematic (1 of 6)
Hole 3mm
JCOMP
PORST
TDO
TDI
TCK
TMS
Power Supply
Interface
CAN2_TX
CAN2_RX
HW_MUTE
I2S_TEST(A)
I2S_TEST(B)
M3
M2
M1
M4
Hole 3mm
Hole 3mm
Hole 3mm
I2S_TEST (B)
I2S_TEST (A)
HW_MUTE (A)
HW_MUTE (B)
I2S_TEST(B)
I2S_TEST(A)
Vcc_uc
J1
CAN2_TX
CAN2_RX
JCOMP
PORST
TDO
TDI
TCK
TMS
FDA903_A
I2S_WS
I2S_DATA
I2S_CLK
I2S_WS
I2S_DATA
I2S_CLK
I2S_TEST (A)
Channel A
J7
HW_MUTE (A)
HW_MUTE
4
3
2
1
CHA+
CHA-
1
2
691101710002
Volume
ADC_A39
ADC_A40
I2C_SCL
I2C_SDA
I2C_SCL
I2C_SDA
CD/DIAG (A)
61900411121
2
Vcc_uc
10k
4
430182080816
Vcc_uc
MCU
R4
3
Play/Mute
Speed
I2S_TEST (B)
HW_MUTE (B)
D6
R1
90
Play/Mute
D7
R2
150
I2S_WS
I2S_DATA
I2S_CLK
Channel B
J8
Green, 3.2V
Vcc_uc
FDA903_B
SW1
PD12
PF2
PH4
CD/DIAG (A)
CD/DIAG (B)
S3
1
CHB+
1
2
691101710002
I2C_SCL
I2C_SDA
CD/DIAG (B)
CHB-
HW MUTE
Amber, 2V
D8
Vcc_uc
Open load detect
R3
90
Blue, 3.2V
AEK-AUD-C1D9031
Schematic diagrams
page 3/10
Main Power
Q1
STD95P3LLH6AG
D1
L1
Vcc
2
2
3
XAL1010-472MEB
R5
1K3
C3
D2
C5
4.7uF, 50V
R7
22k
4.7uF, 50V
R6
22k
D3
Red, 2V
C6
1u
C8
C9
220uF, 50V
691236510002
1
VCC
220uF, 50V
Vbatt
1
GND
2
1
TP2
MMBZ5244B
J3
+12Vin
SM6T36CAY
DB4411 - Rev 1
Figure 3. AEK-AUD-C1D9031 circuit schematic (2 of 6)
C11
C12
33n
33p
GND
TP1
U2
VCC
1
LD1117S50TR
Vout
Vout
2
5V_Reg
1
1
2
R8
1K3
JP2
4
Default: 1-2
C2
10u
C4
10n
C7
C10
1u
100n
PG
EN
VO
D4
Green, 3.2V
61300411121
+5V +3V3
1
2
2
JP3
Default: 1-2
Vcc_uc
4
3
1
5
JP5
C13
C14
100n
1u
Voltage regulator
+3V3
2
R9
180
Default: 1-2
D5
Yellow, 2V
CAN voltage
3
1
3
JP1
Default: 1-2
3.3V_ext
Voltage selector
+5V +3V3
FDA voltage
1
MCU voltage
2
4 5V_ext
3
2
1 3.3V_ext
3
3
+5V +3V3
J2
NC
Exposed pad
C1
10u
Vin
GND
U1
3
VI
GND
3
+3.3V SELECT
LD39050PU33R
GND
6
0
+5V
2
+5V SELECT
5V_ext
JP4
Default: 1-2
Vcc_fda
Vcc/IO
AEK-AUD-C1D9031
Schematic diagrams
page 4/10
DB4411 - Rev 1
Figure 4. AEK-AUD-C1D9031 circuit schematic (3 of 6)
U3
C25
10n
Vcc_uc
R10
5.6k
T2 T3
ADC_A39
ADC_A40
JCOMP
TCK
TMS
TDI
TDO
Speed
Volume
15
16
JCOMP
TCK
TMS
TDI
TDO
42
43
40
39
41
51
50
CAN2_RX
CAN2_TX
R11
5.6k
PH4- eMIOS_Ch19
PF2- eMIOS_Ch20
PD12- eMIOS_Ch14
PI3- ADC39
PI4- ADC40
PA5- JCOMP
PA6- TCK
PA7- TMS
PA8- TDI
PA9- TDO
PA1- CAN2_RX
PA2- CAN2_TX
PC2- CD/DIAG_A
PE10- CD/DIAG_B
PC4- HW MUTE
PC1- Play/Mute
PORST
TESTMODE
EXTAL
XTAL
5
54
CD/DIAG (A)
CD/DIAG (B)
3
HW_MUTE
6
Play/Mute
45
44
PORST
SW1
T7
R12
4k7
Vcc_uc
PORST
36
C36
10p
3
C21
10n
56
64
8
PH4
PF2
PD12
X1
37
40MHz, +/-20ppm
1
Open load detect
HW MUTE
Play/Mute
C37
10p
32
31
I2C_SCL
I2C_SDA
T4 T5 T6
I2S_CLK
I2S_DATA
I2S_WS
I2S_TEST(A)
I2S_TEST(B)
I2S_CLK
I2S_DATA
I2S_WS
I2S_TEST(A)
I2S_TEST(B)
T1
47
C15
1u
Vcc_uc
C16
47n
33
C18
10n
C19
47n
49
C17
4.7uF, 50V
27
C22
10n
C26
47n
34
C20
100n
Vcc_uc
11
C29
10n
28
C23
100n
C32
47n
C30
100n
57
C28
470n
C35
10n
12
20
C27
100n
22
C24
470n
24
25
29
26
61
C33
100n
38
C31
10n
C34
10n
11
27
33
47
34
28
49
12
20
57
22
38
PB8- I2C_SCL
PB9- I2C_SDA
PG11- I2S_CLK
PG12- I2S_DATA
PB11- I2S_WS
PD11- I2S_TEST(A)
PC13- I2S_TEST(B)
VDD_LV_FLA0
VDD_LV_ADC_S
VDD_LV
VDD_LV
VDD_HV_IO_MAIN
VDD_HV_IO_MAIN
VDD_HV_IO_MAIN
VDD_HV_IO_MAIN
VDD_HV_ADR_S
VDD_HV_FLA
VDD_HV_ADV
VDD_HV_OSC
PA10- CAN4_TX, DSPI3_CS0, eMIOS Ch15, ...
PA11- CAN4_RX, DSPI3_SCK, eMIOS Ch16, ...
VSS_HV_OSC
VSS_HV_ADV
VSS_HV_ADR_S
VSS_LV
PI1
PI2
52
53
PA10
PA11
30
PB10- ADC82, CAN1_TX, DSPI2_SOUT/CS1, eMIOS Ch25, ...
4
PC3- CAN6_RX, DSPI3_SIN, eMIOS Ch7, ...
62
PC12- CAN4_RX, DSPI1_CS3/DSPI3_CS1, eMIOS Ch31, ...
60
PC14- DSPI1_SCK, eMIOS Ch27, ...
59
PC15- DSPI1_SOUT, eMIOS Ch26, ...
58
PD0- DSPI2_SCK, eMIOS Ch22, ...
48
PD5- CAN5_TX, DSPI0_SOUT, eMIOS Ch7, ...
9
PD13- ADC16, DSPI3_SCK, eMIOS Ch15, ...
1
PD14- CAN0_TX, ...
2
PD15- CAN0_RX, eMIOS Ch0, ...
PF3- CAN6_TX, DSPI1_CS1, eMIOS Ch2, ...
PI6- ADC49, ...
PI7- ADC50, ...
PM14- CAN4_RX, ...
PC3
PC12
PC15
PD0
PD5
PD13
PD14
PD15
7
PE2
PE3
PE11
63
PF3
PE2- ADC13, DSPI3_SOUT, eMIOS Ch13, ...
10
PE3- ADC17, DSPI3_CS0, eMIOS Ch16, ...
55
PE11- CAN5_RX, DSPI3_SOUT, eMIOS Ch18, ...
PG10- ADC55, ...
35
21
19
65
13
PI1- ADC35, CAN3_TX, DSPI2_CS1, eMIOS Ch4, ...
14
PI2- ADC38, CAN3_RX, DSPI2_CS0, eMIOS Ch5, ...
J4
2 I2S_TEST(A)
4 I2S_CLK
6 PI1
8 PD13
10 PC3
12 PD14
14 PC12
16 I2S_TEST(B)
18 PD0
20 PA11
22 PM14
24
I2S_WS
1
I2S_DATA 3
PI2
5
PE3 7
PE2 9
PD15 11
PF3 13
15
PC1517
PE11 19
PA10 21
PD5 23
61002421121
23
17
18
46
PM14
SPC582B60E1
AEK-AUD-C1D9031
Schematic diagrams
page 5/10
DB4411 - Rev 1
Figure 5. AEK-AUD-C1D9031 circuit schematic (4 of 6)
U4
Address: 0100
R13
N.M.
R15
10k
R17
N.M.
R22
R23
R24
R25
I2S_WS
I2S_CLK
I2S_DATA
I2S_TEST (A)
Vcc_fda
R19
N.M.
R26
R27
I2C_SCL
I2C_SDA
R14
10k
R16
N.M.
R18
10k
100
100
100
100
100
100
R20
10k
24
23
22
21
20
19
10
11
12
13
FBP
OUTP
OUTP
I2S_WS
I2S_CLK
I2S_DATA
I2S_TEST
FBM
OUTM
OUTM
I2C_CLK
I2C_DATA
30
10k
15
CD/DIAG (A)
FDA903D
VCCP
HW_MUTE
VCCM
CD/DIAG
VCC
C42
100n
25
DGND
DGSVR
AGSVR
AVDD
AGND
PAD
C40
1u
6
4
5
R30
10R
10u [XAL6060-103ME]
L4
CHA-
C49
330p
C54
3.3u
C57
1u
36
C46
C50
100n
1u
C47
C51
100n
1u
A5VSVR
C90
220uF, 50V
L5
17
18
C89
220uF, 50V
VCC
3
2
R31
10R
VCC
35
BLM18BA220SN1
C44
SVR
26
AVdd_A
D1V8SVR
7
14
16
34
BLM18BD102SN1
C56
1u
100p
C58
C59
10n
4.7u
28
27
C45
C52
C55
100p
10n
4.7u
37
L2
8
DVDD
TAB
VCC
C41
100n
1
C39
1u
GNDM
29
9
NC
NC
NC
NC
C38
10n
CHA+
C53
3.3u
C48
330p
R29
10R
EN1
EN2
EN3
EN4
GNDP
R21
10u [XAL6060-103ME]
L3
R28
10R
T8
HW_MUTE (A)
31
33
32
C43
4.7n
AEK-AUD-C1D9031
Schematic diagrams
page 6/10
DB4411 - Rev 1
Figure 6. AEK-AUD-C1D9031 circuit schematic (5 of 6)
U5
Address: 0010
R32
N.M.
R34
N.M.
R36
10k
R41
R42
R43
R44
I2S_WS
I2S_CLK
I2S_DATA
I2S_TEST (B)
Vcc_fda
R38
N.M.
R45
R46
I2C_SCL
I2C_SDA
R33
10k
R35
10k
R37
N.M.
100
100
100
100
100
100
R39
10k
24
23
22
21
20
19
10
11
12
13
FBP
OUTP
OUTP
I2S_WS
I2S_CLK
I2S_DATA
I2S_TEST
FBM
OUTM
OUTM
I2C_CLK
I2C_DATA
30
10k
15
CD/DIAG (B)
FDA903D
VCCP
HW_MUTE
VCCM
CD/DIAG
VCC
C64
100n
25
DGND
DGSVR
AVDD
AGND
AGSVR
PAD
26
C62
1u
C78
1u
R49
6
4
5
10R
10u [XAL6060-103ME]
L7
CHB-
C71
330p
C76
3.3u
C79
1u
VCC
35
36
C68
C72
100n
1u
C69
C73
100n
1u
A5VSVR
C92
220uF, 50V
L8
17
18
C91
220uF, 50V
VCC
3
2
R50
10R
BLM18BA220SN1
100p
C80
C81
10n
4.7u
28
27
C67
C74
C77
100p
10n
4.7u
37
AVdd_B
C75
3.3u
C66
7
14
16
34
BLM18BD102SN1
D1V8SVR
TAB
L9
8
DVDD
SVR
VCC
C63
100n
1
C61
1u
GNDM
29
9
NC
NC
NC
NC
C60
10n
CHB+
C70
330p
R48
10R
EN1
EN2
EN3
EN4
GNDP
R40
10u [XAL6060-103ME]
L6
R47
10R
T9
HW_MUTE (B)
31
33
32
C65
4.7n
AEK-AUD-C1D9031
Schematic diagrams
page 7/10
DB4411 - Rev 1
Figure 7. AEK-AUD-C1D9031 circuit schematic (6 of 6)
PORST
JCOMP
TCK
TMS
TDI
TDO
CAN Interface
Vcc/IO
R55
N.M.
PORST
JCOMP
TCK
TMS
TDI
TDO
JTAG interface
R56
0R
+5V
CAN2_TX
R51
22R
R52
22R
C83 100n
CAN2_RX
1
2
3
4
U6
J6
TDI
TDO
TCK
J5
TXD
VSS
VDD
RXD
8
7
6
5
STBY
CANH
CANL
VIO
MCP2562FD-E_SN
CAN_H
CAN_L
Vcc/IO
C85
47p
C84
100n
C86
47p
R57
1
2
3
4
PORST
Vcc_uc
61900411121
120R
1
3
5
7
9
11
13
C88
33p
2
4
6
8
10
12
14
TMS
R62
10k
61201421621
JCOMP
S2
2
4
GND
GND
1
3
WS-TASV SMT Tact Switch 5x5mm
I2S Transceiver & Translation Level
+3V3
+5V
U7
1
VCC-A
VCC-B
T10
C82
100n
T12
2
A1
B1
7
T11
I2S_TEST(B)
0R
4
A2
GND
B2
DIR
SN74LVC2T45
DIR = 0 ==> IN = B
I2S_TEST(A)
6
5
C87
100n
I2S_TEST (B)
T13
3
R53
Vcc_fda
8
HW_MUTE (A)
1
2
3
R58
N.M.
S1
N.O._1
C_1
N.C._1
N.C._2
C_2
N.O._2
ESB-33535A
I2S_TEST (A)
R59
0R
4
5
6
HW_MUTE (B)
Vcc_fda
R60
R61
0R
N.M.
HW_MUTE
R54
0R
AEK-AUD-C1D9031
Schematic diagrams
page 8/10
AEK-AUD-C1D9031
Revision history
Table 1. Document revision history
DB4411 - Rev 1
Date
Version
04-Feb-2021
1
Changes
Initial release.
page 9/10
AEK-AUD-C1D9031
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DB4411 - Rev 1
page 10/10
