AEK-COM-BLEV1

AEK-COM-BLEV1 Data brief Bluetooth communication board based on BlueNRG-1 Features • • • • • • • • • • • • • Based on the BlueNRG-1 Bluetooth low energy system on chip Associated STSW-BLUENRG-DK (BlueNRG-1 development kit software package) including firmware and documentation Up to +8 dBm available output power (at antenna connector) Excellent receiver sensitivity (-88 dBm) Very low power consumption: 7.7 mA RX and 8.2 mA TX at +0 dBm Bluetooth® low energy compliant: supports master, slave and simultaneous master-and-slave roles New integrated balun BALF-NRG-02D3 which integrates a matching network and harmonics filter 3 user LEDs JTAG debug connector Pre-programmed as network processor Board size: 60 x 40 mm. Part of the AutoDevKit™ initiative RoHS and WEEE compliant Description The AEK-COM-BLEV1 evaluation board is based on the BlueNRG-1 low power Bluetooth® smart system on chip, compliant with the Bluetooth® specification. Product summary The evaluation board can be connected to a microcontroller via a 12-pin or alternative 9-pin male connector for SPI, serial interface or I²C communication. Bluetooth communication board based on the BlueNRG-1 AEK-COMBLEV1 Firmware for AEKCOM-BLEV1 testing The BlueNRG-1 device is supplied with the network processor software loaded and ready to process Bluetooth commands. The software image (DTM_UART.hex) is available in the BlueNRG design kit. STSW-AEKBLE Bluetooth® low energy system-on-chip BlueNRG-1 The STSW-AEKBLE firmware provides a straightforward demonstration of the AEKCOM-BLEV1 board functionality used in conjunction with the AEK-MCU-C4MLIT1 evaluation board with microcontroller. Setup for BlueNRG kits STSWBLUENRG-DK 50 Ω, conjugate match balun to BlueNRG transceiver, with integrated harmonic filter BALFNRG-02D3 Factory Automation Applications Bluetooth Low Energy Mobility Services DB4125 - Rev 1 - February 2020 For further information contact your local STMicroelectronics sales office. www.st.com AEK-COM-BLEV1 Loading firmware onto the BlueNRG-1 chip 1 Loading firmware onto the BlueNRG-1 chip Follow the procedure below to restore the factor firmware on the BlueNRG-1 device. 1.1 Hardware and software requirements • • • • • 1.2 DB4125 - Rev 1 ST-LINK/V2 programmer/debugger, which is connected through the evaluation board JTAG port STSW-LINK007 - ST-LINK/V2 firmware upgrade STSW-LINK009 - ST-LINK/V2 Windows driver STSW-BNRG1STLINK - ST-LINK utility required to burn the code in the BlueNRG-1 STSW-BLUENRG-DK - design kit containing the Flash image for the BlueNRG-1. After installing the design kit, go to the installation directory ([Firmware ]>[BLE_Examples]>[DTM]>[BlueNRG-1]) to find the “DTM_UART.hex” file Firmware burning procedure Step 1. Connect the ST-LINK/V2 to the PC via USB and to the AEK-COM-BLEV1 evaluation board JTAG port Step 2. Run the BlueNRG-1 ST-LINK Utility page 2/12 AEK-COM-BLEV1 Firmware burning procedure Step 3. From the top menu, select [Target]>[Settings] and ensure the following parameters are set: – Frequency: 4.0 MHz – Mode: Normal – Port: SWD Figure 1. BlueNRG-1 ST-LINK Utility settings DB4125 - Rev 1 Step 4. Press [OK] to confirm Step 5. From the main menu, select [Target]>[Connect] to connect the programmer The ST-LINK/V2 LED starts blinking Step 6. From main menu, select [Target]>[Program Verify] page 3/12 AEK-COM-BLEV1 Firmware burning procedure Step 7. Press [Browse] and select DTM_UART.hex from the disk to download it Figure 2. DTM_UART.hex file downloading DB4125 - Rev 1 page 4/12 AEK-COM-BLEV1 Firmware burning procedure Step 8. Press [Start] to Flash the image onto the BlueNRG-1 memory Figure 3. BlueNRG-1 ST LINK Utility device memory Step 9. DB4125 - Rev 1 From the main menu, select[]>[Target]>[Disconnect] to disconnect the programmer page 5/12 AEK-COM-BLEV1 Block diagram 2 Block diagram Figure 4. AEK-COM-BLEV1 block diagram DB4125 - Rev 1 page 6/12 DB4125 - Rev 1 3 Schematic diagrams Figure 5. AEK-COM-BLEV1 schematic diagram (1 of 4) C1 C2 100n_0402 1u_0402 D1 C3 VBLUE1 3 1 2 C4 150n_0402 RESETN C6 C5 I2C2_DAT I2C2_CLK DIO10 DIO9 DIO8 DIO7 DIO6 VBAT3 DIO5 DIO4 24 23 22 21 20 19 18 17 22p_0402 XTAL_LS VBAT1 33 GND VBAT1 SXTAL0 SXTAL1 RF0 RF1 VBAT2 FXTAL0 FXTAL1 Q1 U12 1 2 VBAT2 B1 B2 A1 A2 BALF-NRG-02D3 L3 4 3 J2 C12 C11 SMA connector Q2 C15 15p_0402 page 7/12 SPI_IN SPI_OUT SPI_CS SPI_CLK DIO14 C14 XTAL_HS L5 Schematic diagrams 15p_0402 AEK-COM-BLEV1 DIO3 DIO2 DIO1 DIO0 DIO14 TEST1 ADC1 ADC2 9 10 11 12 13 14 15 16 BlueNRG-1 1 2 3 4 5 6 7 8 DIO3 DIO2 DIO1 DIO0 ANATEST0/DIO14 ANATEST1 ADC1 ADC2 TXD DIO7 DIO6 JTMS-SWTDIO JTCK-SWTCK DIO8 DIO7 DIO6 VBAT3 DIO5 DIO4 DIO11 TEST DIO12 DIO13 VDD1V2 SMPSFILT2 SMPSFILT1 RESETN 32 DIO11 31 TEST 30 DIO12 29 DIO13 28 27 26 25 RESETN 22p_0402 U1 2nH_0402 L1 DIO12 DIO13 SPI_CS1/RXD 100p_0402 DB4125 - Rev 1 Figure 6. AEK-COM-BLEV1 schematic diagram (2 of 4) 2u2F-16V-0603 R24 VBLUE1 VBLUE 0R-1206 1 2 3 C22 1u_0402 Vin N.C. Vout 7 C26 R25 0R_0603 Vinh Gnd Bypass U3 C24 2u2_0402 1 +5V Gnd LDS3985PU33R JP1 6 5 4 C23 33n_0402 VBLUE 3 2 R28 470_0402 JP5 TEST R55 100k_0402 1 1 2 Jumper 2 2 VBLUE1 DL4 GREEN AEK-COM-BLEV1 Schematic diagrams page 8/12 DB4125 - Rev 1 Figure 7. AEK-COM-BLEV1 schematic diagram (3 of 4) CN2 +5V CN1 VBLUE +5V R1 TXD RESETN R2 R3 I2C2_DAT R4 I2C2_CLK R5 TP2 GND 3 4 0R0_0603 5 0R0_0603 6 0R0_0603 7 8 SPI_IN SPI_OUT R6 R7 SPI_CLK R8 SPI_CS R9 RESETN R10 5 6 0R0_0603 0R0_0603 7 0R0_0603 8 0R0_0603 9 V1 V2 V3 V4 0R0_0603 0R0_0603 RXD 0R0_0603 TXD 9 R6 R7 10 11 0R0_0603 12 0R0_0603 CN3 DIO6 DIO7 DIO12 DIO13 TP3 GND 3 4 1 2 RXD TP1 GND 1 2 R13 R15 R14 R16 0_0402 0_0402 0_0402 0_0402 1 2 3 4 5 Header 5 CN4 DIO14 TEST1 ADC1 ADC2 R17 R18 R19 R20 0_0402 0_0402 0_0402 0_0402 1 2 3 4 5 Header 5 AEK-COM-BLEV1 Schematic diagrams page 9/12 DB4125 - Rev 1 Figure 8. AEK-COM-BLEV1 schematic diagram (4 of 4) VBLUE JTAG VBLUE1 VBLUE1 VBAT1 Male Connector 2x10 HDR straight 1u_0402 VBAT3 VBAT2 C17 C16 VBLUE1 C18 C19 1u_0402 100n_0402 100n_0402 C20 100n_0402 1u_0402 VBLUE R26 100k_0402 RESETN R32 510_0402 R33 680_0402 R40 680_0402 C25 SWD ST Link: 3.0-3.6V, 5V tolerant IAR J-Link: 1.2-3.6V, 5V tolerant DIO7 DIO6 2 4 6 8 10 12 14 16 18 20 DIO14 CN7 1 3 5 DIO0 7 JTMS-SWTDIO 9 JTCK-SWTCK 11 13 DIO1 15 RESETN 17 19 C21 GND DL1 DL2 DL3 YELLOW RED BLUE 10n_0402 SW1 RESET GND R29 100_0402 AEK-COM-BLEV1 Schematic diagrams page 10/12 AEK-COM-BLEV1 Revision history Table 1. Document revision history DB4125 - Rev 1 Date Version 19-Feb-2020 1 Changes Initial release. page 11/12 AEK-COM-BLEV1 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DB4125 - Rev 1 page 12/12