AIS326DQ

AIS326DQ MEMS inertial sensor 3-axis, low g accelerometer with digital output Features ■ 3.3 V single supply operation ■ 1.8 V compatible IOs ■ SPI digital output interface ■ 12 bit resolution ■ Interrupt activated by motion ■ Programmable interrupt threshold ■ Embedded self-test ■ High shock survivability ■ ECOPACK® compliant ■ Extended temperature range -40 °C to +105 °C QFPN-28 Applications ■ Anti-theft systems and inertial navigation ■ Motion activated functions ■ Vibration monitoring and compensation ■ Tilt measurements ■ Black boxes, event recorders Description The AIS326DQ is a three axes digital output accelerometer that includes a sensing element and an IC interface able to take the information from the sensing element and to provide the measured acceleration signals to the external world through an SPI serial interface. I²C compatible interface is also available. process developed by ST to produce inertial sensors and actuators in silicon. The IC interface instead is manufactured using a CMOS process that allows high level of integration to design a dedicated circuit which is factory trimmed to better match the sensing element characteristics. The AIS326DQ has a user selectable full scale of ±2 g, ±6 g and it is capable of measuring acceleration over a bandwidth of 640 Hz for all axes. The device bandwidth may be selected accordingly to the application requirements. The self-test capability allows the user to check the functioning of the system. The device is available in plastic quad flat package no lead surface mount (QFPN) and it is specified over a temperature range extending from -40 °C to +105 °C. The sensing element, capable of detecting the acceleration, is manufactured using a dedicated Table 1. Device summary Order code Operating temperature range [° C] Package Packing AIS326DQ -40 to +105 QFPN-28 Tray AIS326DQTR -40 to +105 QFPN-28 Tape and reel June 2010 Doc ID 14956 Rev 4 1/51 www.st.com 51 Contents AIS326DQ Contents 1 2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 QFPN-28 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.1 3 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5.2 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5.3 Self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 Digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.1 SPI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.2 SPI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.3 SPI Read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2/51 7.1 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2 OFFSET_X (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Doc ID 14956 Rev 4 AIS326DQ 8 Contents 7.3 OFFSET_Y (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 OFFSET_Z (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.5 GAIN_X (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.6 GAIN_Y (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.7 GAIN_Z (1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.8 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.9 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.10 CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.11 HP_FILTER_RESET (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.12 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.13 OUTX_L (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.14 OUTX_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.15 OUTY_L (2Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.16 OUTY_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.17 OUTZ_L (2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.18 OUTZ_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.19 FF_WU_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.20 FF_WU_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.21 FF_WU_ACK (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.22 FF_WU_THS_L (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.23 FF_WU_THS_H (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.24 FF_WU_DURATION (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.25 DD_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.26 DD_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.27 DD_ACK (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.28 DD_THSI_L (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.29 DD_THSI_H (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.30 DD_THSE_L (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.31 DD_THSE_H (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1 Mechanical characteristics at 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.2 Mechanical characteristics at -40 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Doc ID 14956 Rev 4 3/51 Contents 9 AIS326DQ 8.3 Mechanical characteristics at 105 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.4 Mechanical characteristics derived from measurement in the -40 °C to +105 °C temperature range 43 8.5 Electro-mechanical characteristics at 25 °C . . . . . . . . . . . . . . . . . . . . . . . 44 8.6 Electrical characteristics at 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.7 Electrical characteristics at -40 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.8 Electrical characteristics at 105 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1 General guidelines about soldering surface mount accelerometer . . . . . 46 9.2 PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.2.1 PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.3 Stencil design and solder paste application . . . . . . . . . . . . . . . . . . . . . . . 47 9.4 Process consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4/51 Doc ID 14956 Rev 4 AIS326DQ List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Mechanical characteristics @ Vdd = 3.3 V, T = -40 °C to 105 °C unless otherwise noted. . 7 Electrical characteristics @ Vdd=3.3 V, T = -40 °C to 105 °C unless otherwise noted . . . . 9 SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Registers address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 OFFSET_X register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 OFFSET_X register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 OFFSET_Y register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 OFFSET_Y register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 OFFSET_Z register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 OFFSET_Z register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 GAIN_X register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 GAIN_X register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 GAIN_Y register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 GAIN_Y register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 GAIN_Z register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 GAIN_Z register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CTRL_REG1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CTRL_REG2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CTRL_REG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CTRL_REG3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STATUS_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OUTX_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OUTX_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OUTX_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 OUTX_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 OUTY_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 OUTY_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 OUTY_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 OUTY_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 OUTZ_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 OUTZ_L register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 OUTZ_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 OUTZ_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FF_WU_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FF_WU_CFG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FF_WU_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FF_WU_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FF_WU_THS_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FF_WU_THS_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Doc ID 14956 Rev 4 5/51 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. 6/51 AIS326DQ FF_WU_THS_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FF_WU_THS_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FF_WU_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 FF_WU_DURATION register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DD_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DD_CFG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DD_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DD_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DD_THSI_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DD_THSI_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DD_THSI_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DD_THSI_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DD_THSE_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DD_THSE_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DD_THSE_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DD_THSE_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Doc ID 14956 Rev 4 AIS326DQ List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SPI slave timing diagram (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 AIS326DQ electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI Write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 X-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 X-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Y-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Y-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Z-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Z-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 X-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 X-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Y-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Y-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Z-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Z-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 X-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 X-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Y-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Y-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Z-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Z-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 X-axis zero-g level change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 X-axis sensitivity change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Y-axis zero-g level change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Y-axis sensitivity change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Z-axis zero-g level change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Z-axis sensitivity change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 X and Y axes zero-g level as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 40 X and Y axes sensitivity as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Z axis zero-g level as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Z axis sensitivity as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Current consumption in power-down mode (Vdd=3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Current consumption in operational mode (Vdd=3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Current consumption in power-down mode (Vdd=3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Current consumption in operational mode (Vdd=3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Current consumption in power-down mode (Vdd=3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Current consumption in operational mode (Vdd=3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Recommended land and solder mask design for QFPN packages . . . . . . . . . . . . . . . . . . 43 QFPN-28 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Doc ID 14956 Rev 4 7/51 Block diagram and pin description AIS326DQ 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram X+ Y+ Z+ a DE MUX MUX Reconstruction Σ∆ CHARGE AMPLIFIER Filter Reconstruction Σ∆ Regs Array Filter Z- SELF TEST REFERENCE Filter TRIMMING CIRCUITS CONTROL LOGIC & INTERRUPT GEN. CLOCK QFPN-28 pin description 28 Z NC NC NC NC NC NC Pin connection NC Figure 2. SDO/SDI Reconstruction Σ∆ X- 22 NC 1 1 Y 21 NC GND Reserved Vdd X Vdd AIS326DQ Reserved Reserved (TOP VIEW) GND GND RDY/INT CK 15 NC NC 7 Doc ID 14956 Rev 4 NC CS SPC Vdd_IO 14 SDI/SDO NC 8 SDO DIRECTIONS OF THE DETECTABLE ACCELERATIONS 8/51 SPC SPI SDO Y- 1.2 CS RDY/INT AIS326DQ Block diagram and pin description Table 2. Pin description Pin# Name Function 1 NC 2 GND 0 V supply 3 Vdd Power supply 4 Reserved 5 GND 6 RDY/INT 7, 8 NC 9 SDO SPI serial data output 10 SDI/ SDO SPI serial data input (SDI) 3-wire interface serial data output (SDO) 11 Vdd_IO 12 SPC 13 CS Chip select (logic 0: SPI enabled, logic 1: SPI disabled) 14, 15 NC Internally not connected 16 CK Optional external clock, if not used either leave unconnected or connect to GND 17 GND 18 Reserved 19 Vdd 20 Reserved 21 - 28 NC Internally not connected Either leave unconnected or connect to GND 0 V supply Data ready/inertial wake-up and free-fall interrupt Internally not connected Power supply for I/O pads SPI serial port clock 0 V supply Either leave unconnected or connect to Vdd_IO Power supply Connect to Vdd Internally not connected Doc ID 14956 Rev 4 9/51 Mechanical and electrical specifications AIS326DQ 2 Mechanical and electrical specifications 2.1 Mechanical characteristics Table 3. Mechanical characteristics @ Vdd = 3.3 V, T = -40 °C to 105 °C unless otherwise noted(1) Symbol FS Dres Parameter Measurement range(3) Device resolution Min. Typ.(2) FS bit set to 0 ±1.7 ±2.0 FS bit set to 1 ±5.3 ±6.0 Test conditions TCSo Off TCOff NL CrAx 10/51 Sensitivity Sensitivity change vs temperature Zero-g level offset accuracy(5),(6) Zero-g level change vs temperature Non linearity(4) Unit g Full-scale = ±2 g T = 25 °C, ODR1=40 Hz 1.0 Full-scale = ±2 g T = 25 °C, ODR2=160 Hz 2.0 mg Full-scale = ±2 g T = 25 °C, ODR3 = 640 Hz 3.9 Full-scale = ±2 g T = 25 °C, ODR4 = 2560 Hz 15.6 Full-scale = ±2 g 12 bit representation So Max. Full-scale = ±6 g 12 bit representation(4) 952 1024 1096 LSb/g 316 Full-scale = ±2 g 12 bit representation 340 364 0.025 %/°C Full-scale = ±2 g X, Y axis -100 100 Full-scale = ±2 g Z axis -200 200 Full-scale = ±6 g X, Y axis(4) -100 100 Full-scale = ±6 g Z axis(4) -200 200 mg Max delta from 25 °C 0.2 Best fit straight line X, Y axis Full-scale = ±2 g ODR = 40 Hz ±2 % FS Best fit straight line Z axis Full-scale = ±2 g ODR = 40 Hz Cross axis(4) ±3 -5 Doc ID 14956 Rev 4 mg/°C 5 % AIS326DQ Table 3. Symbol Vst Mechanical and electrical specifications Mechanical characteristics @ Vdd = 3.3 V, T = -40 °C to 105 °C unless otherwise noted(1) (continued) Min. Typ.(2) Max. Full-scale= ±2 g X axis 200 460 750 Full-scale= ±2 g Y axis 200 460 750 Full-scale= ±2 g Z axis 140 360 580 Full-scale= ±6 g X axis 60 160 260 Full-scale= ±6 g Y axis 60 160 260 Full-scale= ±6 g Z axis 45 120 200 Parameter Test conditions (7),(8) Self-test output change BW System bandwidth(9) TOP Operating temperature range Wh Product weight ODRx/4 -40 Unit LSb LSb Hz +105 0.2 °C gram 1. The product is factory calibrated at 3.3 V. Operation over 3.6 V is not recommended 2. Typical specifications are not guaranteed 3. Verified by wafer level test and specification of initial offset and sensitivity 4. Guaranteed by design 5. Zero-g level offset value after MSL3 preconditioning 6. Offset can be eliminated by enabling the built-in high pass filter (HPF) 7. Self test output changes with the power supply. “Self-test output change” is defined as OUTPUT[LSb](Self-test bit on CTRL_REG1=1) - OUTPUT[LSb](Self-test bit on CTRL_REG1=0). 1LSb = 1g/1024 at 12 bit representation, 2 g Full-scale 8. Output data reach 99% of final value after 5/ODR when enabling Self-test mode due to device filtering 9. ODRx is output data rate. Refer to Table 4 for specifications Doc ID 14956 Rev 4 11/51 Mechanical and electrical specifications AIS326DQ 2.2 Electrical characteristics Table 4. Electrical characteristics @ Vdd=3.3 V, T = -40 °C to 105 °C unless otherwise noted(1) Symbol Vdd Vdd_IO Idd IddPdn VIH VIL Parameter Test conditions Supply voltage (3) I/O pads supply voltage Min. Typ.(2) Max. Unit 3.0 3.3 3.6 V Vdd V 0.67 0.80 mA 2 20 µA 1.71 Supply current Vdd = 3.3 V Current consumption in power-down mode Digital high level Input voltage(3) 0.8*Vdd_IO V (3) 0.2*Vdd_IO Digital low level Input voltage VOH High level output voltage(3) VOL Low level output voltage(3) 0.9*Vdd_IO V 0.1*Vdd_IO ODR1 Output data rate 1 Dec factor = 512 40 ODR2 Output data rate 2 Dec factor = 128 160 ODR3 Output data rate 3 Dec factor = 32 640 ODR4 Output data rate 4 Dec factor = 8 2560 Hz BW (4) System bandwidth (5) Ton Turn-on time TOP Operating temperature range -40 1. The product is factory calibrated at 3.3 V. Operation over 3.6 V is not recommended 2. Typical specifications are not guaranteed 3. Guaranteed by design 4. Digital filter -3 dB frequency 5. Time to obtain valid data after exiting power-down mode 12/51 Doc ID 14956 Rev 4 ODRx/4 Hz 5/ODRx s +105 °C AIS326DQ Mechanical and electrical specifications 2.3 Communication interface characteristics 2.3.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and TOP. Table 5. SPI slave timing values Value(1) Symbol Parameter Unit Min tc(SPC) SPI clock cycle fc(SPC) SPI clock frequency tsu(CS) CS setup time 5 th(CS) CS hold time 10 tsu(SI) SDI input setup time 5 th(SI) SDI input hold time 15 tv(SO) SDO valid output time th(SO) SDO output hold time tdis(SO) Max 125 ns 8 MHz ns 55 7 SDO output disable time 50 1. Values are guaranteed at 8 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production SPI slave timing diagram (2) Figure 3. CS (3) (3) tc(SPC) tsu(CS) SPC (3) (3) tsu(SI) SDI (3) th(SI) LSB IN MSB IN tv(SO) SDO th(CS) (3) MSB OUT (3) tdis(SO) th(SO) LSB OUT (3) 2. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output port 3. When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors Doc ID 14956 Rev 4 13/51 Mechanical and electrical specifications 2.4 AIS326DQ Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 6. Absolute maximum ratings Symbol Vdd Vdd_IO Vin Ratings Supply voltage(1) (1) I/O pins supply voltage Input voltage on any control pin(1) (CS, SPC, SDI/SDO, SDO, CK) Maximum value Unit -0.3 to 6.0 V -0.3 to Vdd +0.1 V -0.3 to Vdd_IO +0.3 V 3000 g for 0.5 ms APOW Acceleration (any axis, powered, Vdd = 3.3 V) AUNP Acceleration (any axis, unpowered) TOP Operating temperature range -40 to +105 °C TSTG Storage temperature range -40 to +125 °C 4.0 (HBM) kV 200 (MM) V 1.5 (CDM) kV 10000 g for 0.1 ms 3000 g for 0.5 ms ESD Electrostatic discharge protection 10000 g for 0.1 ms 1. Supply voltage on any pin should never exceed 6.0 V. This is a mechanical shock sensitive device, improper handling can cause permanent damages to the part. This is an ESD sensitive device, improper handling can cause permanent damages to the part. 14/51 Doc ID 14956 Rev 4 AIS326DQ Mechanical and electrical specifications 2.5 Terminology 2.5.1 Sensitivity Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (point to the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and also very little over time. The Sensitivity tolerance describes the range of sensitivities of a large population of sensors. 2.5.2 Zero-g level Zero-g level offset (Off) describes the deviation of an actual output signal from the ideal output signal if there is no acceleration present. A sensor in a steady state on a horizontal surface will measure 0 g in X axis and 0 g in Y axis whereas the Z axis will measure 1 g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, 00h with 16 bit representation, data expressed as 2’s complement number). A deviation from ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress to a precise MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Zero-g level change vs. temperature”. The Zero-g level of an individual sensor is stable over lifetime. The Zero-g level tolerance describes the range of Zero-g levels of a population of sensors. 2.5.3 Self test Self test allows to test the mechanical and electric part of the sensor, allowing the seismic mass to be moved by means of an electrostatic test-force. The self-test function is off when the self-test bit of CTRL_REG1 (control register 1) is programmed to ‘0‘. When the self-test bit of CTRL_REG1 is programmed to ‘1‘an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs will exhibit a change in their DC levels which is related to the selected full scale and depending on the Supply Voltage through the device sensitivity. When Self Test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified inside Table 3 or 4 then the sensor is working properly and the parameters of the interface chip are within the defined specification. Doc ID 14956 Rev 4 15/51 Functionality 3 AIS326DQ Functionality The AIS326DQ is a high performance, low-power, digital output 3-axes linear accelerometer packaged in a QFN package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide a signal to the external world through an SPI serial interface. 3.1 Sensing element A proprietary process is used to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the sense capacitor. At steady state the nominal value of the capacitors are few pF and when an acceleration is applied the maximum variation of the capacitive load is up to 100 pF. 3.2 IC interface The complete measurement chain is composed by a low-noise capacitive amplifier which converts into an analog voltage the capacitive unbalancing of the MEMS sensor and by three Σ∆ analog-to-digital converters, one for each axis, that translate the produced signal into a digital bitstream. The Σ∆ converters are coupled with dedicated reconstruction filters which remove the high frequency components of the quantization noise and provide low rate and high resolution digital words. The charge amplifier and the Σ∆ converters are operated respectively at 61.5 kHz and 20.5 kHz. The data rate at the output of the reconstruction depends on the user selected decimation factor (DF) and spans from 40 Hz to 2560 Hz. The acceleration data may be accessed through an SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller. The AIS326DQ features a data-ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in digital system employing the device itself. The AIS326DQ may also be configured to generate an inertial wake-up, direction detection and free-fall interrupt signal accordingly to a programmed acceleration event along the enabled axes. 16/51 Doc ID 14956 Rev 4 AIS326DQ 3.3 Functionality Factory calibration The IC interface is factory calibrated for sensitivity (So) and Zero-g level (Off). The trimming values are stored inside the device by a non volatile structure. Any time the device is turned on, the trimming parameters are downloaded into the registers to be employed during the normal operation. This allows the user to employ the device without further calibration. Doc ID 14956 Rev 4 17/51 Application hints 4 AIS326DQ Application hints Figure 4. AIS326DQ electrical connection 28 Z 22 1 Y 1 21 AIS326DQ 10uF X (TOP VIEW) 7 100nF 15 8 14 DIRECTIONS OF THE DETECTABLE ACCELERATIONS CS SPC SDO RDY/INT Vdd SDI/SDO Vdd_IO GND Digital signal from/to signal controller. Signal’s levels are defined by proper selection of Vdd_IO The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Al) should be placed as near as possible to the pin 3 of the device (common design practice). All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to Figure 4). It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses. In this condition the measurement chain is powered off. The functionality of the device and the measured acceleration data is selectable and accessible through the SPI interface. The design of the application board should take in consideration that the AIS326DQ is equipped also with an I2C compatible interface that it is activated when the signal on CS pin is high (logic:1). The functions, the thresholds and the timing of the interrupt pin (INT) can be completely programmed by the user through the SPI interface. 18/51 Doc ID 14956 Rev 4 AIS326DQ 5 Digital interface Digital interface The registers embedded inside the AIS326DQ may be accessed through SPI serial interface. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. Table 7. Serial interface pin description Pin name CS Chip select (logic 0: SPI enabled, logic 1: SPI disabled) SPC SPI serial port clock SDI/SDO SDO Pin description SPI serial data input (SDI) 3-wire interface serial data output (SDO) SPI serial data output (SDO) The embedded registers may be accessed also through an I2C interface. For I2C operation refer to LIS3LV02DQ datasheet or contact ST technical support. 5.1 SPI bus interface The AIS326DQ SPI is a bus slave. The SPI allows to write and read the registers of the device. The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. Figure 5. Read and write protocol CS SPC SDI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 RW MS AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the Serial Port Clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. Both the read register and write register commands are completed in 16 clock pulses or in multiple of 8 in case of multiple byte read/write. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge Doc ID 14956 Rev 4 19/51 Digital interface AIS326DQ of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS. bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands. When 1, the address will be auto increased in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). In multiple read/write commands further blocks of 8 clock periods will be added. When MS bit is 0 the address used to read/write data remains the same for every block. When MS bit is ‘1’ the address used to read/write data is increased at every block. The function and the behavior of SDI and SDO remain unchanged. 5.1.1 SPI Read Figure 6. SPI read protocol CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 The SPI Read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). bit 16-... : data DO(...-8). Further data in multiple byte reading. 20/51 Doc ID 14956 Rev 4 AIS326DQ Digital interface Figure 7. Multiple bytes SPI read protocol (2 bytes example) CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15DO14DO13DO12DO11DO10DO9 DO8 5.1.2 SPI Write Figure 8. SPI Write protocol CS SPC SDI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 RW MS AD5 AD4 AD3 AD2 AD1 AD0 The SPI Write command is performed with 16 clock pulses. Multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0: WRITE bit. The value is 0. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple writing. bit 2 -7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device (MSb first). bit 16-... : data DI(...-8). Further data in multiple byte writing. Figure 9. Multiple bytes SPI write protocol (2 bytes example) CS SPC SDI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 RW MS AD5 AD4 AD3 AD2 AD1 AD0 Doc ID 14956 Rev 4 21/51 Digital interface 5.1.3 AIS326DQ SPI Read in 3-wires mode 3-wires mode is entered by setting to ‘1’ bit SIM (SPI serial interface mode selection) in CTRL_REG2. Figure 10. SPI read protocol in 3-wires mode CS SPC SDI/O DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 RW MS AD5 AD4 AD3 AD2 AD1 AD0 The SPI read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). Multiple read command is also available in 3-wires mode. 22/51 Doc ID 14956 Rev 4 AIS326DQ 6 Register mapping Register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related address. Table 8. Registers address map Register address Register name Type Default Binary Comment Hex rw 0000000 - 0001110 00 - 0E r 0001111 rw 0010000 - 0010101 10 - 15 OFFSET_X rw 0010110 16 Calibration Loaded at boot OFFSET_Y rw 0010111 17 Calibration Loaded at boot OFFSET_Z rw 0011000 18 Calibration Loaded at boot GAIN_X rw 0011001 19 Calibration Loaded at boot GAIN_Y rw 0011010 1A Calibration Loaded at boot GAIN_Z rw 0011011 1B Calibration Loaded at boot WHO_AM_I 0F Reserved 00111010 Reserved 0011100 -0011111 1C-1F Reserved CTRL_REG1 rw 0100000 20 00000111 CTRL_REG2 rw 0100001 21 00000000 CTRL_REG3 rw 0100010 22 00001000 0100011 23 dummy 0100100-0100110 24-26 HP_FILTER RESET r Dummy register Dummy register Not used STATUS_REG rw 0100111 27 00000000 OUTX_L r 0101000 28 output OUTX_H r 0101001 29 output OUTY_L r 0101010 2A output OUTY_H r 0101011 2B output OUTZ_L r 0101100 2C output OUTZ_H r 0101101 2D output r 0101110 2E Reserved 0101111 2F Not used FF_WU_CFG rw 0110000 30 00000000 FF_WU_SRC rw 0110001 31 00000000 FF_WU_ACK r 0110010 32 dummy 0110011 33 0110100 34 FF_WU_THS_L rw Doc ID 14956 Rev 4 Dummy register Not used 00000000 23/51 Register mapping Table 8. AIS326DQ Registers address map (continued) Register address Register name Type Default Binary FF_WU_THS_H Comment Hex rw 0110101 35 00000000 FF_WU_DURATION rw 0110110 36 00000000 0110111 37 Not used DD_CFG rw 0111000 38 00000000 DD_SRC rw 0111001 39 00000000 DD_ACK r 0111010 3A dummy 0111011 3B Dummy register Not used DD_THSI_L rw 0111100 3C 00000000 DD_THSI_H rw 0111101 3D 00000000 DD_THSE_L rw 0111110 3E 00000000 DD_THSE_H rw 0111111 3F 00000000 1000000-1111111 40-7F Reserved Registers marked as Reserved must not be changed. The writing to those registers may cause permanent damages to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up. 24/51 Doc ID 14956 Rev 4 AIS326DQ 7 Register description Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers 7.2 to 7.7 contain the factory calibration values, it is not necessary to change their value for normal device operation. 7.1 WHO_AM_I (0Fh) Table 9. W7 Table 10. W7, W0 Register W6 W5 W4 W3 W2 W1 W0 Register description AIS326DQ physical address equal to 3Ah Addressing this register the physical address of the device is returned. For AIS326DQ the physical address assigned in factory is 3Ah. 7.2 OFFSET_X (16h) Table 11. OX7 Table 12. OX7, OX0 7.3 OFFSET_X register OX6 OX5 OX4 OX3 OX2 OX1 OX0 OY3 OY2 OY1 OY0 OFFSET_X register description Digital offset trimming for X-Axis OFFSET_Y (17h) Table 13. OY7 Table 14. OY7, OY0 OFFSET_Y register OY6 OY5 OY4 OFFSET_Y register description Digital offset trimming for Y-Axis Doc ID 14956 Rev 4 25/51 Register description 7.4 OFFSET_Z (18h) Table 15. OZ7 Table 16. OZ7, OZ0 7.5 GX7 Table 18. GX7, GX0 GY7 OZ5 OZ4 OZ3 OZ2 OZ1 OZ0 GX3 GX2 GX1 GX0 GY3 GY2 GY1 GY0 GZ3 GZ2 GZ1 GZ0 OFFSET_Z register description Digital offset trimming for Z-Axis GAIN_X register GX6 GX5 GX4 GAIN_X register description Digital gain trimming for X-Axis GAIN_Y register GY6 GY5 GY4 Table 20. GAIN_Y register description GY7, GY0 Digital gain trimming for Y-Axis GAIN_Z (1Bh) Table 21. GZ7 Table 22. GZ7, GZ0 26/51 OZ6 GAIN_Y (1Ah) Table 19. 7.7 OFFSET_Z register GAIN_X (19h) Table 17. 7.6 AIS326DQ GAIN_Z register GZ6 GZ5 GZ4 GAIN_Z register description Digital gain trimming for Z-Axis Doc ID 14956 Rev 4 AIS326DQ 7.8 Register description CTRL_REG1 (20h) Table 23. PD1 Table 24. CTRL_REG1 register PD0 DF1 DF0 ST Zen Yen Xen CTRL_REG1 register description PD1, PD0 Power down control (00: power-down mode; 01, 10, 11: device on) DF1, DF0 Decimation factor control (00: decimate by 512; 01: decimate by 128; 10: decimate by 32; 11: decimate by 8) ST Self test enable (0: normal mode; 1: self-test active) Zen Z-axis enable (0: axis off; 1: axis on) Yen Y-axis enable (0: axis off; 1: axis on) Xen X-axis enable (0: axis off; 1: axis on) PD1, PD0 bit allows to turn the device out of power-down mode. The device is in powerdown mode when PD1, PD0= “00” (default value after boot). The device is in normal mode when either PD1 or PD0 is set to 1. DF1, DF0 bit allows to select the data rate at which acceleration samples are produced. The default value is “00” which corresponds to a data-rate of 40 Hz. By changing the content of DF1, DF0 to “01”, “10” and “11” the selected data-rate will be set respectively equal to 160 Hz, 640 Hz and to 2560 Hz. ST bit is used to activate the self test function. When the bit is set to one, an output change will occur to the device outputs (refer to table 2 and 3 for specification) thus allowing to check the functionality of the whole measurement chain. Zen bit enables the Z-axis measurement channel when set to 1. The default value is 1. Yen bit enables the Y-axis measurement channel when set to 1. The default value is 1. Xen bit enables the X-axis measurement channel when set to 1. The default value is 1. 7.9 CTRL_REG2 (21h) Table 25. FS CTRL_REG2 register BDU BLE BOOT Doc ID 14956 Rev 4 IEN DRDY SIM DAS 27/51 Register description Table 26. AIS326DQ CTRL_REG2 register description FS Full scale selection (0: ±2 g; 1: ±6 g) BDU Block data update (0: continuous update; 1: output registers not updated between MSB and LSB reading) BLE Big/little endian selection (0: little endian; 1: big endian) BOOT Reboot memory content IEN Interrupt ENable (0: data ready on RDY pad; 1: interrupt events on RDY pad) DRDY Enable data-ready generation SIM SPI serial interface mode selection (0: 4-wire interface; 1: 3-wire interface) DAS Data alignment selection (0: 12 bit right justified; 1: 16 bit left justified) FS bit is used to select full scale value. After the device power-up the default full scale value is +/-2 g. In order to obtain a +/-6 g full scale it is necessary to set FS bit to ‘1’. BDU bit is used to inhibit output registers update between the reading of upper and lower register parts. In default mode (BDU = ‘0’) the lower and upper register parts are updated continuously. If it is not sure to read faster than output data rate, it is recommended to set BDU bit to ‘1’. In this way, after the reading of the lower (upper) register part, the content of that output registers is not updated until the upper (lower) part is read too. This feature avoids reading LSB and MSB related to different samples. BLE bit is used to select Big Endian or Little Endian representation for output registers. In Big Endian’s one MSB acceleration value is located at addresses 28h (X-axis), 2Ah (Y-axis) and 2Ch (Z-axis) while LSB acceleration value is located at addresses 29h (X-axis), 2Bh (Yaxis) and 2Dh (Z-axis). In Little Endian representation (Default, BLE=‘0‘) the order is inverted (refer to data register description for more details). BOOT bit is used to refresh the content of internal registers stored in the flash memory block. At the device power up the content of the flash memory block is transferred to the internal registers related to trimming functions to permit a good behavior of the device itself. If for any reason the content of trimming registers was changed it is sufficient to use this bit to restore correct values. When BOOT bit is set to ‘1’ the content of internal flash is copied inside corresponding internal registers and it is used to calibrate the device. These values are factory trimmed and they are different for every accelerometer. They permit a good behavior of the device and normally they have not to be changed. At the end of the boot process the BOOT bit is set again to ‘0’. IEN bit is used to switch the value present on data-ready pad between Data-Ready signal and Interrupt signal. At power up the Data-ready signal is chosen. It is however necessary to modify DRDY bit to enable Data-Ready signal generation. 28/51 Doc ID 14956 Rev 4 AIS326DQ Register description DRDY bit is used to enable Data-Ready (RDY/INT) pin activation. If DRDY bit is ‘0’ (default value) on Data-Ready pad a ‘0’ value is present. If a Data-Ready signal is desired it is necessary to set to ‘1’ DRDY bit. Data-Ready signal goes to ‘1’ whenever a new data is available for all the enabled axis. For example if Z-axis is disabled, Data-Ready signal goes to ‘1’ when new values are available for both X and Y axis. Data-Ready signal comes back to ‘0’ when all the registers containing values of the enabled axis are read. To be sure not to loose any data coming from the accelerometer data registers must be read before a new Data-Ready rising edge is generated. In this case Data-ready signal will have the same frequency of the data rate chosen. SIM bit selects the SPI Serial Interface Mode. When SIM is ‘0’ (default value) the 4-wire interface mode is selected. The data coming from the device are sent to SDO pad. In 3-wire interface mode output data are sent to SDA/SDI pad. DAS bit permits to decide between 12 bit right justified and 16 bit left justified representation of data coming from the device. The first case is the default case and the most significant bits are replaced by the bit representing the sign. 7.10 CTRL_REG3 (22h) Table 27. ECK Table 28. CTRL_REG3 register HPDD HPFF FDS res res CFS1 CFS0 CTRL_REG3 register description ECK External Clock. Default value: 0 (0: clock from internal oscillator; 1: clock from external pad) HPDD High Pass filter enabled for Direction Detection. Default value: 0 (0: filter bypassed; 1: filter enabled) HPFF High Pass filter enabled for Free-Fall and Wake-Up. Default value: 0 (0: filter bypassed; 1: filter enabled) FDS Filtered Data Selection. Default value: 0 (0: internal filter bypassed; 1: data from internal filter) CFS1, CFS0 High-pass filter Cut-off Frequency Selection. Default value: 00 (00: Hpc=512 01: Hpc=1024 10: Hpc=2048 11: Hpc=4096) FDS bit enables (FDS=1) or bypass (FDS=0) the high pass filter in the signal chain of the sensor. Doc ID 14956 Rev 4 29/51 Register description AIS326DQ CFS1, CFS0 bits defines the coefficient Hpc to be used to calculate the -3dB cut-off frequency of the high pass filter: 0.318 ODRx f cutoff = --------------- ⋅ ----------------Hpc 2 7.11 HP_FILTER_RESET (23h) Dummy register. Reading at this address zeroes instantaneously the content of the internal high pass-filter. Read data is not significant. 7.12 STATUS_REG (27h) Table 29. ZYXOR Table 30. STATUS_REG register ZOR YOR XOR ZYXDA ZDA YDA XDA STATUS_REG register description ZYXOR X, Y and Z axis data overrun ZOR Z axis data overrun YOR Y axis data overrun XOR X axis data overrun ZYXDA X, Y and Z axis new data available ZDA Z axis new data available YDA Y axis new data available XDA X axis new data available The content of this register is updated every ODR cycle, regardless of BDU bit value in CTRL_REG2. 7.13 OUTX_L (28h) Table 31. XD7 Table 32. XD7, XD0 30/51 OUTX_L register XD6 XD5 XD4 OUTX_L register description X axis acceleration data LSB Doc ID 14956 Rev 4 XD3 XD2 XD1 XD0 AIS326DQ Register description In big endian mode (bit BLE in CTRL_REG2 set to ‘1’) the content of this register is the MSB acceleration data and depends on bit DAS in CTRL_REG2 register as described in the following section. 7.14 OUTX_H (29h) Table 33. XD15 Table 34. XD15, XD8 OUTX_H register XD14 XD13 XD12 XD11 XD10 XD9 XD8 OUTX_H register description X axis acceleration data MSB When reading the register in “12 bit right justified” mode the most significant bits (15:12) are replaced with bit 11 (i.e. XD15-XD12=XD11, XD11, XD11, XD11). In big endian mode (bit BLE in CTRL_REG2 set to ‘1’) the content of this register is the LSB acceleration data. 7.15 OUTY_L (2Ah) Table 35. YD7 Table 36. YD7, YD0 OUTY_L register YD6 YD5 YD4 YD3 YD2 YD1 YD0 OUTY_L register description Y axis acceleration data LSB In big endian mode (bit BLE in CTRL_REG2 set to ‘1’) the content of this register is the MSB acceleration data and depends on bit DAS in CTRL_REG2 register as described in the following section. 7.16 OUTY_H (2Bh) Table 37. YD15 Table 38. YD15, YD8 OUTY_H register YD14 YD13 YD12 YD11 YD10 YD9 YD8 OUTY_H register description Y axis acceleration data MSB Doc ID 14956 Rev 4 31/51 Register description AIS326DQ When reading the register in “12 bit right justified” mode the most significant bits (15:12) are replaced with bit 11 (i.e. YD15-YD12=YD11, YD11, YD11, YD11). In big endian mode (bit BLE in CTRL_REG2 set to ‘1’) the content of this register is the LSB acceleration data. 7.17 OUTZ_L (2Ch) Table 39. ZD7 Table 40. ZD7, ZD0 OUTZ_L register ZD6 ZD5 ZD4 ZD3 ZD2 ZD1 ZD0 OUTZ_L register description Z axis acceleration data LSB In big endian mode (bit BLE in CTRL_REG2 set to ‘1’) the content of this register is the MSB acceleration data and depends on bit DAS in CTRL_REG2 register as described in the following section. 7.18 OUTZ_H (2Dh) Table 41. ZD15 Table 42. ZD15, ZD8 OUTZ_H register ZD14 ZD13 ZD12 ZD11 ZD10 ZD9 ZD8 OUTZ_H register description Z axis acceleration data MSB When reading the register in “12 bit right justified” mode the most significant bits (15:12) are replaced with bit 11 (i.e. ZD15-ZD12=ZD11, ZD11, ZD11, ZD11). In big endian mode (bit BLE in CTRL_REG2 set to ‘1’) the content of this register is the LSB acceleration data. 32/51 Doc ID 14956 Rev 4 AIS326DQ 7.19 Register description FF_WU_CFG (30h) Table 43. AOI Table 44. FF_WU_CFG register LIR ZHIE ZLIE YHIE YLIE XHIE XLIE FF_WU_CFG register description AOI And/Or combination of Interrupt events. Default value: 0. (0: OR combination of interrupt events; 1: AND combination of interrupt events) LIR Latch interrupt request. Default value: 0. (0: interrupt request not latched; 1: interrupt request latched) ZHIE Enable Interrupt request on Z High event. Default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ZLIE Enable Interrupt request on Z Low event. Default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) YHIE Enable Interrupt request on Y High event. Default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) YLIE Enable Interrupt request on Y Low event. Default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) XHIE Enable Interrupt request on X High event. Default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) XLIE Enable Interrupt request on X Low event. Default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Free-fall and inertial wake-up configuration register. Doc ID 14956 Rev 4 33/51 Register description 7.20 FF_WU_SRC (31h) Table 45. X Table 46. 7.21 AIS326DQ FF_WU_SRC register IA ZH ZL YH YL XH XL FF_WU_SRC register description IA Interrupt Active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) ZH Z High. Default value: 0 (0: no interrupt; 1: Z High event has occurred) ZL Z Low. Default value: 0 (0: no interrupt; 1: Z Low event has occurred) YH Y High. Default value: 0 (0: no interrupt; 1: Y High event has occurred) YL Y Low. Default value: 0 (0: no interrupt; 1: Y Low event has occurred) XH X High. Default value: 0 (0: no interrupt; 1: X High event has occurred) XL X Low. Default value: 0 (0: no interrupt; 1: X Low event has occurred) FF_WU_ACK (32h) Dummy register. If LIR bit in FF_WU_CFG register is set to ‘1’, a reading at this address refreshes the FF_WU_SRC register. Read data is not significant. 7.22 FF_WU_THS_L (34h) Table 47. THS7 Table 48. THS7, THS0 7.23 THS6 THS5 THS4 THS3 THS2 THS1 THS0 THS9 THS8 FF_WU_THS_L register description Free-fall / inertial wake up acceleration threshold LSB FF_WU_THS_H (35h) Table 49. THS15 34/51 FF_WU_THS_L register FF_WU_THS_H register THS14 THS13 THS12 THS11 Doc ID 14956 Rev 4 THS10 AIS326DQ Register description Table 50. FF_WU_THS_H register description THS15, THS8 Free-fall / inertial wake up acceleration threshold MSB Doc ID 14956 Rev 4 35/51 Register description 7.24 AIS326DQ FF_WU_DURATION (36h) Table 51. FF_WU_DURATION register FWD7 Table 52. FWD6 FWD5 FWD4 FWD3 FWD2 FWD1 FWD0 FF_WU_DURATION register description FWD7, FWD0 Minimum duration of the Free-fall/Wake-up event This register sets the minimum duration of the free-fall/wake-up event to be recognized. FF_WU_DURATION (Dec) Duration ( s ) = -----------------------------------------------------------------------ODR 7.25 DD_CFG (38h) Table 53. IEND Table 54. 36/51 DD_CFG register LIR ZHIE ZLIE YHIE YLIE XHIE XLIE DD_CFG register description IEND Interrupt enable on direction change. Default value: 0 (0: disabled; 1: interrupt signal enabled) LIR Latch Interrupt request into DD_SRC reg with the DD_SRC reg cleared by reading DD_ACK reg. Default value: 0. (0: interrupt request not latched; 1: interrupt request latched) ZHIE Enable interrupt generation on Z high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ZLIE Enable interrupt generation on Z low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) YHIE Enable interrupt generation on Y high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Doc ID 14956 Rev 4 AIS326DQ Register description Table 54. DD_CFG register description (continued) YLIE Enable interrupt generation on Y low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) XHIE Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) XLIE Enable interrupt generation on X low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Direction-detector configuration register. 7.26 DD_SRC (39h) Table 55. X Table 56. DD_SRC register IA ZH ZL YH YL XH XL DD_SRC register description IA Interrupt event from direction change. (0: no direction changes detected; 1: direction has changed from previous measurement) ZH Z High. Default value: 0 (0: Z below THSI threshold; 1: Z accel. exceeding THSE threshold along positive direction of acceleration axis) ZL Z Low. Default value: 0 (0: Z below THSI threshold; 1: Z accel. exceeding THSE threshold along negative direction of acceleration axis) YH Y High. Default value: 0 (0: Y below THSI threshold; 1: Y accel. exceeding THSE threshold along positive direction of acceleration axis) YL Y Low. Default value: 0 (0: Y below THSI threshold; 1: Y accel. exceeding THSE threshold along negative direction of acceleration axis) XH X High. Default value: 0 (0: X below THSI threshold; 1: X accel. exceeding THSE threshold along positive direction of acceleration axis) XL X Low. Default value: 0 (0: X below THSI threshold; 1: X accel. exceeding THSE threshold along negative direction of acceleration axis) Doc ID 14956 Rev 4 37/51 Register description AIS326DQ Direction detector source register. 7.27 DD_ACK (3Ah) Dummy register. If LIR bit in DD_CFG register is set to ‘1’, a reading at this address refreshes the DD_SRC register. Read data is not significant. 7.28 DD_THSI_L (3Ch) Table 57. DD_THSI_L register THSI7 Table 58. THSI6 THSI15 Table 60. THSI1 THSI0 THSI10 THSI9 THSI8 THSE2 THSE1 THSE0 THSE10 THSE9 THSE8 DD_THSI_H register THSI14 THSI13 THSI12 THSI11 DD_THSI_H register description Direction detection internal threshold MSB DD_THSE_L (3Eh) Table 61. THSE7 Table 62. DD_THSE_L register THSE6 THSE5 THSE4 THSE3 DD_THSE_L register description THSE7, THSE0 Direction detection external threshold LSB DD_THSE_H (3Fh) Table 63. THSE15 38/51 THSI2 Direction detection internal threshold LSB THSI15, THSI8 7.31 THSI3 DD_THSI_H (3Dh) Table 59. 7.30 THSI4 DD_THSI_L register description THSI7, THSI0 7.29 THSI5 DD_THSE_H register THSE14 THSE13 THSE12 THSE11 Doc ID 14956 Rev 4 AIS326DQ Register description Table 64. DD_THSE_H register description THSE15, THSE8 Direction detection external threshold MSB Doc ID 14956 Rev 4 39/51 Typical performance characteristics AIS326DQ 8 Typical performance characteristics 8.1 Mechanical characteristics at 25 °C Figure 11. X-axis zero-g level at 3.3 V Figure 12. X-axis sensitivity at 3.3 V 45 30 40 25 30 Percent of parts [%] Percent of parts [%] 35 25 20 15 20 15 10 10 5 5 0 −80 −60 −40 −20 0 20 Zero−g Level Offset [mg] 40 60 0 80 Figure 13. Y-axis zero-g level at 3.3 V 940 960 980 1000 1020 1040 Sensitivity [LSB/g] 1060 1080 1100 1120 1100 1120 1100 1120 Figure 14. Y-axis sensitivity at 3.3 V 40 30 35 25 Percent of parts [%] Percent of parts [%] 30 25 20 15 20 15 10 10 5 5 0 −80 −60 −40 −20 0 20 Zero−g Level Offset [mg] 40 60 0 80 Figure 15. Z-axis zero-g level at 3.3 V 940 960 980 1000 1020 1040 Sensitivity [LSB/g] 1060 1080 Figure 16. Z-axis sensitivity at 3.3 V 30 35 30 25 Percent of parts [%] Percent of parts [%] 25 20 15 10 20 15 10 5 0 −80 40/51 5 −60 −40 −20 0 20 Zero−g Level Offset [mg] 40 60 80 0 940 Doc ID 14956 Rev 4 960 980 1000 1020 1040 Sensitivity [LSB/g] 1060 1080 AIS326DQ 8.2 Typical performance characteristics Mechanical characteristics at -40 °C Figure 17. X-axis zero-g level at 3.3 V Figure 18. X-axis sensitivity at 3.3 V 40 30 35 25 Percent of parts [%] Percent of parts [%] 30 25 20 15 20 15 10 10 5 5 0 −80 −60 −40 −20 0 20 Zero−g Level Offset [mg] 40 60 0 80 Figure 19. Y-axis zero-g level at 3.3 V 940 960 980 1000 1020 1040 Sensitivity [LSB/g] 1060 1080 1100 1120 1100 1120 1100 1120 Figure 20. Y-axis sensitivity at 3.3 V 45 30 40 25 30 Percent of parts [%] Percent of parts [%] 35 25 20 15 20 15 10 10 5 5 0 −80 −60 −40 −20 0 20 Zero−g Level Offset [mg] 40 60 0 80 Figure 21. Z-axis zero-g level at 3.3 V 940 960 980 1000 1020 1040 Sensitivity [LSB/g] 1060 1080 Figure 22. Z-axis sensitivity at 3.3 V 25 30 25 Percent of parts [%] Percent of parts [%] 20 15 10 20 15 10 5 5 0 −80 −60 −40 −20 0 20 Zero−g Level Offset [mg] 40 60 80 0 940 Doc ID 14956 Rev 4 960 980 1000 1020 1040 Sensitivity [LSB/g] 1060 1080 41/51 Typical performance characteristics 8.3 AIS326DQ Mechanical characteristics at 105 °C Figure 23. X-axis zero-g level at 3.3 V Figure 24. X-axis sensitivity at 3.3 V 25 30 25 Percent of parts [%] Percent of parts [%] 20 15 10 20 15 10 5 5 0 −100 −80 −60 −40 −20 0 20 Zero−g Level Offset [mg] 40 60 80 0 100 Figure 25. Y-axis zero-g level at 3.3 V 920 940 960 980 1000 1020 Sensitivity [LSB/g] 1040 1060 1080 1100 1100 1120 1080 1100 Figure 26. Y-axis sensitivity at 3.3 V 35 30 30 25 Percent of parts [%] Percent of parts [%] 25 20 15 20 15 10 10 5 5 0 −100 −80 −60 −40 −20 0 20 Zero−g Level Offset [mg] 40 60 80 0 100 Figure 27. Z-axis zero-g level at 3.3 V 940 960 980 1000 1020 1040 Sensitivity [LSB/g] 1060 1080 Figure 28. Z-axis sensitivity at 3.3 V 25 30 25 Percent of parts [%] Percent of parts [%] 20 15 10 20 15 10 5 5 0 −150 42/51 −100 −50 0 50 Zero−g Level Offset [mg] 100 150 0 920 Doc ID 14956 Rev 4 940 960 980 1000 1020 Sensitivity [LSB/g] 1040 1060 AIS326DQ 8.4 Typical performance characteristics Mechanical characteristics derived from measurement in the -40 °C to +105 °C temperature range Figure 30. X-axis sensitivity change vs. temperature at 3.3 V 100 5 80 4 60 3 40 2 Sensitivity [%] Zero−g Level [mg] Figure 29. X-axis zero-g level change vs. temperature at 3.3 V 20 0 −20 −2 −60 −3 −80 −4 −25 0 25 50 Temp [oC] 75 100 −5 −50 125 Figure 31. Y-axis zero-g level change vs. temperature at 3.3 V 100 5 80 4 60 3 40 2 20 0 −20 −3 −80 −4 25 50 o Temp [ C] 75 100 −5 −50 125 Figure 33. Z-axis zero-g level change vs. temperature at 3.3 V 4 60 3 40 2 Sensitivity [%] 5 80 20 0 −20 −3 −80 −4 75 100 0 25 50 o Temp [ C] 75 100 125 0 −2 25 50 Temp [oC] −25 −1 −60 0 125 1 −40 −25 100 Figure 34. Z-axis sensitivity change vs. temperature at 3.3 V 100 −100 −50 75 0 −2 0 25 50 Temp [oC] −1 −60 −25 0 1 −40 −100 −50 −25 Figure 32. Y-axis sensitivity change vs. temperature at 3.3 V Sensitivity [%] Zero−g Level [mg] 0 −1 −40 −100 −50 Zero−g Level [mg] 1 125 −5 −50 Doc ID 14956 Rev 4 −25 0 25 50 Temp [oC] 75 100 125 43/51 Typical performance characteristics 8.5 AIS326DQ Electro-mechanical characteristics at 25 °C Figure 35. X and Y axes zero-g level as function of supply voltage Figure 36. X and Y axes sensitivity as function of supply voltage 80 5 4 60 Normalized Sensitivity [%] Normalized Zero−g Level [mg] 3 40 20 0 −20 2 1 0 −1 −2 −40 −3 −60 −80 3 −4 3.1 3.2 3.3 Vdd [V] 3.4 3.5 −5 3 3.6 Figure 37. Z axis zero-g level as function of supply voltage 3.1 3.2 3.3 Vdd [V] 3.4 3.5 3.6 Figure 38. Z axis sensitivity as function of supply voltage 80 5 4 60 Normalized Sensitivity [%] Normalized Zero−g Level [mg] 3 40 20 0 −20 2 1 0 −1 −2 −40 −3 −60 −80 3 44/51 −4 3.1 3.2 3.3 Vdd [V] 3.4 3.5 3.6 −5 3 Doc ID 14956 Rev 4 3.1 3.2 3.3 Vdd [V] 3.4 3.5 3.6 AIS326DQ Typical performance characteristics 8.6 Electrical characteristics at 25 °C Figure 40. Current consumption in operational mode (Vdd=3.3 V) 25 25 20 20 Percent of parts [%] Percent of parts [%] Figure 39. Current consumption in powerdown mode (Vdd=3.3 V) 15 10 5 0 −2 15 10 5 −1 8.7 0 1 2 3 4 Current consumption [uA] 5 6 0 500 7 550 600 650 700 750 Current consumption [uA] 800 850 Electrical characteristics at -40 °C Figure 41. Current consumption in powerdown mode (Vdd=3.3 V) Figure 42. Current consumption in operational mode (Vdd=3.3 V) 30 25 25 20 Percent of parts [%] Percent of parts [%] 20 15 10 15 10 5 5 0 −2 −1 8.8 0 1 2 3 4 Current consumption [uA] 5 6 0 500 7 550 600 650 700 750 Current consumption [uA] 800 850 Electrical characteristics at 105 °C Figure 43. Current consumption in powerdown mode (Vdd=3.3 V) Figure 44. Current consumption in operational mode (Vdd=3.3 V) 30 35 30 25 Percent of parts [%] Percent of parts [%] 25 20 15 10 20 15 10 5 0 −2 5 −1 0 1 2 3 4 Current consumption [uA] 5 6 7 0 500 Doc ID 14956 Rev 4 550 600 650 700 750 Current consumption [uA] 800 850 45/51 Soldering information 9 AIS326DQ Soldering information The QFPN-28 package is compliant with the ECOPACK®, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020C, in MSL3 condition. Land pattern and soldering recommendations are also available at www.st.com/. 9.1 General guidelines about soldering surface mount accelerometer As common PCB design and industrial practice when considering accelerometer soldering, there are always 3 elements to take into consideration: 9.2 1. PCB with its own conductive layers (i.e. copper) and other organic materials used for board protection and dielectric isolation. 2. ACCELEROMETER to be mounted on the board. Accelerometer senses acceleration, but it senses also the mechanical stress coming from the board. This stress is minimized with simple PCB design rules. 3. SOLDERING PASTE like SnAgCu. This soldering paste can be dispensed on the board with a screen printing method through a stencil. The pattern of the soldering paste on the PCB is given by the stencil mask itself. PCB design guidelines PCB land and solder masking general recommendations are shown in Figure 45. Refer to Figure 46 for specific device size, land count and pitch. 46/51 ● It is recommended to open solder mask external to PCB land; ● It is mandatory, for correct device functionality, that some clearance is ensured to be present between accelerometer thermal pad and PCB. In order to obtain this clearance it is recommended to open the PCB thermal pad solder mask; ● The area below the sensor (on the same side of the board) must be defined as keepout area. It is strongly recommended not to place any structure in top metal layer underneath the sensor; ● Traces connected to pads should be as much symmetric as possible. Symmetry and balance for pad connection will help component self alignment and will lead to a better control of solder paste reduction after reflow; ● For better performances over temperature it is strongly recommended not to place large insertion components like buttons or shielding boxes at distance less than 2 mm from the sensor; ● Central die pad and “Pin 1 Indicator” are physically connected to GND. Leave “Pin 1 Indicator” unconnected during soldering. Doc ID 14956 Rev 4 AIS326DQ 9.2.1 Soldering information PCB design rules Figure 45. Recommended land and solder mask design for QFPN packages PACKAGE FOOTPRINT PCB LAND SOLDER MASK OPENING PCB THERMAL PAD NOT TO BE DESIGNED ON PCB PCB THERMAL PAD SOLDER MASK OPENING SUGGESTED TO INCREASE DEVICE THERMAL PAD TO PCB CLEARANCE C A D B A = Clearance from PCB land edge to solder mask opening ≤0.1 mm to ensure that some solder mask remains between PCB pads B = PCB land length = QFPN solder pad length + 0.1 mm C = PCB land width = QFPN solder pad width + 0.1 mm D = PCB thermal pad solder mask opening = QFPN thermal pad side + 0.2 mm 9.3 Stencil design and solder paste application The thickness and the pattern of the soldering paste are important for the proper accelerometer mounting process. ● Stainless steel stencils are recommended for solder paste application ● A stencil thickness of 125 - 150 µm (5 - 6 mils) is recommended for screen printing ● The final thickness of soldering paste should allow proper cleaning of flux residuals and clearance between sensor package and PCB ● Stencil aperture should have rectangular shape with dimension up to 25 µm (1mil) smaller than PCB land ● The openings of the stencil for the signal pads should be between 50% and 80% of the PCB pad area ● Optionally, for better solder paste release, the aperture walls should be trapezoidal and the corners rounded ● The fine pitch of the IC leads requires accurate alignment of the stencil to the printed circuit board. The stencil and printed circuit assembly should be aligned to within 25 µm (1 mil) prior to application of the solder paste. Doc ID 14956 Rev 4 47/51 Soldering information 9.4 48/51 AIS326DQ Process consideration ● In case of use of no self-cleaning solder paste it is mandatory proper washing of the board after soldering to eliminate any possible source of leakage between adjacent pads due to flux residues ● The PCB soldering profile depends on the number, size and placement of components in the application board. It is not functional to define a specific soldering profile for the accelerometer only. Customer should use a time and temperature reflow profile that is derived from the PCB design and manufacturing experience. Doc ID 14956 Rev 4 AIS326DQ 10 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 46. QFPN-28 mechanical data and package dimensions mm inch DIM. A MIN. TYP. MAX. MIN. TYP. MAX. 1.70 1.80 1.90 0.067 0.071 0.075 A1 0.05 A3 0.002 0.203 0.008 b 0.30 0.35 0.40 0.012 0.014 0.016 D 6.85 7.0 7.15 0.270 0.275 0.281 D1 4.90 5.00 5.10 0.192 0.197 0.20 E 6.85 7.0 7.15 0.270 0.275 0.281 E1 4.90 5.00 5.10 0.192 0.197 0.20 e L 0.80 0.45 0.55 OUTLINE AND MECHANICAL DATA 0.0315 0.65 0.018 0..022 0.025 L1 0.10 0.004 ddd 0.08 0.003 QFPN-28 (7x7x1.8mm) Quad Flat Package No lead 7787120 C Doc ID 14956 Rev 4 49/51 Revision history 11 AIS326DQ Revision history Table 65. 50/51 Document revision history Date Revision Changes 20-Aug-2008 1 Initial release. 04-Dec-2008 2 Updated VST in Table 3 and IddPdn in Table 4. 30-Apr-2010 3 Updated Section 4: Application hints. 01-Jun-2010 4 Content reworked on cover page to improve readability, no technical changes. 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