ALED6001
Automotive PWM-dimmable single channel LED driver with
integrated boost controller
Datasheet - production data
Applications
• Automotive exterior lighting
• Daytime running lights
• High and low beam lights
TSSOP-16
• Fog lights
• Position lights / blinkers
Features
Description
• AECQ101 qualified
• Switching controller section
– 5.5 V to 36 V input voltage range
– Very low shutdown current: ISHDN < 10 µA
– Internal +5 V LDO for gate driver supply
– Internal +3.3 V LDO for device supply
– Fixed frequency peak current mode control
– Adjustable (100 kHz to 1 MHz) switching
frequency
– External synchronization for multi-device
applications
– High performance external MOSFET driver
– Cycle-by-cycle external MOSFET OCP
– Fixed internal soft-start
– Programmable output OVP
– Boost, buck-boost and SEPIC topologies
supported
– Thermal shutdown with autorestart
– Output short-circuit detection
• LED control section
– Up to 60 V output voltage
– Constant current control loop
– High-side output current sensing circuitry
– 30 to 300 mV differential sensing voltage
– ± 4% output current reference accuracy
– Output overcurrent protection
– Sensing resistor failure protection
– PWM dimming with auxiliary series switch
– Analog dimming
February 2020
This is information on a product in full production.
The ALED6001 is an automotive-grade
(AECQ100 compliant) LED driver that combines a
boost controller and high-side current sensing
circuitry optimized for driving one string of highbrightness LEDs. The device is compatible with
multiple topologies such as boost, SEPIC and
floating load buck-boost. PWM dimming of the
LED brightness is achieved by means of an
external MOSFET in series with the LED string
and directly driven by a dedicated pin. The pin
that manages the LED current setting, usually
connected to an external resistor, can also be
used as analog control if a microcontroller is
located in the LED module. The high-side current
sensing, in combination with a P-channel
MOSFET, provides effective protection in case
the positive terminal of the LED string is shorted
to ground. The high precision current sensing
circuitry allows an LED current regulation
reference within ± 4% accuracy over the entire
temperature range and production spread. A fault
output (open-drain) informs the host system of
faulty conditions: device overtemperature, output
overvoltage (disconnected LED string) and LED
overcurrent.
Table 1. Device summary
Order code
Package
Packing
ALED6001
HTSSOP-16
(exposed pad)
Tube
ALED6001TR
DocID026965 Rev 3
Tape and reel
1/26
www.st.com
Contents
ALED6001
Contents
1
Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8
7.1
Device supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.2
Boost controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/26
Turn on and power-down sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.2.2
Boost controller operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2.3
Boost converter stability and slope compensation . . . . . . . . . . . . . . . . . 14
7.2.4
Switching frequency oscillator and external synchronization . . . . . . . . . 16
7.3
LED current regulation and brightness control . . . . . . . . . . . . . . . . . . . . . 17
7.4
Device protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.4.1
Linear regulators undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.4.2
Power switch overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.4.3
Output overvoltage and OVFB pin disconnection . . . . . . . . . . . . . . . . . 20
7.4.4
Output rail disconnection detection or output short-circuit to ground . . . 21
7.4.5
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.1
9
7.2.1
HTSSOP-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DocID026965 Rev 3
ALED6001
1
Typical application circuit
Typical application circuit
Figure 1. Basic application circuit schematic (boost topology)
L BOOST
DFW
VIN
CIN
VOUT
COUT
ROVFBH
VIN
RGATE
VLDO3
GATE
VOVFB
CLDO3
VLDO3
QSW
CSNS
RSLOPE
LDO3
ROVFBL
RSNS
PGND
VDR
CVDR
VFBP
RVFB
XFAULT
ALED6001
VFBN
PWMI
FSW
VOVFB
VLDO3
OVFB
RFSW
ADIM
RCOMP
PWMO
QDIM
COMP
CCOMP
SGND
AM03411V1
DocID026965 Rev 3
3/26
26
Pin function
2
ALED6001
Pin function
Figure 2. Pin connection (through top view)
PWMI
1
16
VFBP
FS W
2
15
VFBN
XFAU LT
3
14
VIN
LDO3
4
13
VDR
SGND
5
12
GATE
COMP
6
11
PGND
ADIM
7
10
PWMO
OV FB
8
9
CSNS
AM03412V1
4/26
DocID026965 Rev 3
ALED6001
Pin function
Table 2. Pin description
N
Pin
1
PWMI
Device enable and PWM dimming control input.
2
FSW
Switching frequency setting. A resistor between this pin and SGND sets the
desired switching frequency. This pin is also used as synchronization input. If tied
high (e.g.: connected to LDO3 pin) a 600 kHz switching frequency is set.
3
XFAULT
Fault indicator, open-drain output. This pin is tied low by the device in case of
faulty condition. See Section 7.4 on page 20 for details.
4
LDO3
3.3 V linear regulator output and device supply. Connect a 1 μF (typ.) bypass
MLCC between this pin and SGND as close as possible to the chip.
5
SGND
Signal ground. Return for analog circuitry. All setting components must refer to this
grounding pin.
6
COMP
Boost controller loop compensation. A simple RC series must be connected
between this pin and SGND for proper loop compensation. See Section 7.2.3 on
page 14 for details.
7
ADIM
Analog dimming control input. The current at the output is linearly controlled by the
voltage applied to this pin (0.3 V to 1.2 V). When the device is set to operate in
standalone mode, a partition of the LDO3 voltage must be applied to this pin
through a resistor divider.
8
OVFB
Output overvoltage protection feedback input. Connect to the central tap of
a resistor divider at the output.
9
CSNS
Boost controller power switch current sensing input. Connect to the source of the
external Power MOSFET for proper switch overcurrent protection.
10
PWMO
PWM dimming control output. This pin provides a PWM output signal (in phase
with the one applied to the PWMI pin) for direct control of a dimming N-channel
MOSFET.
11
PGND
Power ground. Return for the VDR linear regulator and the power switch gate
drivers. Also used as reference for the Power MOSFET current sensing circuitry.
Connect to ground as close as possible to the quiet terminal of the power switch
sensing resistor.
12
GATE
Power switch gate driver output. Connect to the gate of the Power MOSFET
through a small value resistor.
13
VDR
5 V linear regulator output and gate driver supply. Connect a 1 μF (typ.) bypass
MLCC between this pin and PGND as close as possible to the chip.
14
VIN
Supply voltage input. Connect this pin to the supply power rail. A 1 μF (typ.)
bypass MLCC must be connected between this pin and PGND as close as
possible to the chip.
15
VFBN
Output current differential sensing input, negative terminal. Connect to the hot
terminal (load side) of the high-side sensing resistor.
16
VFBP
Output current differential sensing input, positive terminal. Connect to the quiet
terminal (output capacitor side) of the high-side sensing resistor.
-
TPAD
Thermal pad. Connect to a suitable ground plane area in order to ensure proper
heat dissipation. Electrically connected to PGND and SGND.
DocID026965 Rev 3
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26
Block diagram
3
ALED6001
Block diagram
Figure 3. Simplified block diagram
VIN
VDR
5 V LDO
Slope compensation
Ramp
generator
+
UVLO
detector
EN
Current sensing
CSNS
Boost
converter
control logic
GATE
+
3.3 V LDO
+
LDO3
_
PGND
Sync.
detector
EN
OSC
Output current
setting
Soft start
FSW
ADIM
VFBP
_
gm
+
COMP
+
30 mV - 300 mV
VFBN
Thermal
protection
XFAULT
Feedback/output disconnection and
overload detection
Control logic
OVP
+
_
Fault management
PWM detector
Pow er-down
watchdog timer
EN
OVFB
1.2 V
VDR
PWMO
PWMI
PGND
SGND
AM03413
6/26
DocID026965 Rev 3
ALED6001
4
Absolute maximum ratings
Absolute maximum ratings
Table 3. Absolute maximum ratings(1)
Parameter
Pin
Min.
Max.
VIN to SGND
-0.3
40
VFBP and VFBN to SGND
65
VDR to SGND
-0.3
6
LDO3 to SGND
-0.3
3.6
COMP, CSNS and OVFB to SGND
-0.3
3.6
PGND to SGND
-0.3
0.3
XFAULT, FSW, ADIM and GATE to SGND
-0.3
6
PWMI and PWMO to SGND
-0.3
6
HBM ESD susceptibility
JEDEC JS001
All pins
-2000
2000
VIN, VFBP, VFBN and ADIM ESD
susceptibility
VIN, VFBP, VFBN, ADIM to SGND
-4000
4000
Corner pins
-750
750
Non-corner pins
-500
500
Maximum pin voltage
CDM ESD resistivity to SGND
ANSI/ESD STM5.3.1
Unit
V
1. Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or any other condition above those indicated in Table 5 is not implied. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
Table 4. Thermal characteristics
Symbol
Parameter
TJ,OP
Operating junction temperature
-40
150
TSTG
Storage temperature range
-50
150
Thermal shutdown threshold
150
TSHDN
Conditions
Min.
Typ.
160
Thermal shutdown hysteresis
20
XFAULT release hysteresis
40
Rth,JA(1)
Junction-to-ambient thermal resistance
Rth,JC
Junction-to-case thermal resistance
1s0p
55
2s2p
45
Max.
175
Unit
°C
°C/W
37
1. The device mounted on a standard JESD51-5 test board.
DocID026965 Rev 3
7/26
26
Recommended operating conditions
5
ALED6001
Recommended operating conditions
Table 5. Recommended operating conditions
Symbol
Parameter
Conditions
Min.
Max. Unit
DC characteristics
VVIN
Supply input voltage range
VVDR
VDR pin Input voltage range
VVFBx
Feedback input common mode
voltage range
VFB
Feedback input differential mode
voltage range
VDR and VIN shorted together
VFBP to VFBN
5.5
36
4.7
5.5
4.4
60
30
300
V
mV
AC characteristics
8/26
fsw
Switching frequency
100
1000
fPWMI
Dimming frequency
0.1
20
tPWMI,en
Minimum PWMI pulse duration for
device enable (turn-on)
PWMI input, fSW = 800 kHz
100
µs
tPWMI,dim
Minimum dimming on-time
PWMI input, fSW = 1 MHz
6
µs
DocID026965 Rev 3
kHz
ALED6001
6
Electrical characteristics
Electrical characteristics
VIN = 12 V, VVFBP = 12 V, VVFBN = 12 V and TJ =- 40 °C to 125 °C if not otherwise specified.
Table 6. Electrical characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Supply section
VVIN
Supply voltage range
5.5
PWMI turn-on threshold
PWMI turn-off threshold
PWMI pull-down resistor
PMWI at 3.3 V
36
1.34
1.65
0.7
0.85
1.1
350
570
810
kΩ
10
15
22
ms
100
180
µs
3.3
3.4
V
20
tSHDN
PWMI low-to-shutdown mode delay
tSTART
Start-up time
VLDO3
3.3 V LDO output voltage
6 V ≤ VIN ≤ 36 V, ILDO3 = 0.5 mA,
PWMI high
3.3 V LDO line regulation
ILDO3 = 20 mA, PWMI high
6 V ≤ VIN ≤ 36 V
5
3.3 V LDO load regulation
VIN = 6 V, PWMI high
0.5 mA ≤ ILDO3 ≤ 20 mA
90
100
CLDO3 = CVDR = 470 nF
3.17
V
mV
VLDO3,ON
LDO3 undervoltage lockout upper
threshold
2.2
2.8
3.0
VLDO3,OFF
LDO3 undervoltage lockout lower
threshold
2.5
2.7
2.9
LDO3 undervoltage lockout hysteresis
50
200
400
mV
VVDR
V
3.3 V LDO current limit
VLDO3 = 3.0 V
25
38
46
mA
5 V LDO output voltage
6 V ≤ VIN ≤ 36 V
IVDR = 0.5 mA, PWMI high
4.75
5.0
5.2
V
5 V LDO line regulation
IVDR = 40 mA, PWMI high
6 V ≤ VIN ≤ 36 V
10
40
5 V LDO load regulation
VIN = 6 V, PWMI high
0.5 mA ≤ IVDR ≤ 40 mA
120
200
5 V LDO dropout voltage
IVDR = 25 mA, VVIN = 4.8 V
150
300
mV
VVDR,ON
VDR undervoltage lockout upper
threshold
4.3
4.6
4.75
VVDR,OFF
VDR undervoltage lockout lower
threshold
4.1
4.4
4.6
VDR undervoltage lockout hysteresis
100
150
340
mV
50
75
100
mA
5 V LDO current limit
V
VVDR = 4.5 V
DocID026965 Rev 3
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26
Electrical characteristics
ALED6001
Table 6. Electrical characteristics (continued)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
VIN = 16 V, PWMI low,
-40 °C ≤ TJ ≤ 25 °C
1
4
10
VIN = 16 V, PWMI low,
25 °C ≤ TJ ≤ 125 °C
1
Unit
Power consumption
IVIN,SHDN
IVIN,Q
IVIN,ON
Shutdown current
μA
9
25
1.7
Quiescent current
VIN = 16 V, PWMI to LDO3,
-40 °C ≤ TJ ≤ 125 °C
switching off-time
1
Operating current
VIN = 16 V, PWMI high,
fSW = 200 kHz, CL = 3.3 nF
5
7
Pulse skipping mode
140
180
ns
• kΩ
mA
Boost controller
tON,min
Minimum switching on-time
KFSW
Switching frequency constant
Adjustable switching frequency
fSW
Fixed switching frequency
Synchronization signal frequency
capture range
FSW synchronization input high level
FSW synchronization input low level
Synchronization input high level pulse
width
RGATE
Power switch gate driver output
resistance
tr,GATE
Power switch gate driver rise time
(20 to 80%)
tf,GATE
Power switch gate driver fall time
(80 to 20%)
tSS
Internal soft-start duration
KS
Slope compensation constant
45
50
55
RFSW = 500 kΩ
90
100
110
RFSW = 250 kΩ
180
200
220
RFSW = 50 kΩ
870
1000 1070
FSW pin high (LDO3)
490
600
tCLK,H = 250 ns,
VCLK,L = 0.8 V, VCLK,H = 3.0 V
100
fCLK = 100 kHz to 1 MHz,
tCLK,H = 250 ns
fCLK = 100 kHz to 1 MHz,
VCLK,L = 0.5 V, VCLK,H = 2.8 V
MHz
kHz
710
1000
2.8
0.5
250
V
ns
Pull-up
3
6
Pull-down
1
3
VVDR = 5 V, CL = 3.3 nF
15
30
7
14
2.7
3.5
4.6
ms
3
5
7
A/s
300
360
400
mV
Ω
ns
VCSNS,OCP Power switch OCP detection threshold
10/26
RFSW = 250 kΩ
CSNS pin to PGND
DocID026965 Rev 3
ALED6001
Electrical characteristics
Table 6. Electrical characteristics (continued)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
VADIM = 0.3 V
20
30
40
VADIM = 0.6 V
110
120
130
VADIM = 1.2 V
280
300
304
VADIM to LDO3
290
300
310
ADIM pin voltage turn-off threshold
240
270
290
ADIM pin voltage turn-off hysteresis
1
10
20
Unit
Output current sensing section
VFB
Feedback voltage (VVFBP - VVFBN
differential current sensing voltage)
Feedback reference voltage accuracy
VADIM,OFF
IVFBP
Feedback positive input current
VVFBP = 12.0 V
VVFBN = 11.7 V
-32
-25
-18
IVFBN
Feedback negative input current
VVFBP = 12.0 V
VVFBN = 11.7 V
-7
-5
-4
Pull-up
14
25
Pull-down
3
8
VVDR = 5 V, CL = 3.3 nF
50
130
30
60
mV
μA
PWM dimming control
RPWMO
PWMO gate driver output resistance
tr,PWMO
PWMO gate driver rise time
(20 to 80%)
tf,PWMO
PWMO gate driver fall time (80 to 20%)
Ω
ns
Fault management section
VOVFB,th
XFAULT output low level
IXFAULT = 4 mA
0.12
0.2
V
XFAULT high level leakage current
VXFAULT = 5 V
1
4
µA
OVFB input overvoltage detection
threshold
1.14
1.20
1.25
V
OVFB input overvoltage detection
hysteresis
70
100
130
mV
VOVFB = 1 V
0.7
1
1.2
µA
(VVFBP - VVFBN)
-190
-120
-80
OVFB pull-up current
Open load/VFBP pin disconnection
detection threshold (differential)
mV
Overload /VFBN pin disconnection
detection threshold (differential)
VFBx undervoltage detection threshold
VVFBx respect to SGND
DocID026965 Rev 3
550
600
650
3.1
3.5
4.1
V
11/26
26
Device description
7
ALED6001
Device description
The ALED6001 device is a LED driver that integrates a boost controller, a high-side current
sensing circuitry and a gate driver for an external dimming switch. It has been specifically
designed for driving a single string of high-brightness LEDs. The device can support boost,
floating buck-boost and SEPIC topologies in order to cover most of applications. A single
pin, PWMI, combines both the device enable and PWM dimming control functions.
The brightness of the LED string can be controlled through PWM modulation, analog control
of the output current level (by means of a dedicated pin) or a combination of the two.
7.1
Device supply
The ALED6001 device integrates two low dropout linear regulators to derive the + 3.3 V
(typ.) main supply and the +5 V supply for the gate drivers. The VIN pin is the input terminal
for both linear regulators. Both the linear regulators are enabled when a PWM signal is
applied to the PMWI pin. If the PWMI pin is held low for more than 10 ms (min.), the
shutdown mode is automatically entered and both the LDOs are turned-off for minimum
power consumption. An undervoltage lockout (UVLO) protection is associated to each linear
regulator: in case the output voltage of LDO3 and VDR is below their respective nominal
value, the device is no allowed to operate and the XFAULT pin is tied low.
When an external +5 V rail is available, the related internal LDO can be bypassed by
connecting together the VIN and VDR pins: in this case the VDR pin is used as supply input.
7.2
Boost controller
7.2.1
Turn on and power-down sequences
The ALED6001 is turned on and off by acting on the PWMI pin. This digital input combines
two functions at the same time: device turn on/off and PWM dimming control.
When a high pulse having a 100 µs (typ.) minimum duration appears at the PWMI pin, the
LDOs are turned on and, after the VDR has reached its nominal value, a soft-start sequence
on the boost controller takes place. The output voltage is smoothly increased by releasing in
steps the current limit of the boost converter within a fixed 3 ms (typ.) period, unless the
feedback voltage reaches 75% of the nominal value in advance.
12/26
DocID026965 Rev 3
ALED6001
Device description
Figure 4. Turn-on and turn-off waveforms
tSHDN
PWMI
LDO3
VDR
tSS
tSTART
VOUT
ILED
AM03414
Suddenly after the pulse detection at the PWMI pin, an internal timer is enabled and
cleared. The timer starts counting down on every subsequent falling edge. If the PWMI pin is
held low for more than 10 ms (typ.), the timer is allowed to expire and the ALED6001
automatically turns off minimizing the current consumption.
The start-up time, defined as the delay between the rising edge at the PWMI pin and the first
pulse at the GATE pin, clearly depends on the bypass capacitors connected on both LDO3
and VDR pins. With a typical 1 µF MLCC for both pins, the start-up time is in the order of
100 µs.
7.2.2
Boost controller operation
The boost controller of the ALED6001 device is based on peak current mode control
architecture and can easily support boost, floating buck-boost and SEPIC topologies. The
switching frequency of the converter is set through the FSW pin (external clock source or
setting resistor toward ground) while the switching duty cycle is modulated by the control
loop in order to keep the output (LED) current constant. As a consequence, the output
voltage of the boost converter is determined by the LED string.
DocID026965 Rev 3
13/26
26
Device description
ALED6001
Figure 5. Simplified output regulation circuitry
L
VIN
VOUT
CIN
COUT
QSW
S
GATE
Q
EN
RSLOPE
R
+
_
PGND
RSNS
Sync.
detector
+
FSW
ISL
Current ramp
generator
CSNS
OSC
ISL
RFSW
50 μA
VFBP
EN
+
CCOMP
_
gm
VFBN
+
RCOMP
VADIM
RVFB
-
COMP
ADIM
30mV 300mV
Feedback
reference setting
EN
PWMI
Enable detector and
auto-shutdown counter
PWMO
QDIM
AM03415
The boost controller regulates the output (LED) current by measuring the voltage across the
external sensing resistor. The internal circuitry related to the two pins connected to the
sensing resistor (VFBP and VFBN) has been designed to implement a high-side sensing
scheme and can sustain a relatively high voltage. The voltage drop across the sensing
resistor is the actual feedback voltage for the boost regulator control loop and it can be
linearly varied by means of the ADIM pin (see Section 7.3: LED current regulation and
brightness control on page 17 for details).
The COMP pin is the output of the transconductance amplifier involved in the regulation
loop and a simple RC series must be connected between this pin and SGND to ensure
proper loop stability.
7.2.3
Boost converter stability and slope compensation
As visible in Figure 5, the difference between the feedback voltage and the programmed is
converted into an error current by the transconductance amplifier. This current, provided at
the COMP pin, is turned into a voltage across the compensation network externally
connected to the same pin. This voltage, in turn, determines the trip current for the following
error amplifier.
When the boost converter operates in continuous conduction mode (CCM) and the
switching duty cycle is higher than 50%, sub-harmonic instability may occur.
In order to prevent this, the trip current has to be properly shaped by summing a negative
sawtooth ramp voltage (slope compensation) with the amplified error voltage.
14/26
DocID026965 Rev 3
ALED6001
Device description
In the ALED6001 the slope compensation is achieved by injecting a sawtooth current into
the CSNS pin. Therefore the voltage across the CSNS pin is given by:
Equation 1
vCSNS (t) = iMOS (t) • RSHUNT + iSL (t) • RCSNS
The RSNS resistor is usually designed so that the peak voltage is about 15% of the
overcurrent threshold at the CSNS pin in order to have a good S/N ratio, while the RSLOPE
resistor is calculated for the desired slope compensation amount (typically at least half the
downslope of the inductor current during the switching off-time):
Equation 2
50mV
R SNS ≅ -------------------I L, PEAK
Equation 3
V OUT – V IN, min
R SNS
R SLOPE ≥ ---------------------------------------- • -------------f SW • L
I SL
Where ISL = 50 µA is the maximum current injected by the slope compensation circuitry in
the CSNS pin.
Figure 6. Power switch current sensing scheme
VIN
ISL
50μA
GATE
ISL
CSNS
+
OCP
RSLOPE
VSC
360mV
_
VSNS
RSNS
AM03416
DocID026965 Rev 3
15/26
26
Device description
7.2.4
ALED6001
Switching frequency oscillator and external synchronization
The switching frequency of the boost controller is simply set by connecting a resistor
between the FSW pin and ground. The resistor can be calculated according to Equation 4:
Equation 4
K FSW
R = --------------fSW
Where KFSW = 5 • 1010 Hz • Ω (typ.) and 100 kHz ≤ fSW ≤ 1 MHz.
Figure 7. Switching frequency vs. setting resistor at the FSW pin
1000
900
800
fSW (kHz)
700
600
500
400
300
200
100
0
0
50
100
150
200
250
300
R FSW
350
400
450
500
550
)
AM03417
If the FSW pin is tied high (e.g.: connecting it to LDO3), a 600 kHz (typ.) default switching
frequency is set.
In case the boost controller of the ALED6001 has to be externally synchronized, the FSW
pin can be used as synchronization clock input. In this case the external clock must have
a frequency in the 100 kHz - 1 MHz range and a 250 ns minimum pulse duration in order to
ensure internal oscillator locking.
16/26
DocID026965 Rev 3
ALED6001
Device description
Figure 8. External synchronization signal timing diagram
V FSW
250 ns
3V
0.8 V
t
AM03418
7.3
LED current regulation and brightness control
The brightness of the LEDs connected at the output of the ALED6001 can be controlled by
applying the desired PWM signal at the PWMI pin. The boost controller is turned on and off
according to the duty cycle of the PWMI control signal. When the PWMI is high (and the
soft-start has been completed), the output (LED) current is regulated by keeping constant
the voltage drop across the external sensing resistor connected between the VFBP and
VFBN pins.
A buffered replica of PWMI is available at the PWMO for driving a dimming N-channel
MOSFET when superior dimming performance is required. In some applications a high-side
dimming switch could be desirable (e.g.: protection against output short-circuit to ground or
LED strings using the chassis as return) and a P-channel MOSFET can be used as shown
in Figure 9. Some additional components may be needed to avoid excessive voltage
between the gate and the source of such MOSFET.
DocID026965 Rev 3
17/26
26
Device description
ALED6001
Figure 9. High-side dimming control by using a P-channel MOSFET
L BOOST
DFW
VIN
COUT
CIN
VOUT
ROVFBH
VIN
RGATE
VLDO3
QSW
GATE
CLDO3
RSLOPE
VDR
CVDR
VOVFB
ROVFBL
CSNS
LDO3
RSNS
PGND
ALED6001
VFBP
RVFB
XFAULT
VFBN
PWMI
RGL
FSW
DZ
RGH
QDIMH
VOVFB
VLDO3
RFSW
OVFB
ADIM
RCOMP
PWMO
QDIML
COMP
CCOMP
SGND
AM03419V2
The regulation loop continuously compares the differential voltage drop with an internal
reference and adjusts the switching duty cycle accordingly. In order to provide design
flexibility and analog dimming capability, the internal feedback reference can be changed
through the ADIM pin. As visible in Figure 10, the reference voltage is proportional to the
voltage at the ADIM pin within a limited range.
Equation 5
18/26
DocID026965 Rev 3
ALED6001
Device description
Figure 10. Differential feedback reference voltage vs. ADIM pin voltage
VREF
300 mV
30 mV
300 mV
260 mV
1.2 V
VADIM
AM03420
In case a fixed output (LED) current is needed or simple PWM dimming is used, the ADIM
pin must be connected to the central tap of a resistor divider (supplied by the LDO3 pin) for
the desired LED current level. Because of the best LED current accuracy overtemperature
is obtained at full scale, a voltage higher than 1.2 V should be applied at the ADIM pin in
case the analog dimming is not needed.
If an analog dimming control is required, the voltage at the ADIM pin can be changed
runtime within its functional range. A simple way to perform an analog dimming is easily
achieved by extracting the average value of a PWM signal through a simple RC low-pass
filter (Figure 10).
Figure 11. Simple ADIM pin voltage control through a filtered PWM signal
ALED6001
PWMI
Rf
ADIM
Cf
SGND
AM03421V1
If the voltage at the ADIM pin is lower than 240 mV, both the PWMO and GATE pins are
forced low and the boost converter is temporary disabled. As soon as the ADIM pin voltage
is driven inside the operating range, normal operation is resumed.
DocID026965 Rev 3
19/26
26
Device description
ALED6001
7.4
Device protections
7.4.1
Linear regulators undervoltage lockout
Both the 5 V and 3.3 V linear regulators of the ALED6001 are equipped with an
undervoltage lockout (UVLO) protection. The UVLO protections avoid improper device
operation in case at least one of the two outputs (VDR and LDO3) is below the allowed
level. In particular, the ALED6001 performs the soft-start sequence only after both VDR and
LDO3 cross their respective upper UVLO threshold.
7.4.2
Power switch overcurrent
The current flowing through the external Power MOSFET is monitored, cycle-by-cycle, by
sensing the voltage across the shunt resistor in series with its source. If the voltage drop
exceeds the overcurrent protection (OCP) level, the ongoing switching cycle is suddenly
terminated (cycle-by-cycle Power MOSFET OCP). Normal operation is automatically
resumed once the root cause has been removed. The XFAULT pin is not affected by OCP.
As explained in Section 7.2 on page 12 the slope compensation is added by injecting
a sawtooth current at the CSNS pin. As a consequence, the OCP threshold depends on
both the slope compensation amount and the boost converter's operating point:
Equation 6
VCSNS, OCP – D • I SL • R SLOPE
I MOS, OCP = ---------------------------------------------------------------------------------R SNS
Where VCSNS,OCP = 360 mV (typ.), ISL = 50 µA (typ.) and D is the switching duty cycle.
7.4.3
Output overvoltage and OVFB pin disconnection
The output overvoltage fault detection is achieved by comparing the voltage at the OVFB
pin with an internal threshold. Because of this fault can potentially damage both the device
and the external components, a latched turn off condition is triggered once this event has
been detected. A resistor divider connected to the output of the boost converter sets the
desired OVP threshold.
The OVFB is internally pulled-up in order to protect the device against an OVFB pin
disconnection fault: if the pin is left floating, the OVP is suddenly triggered regardless of the
output voltage level. This small pull-up current (IOVFB,PU) must be taken into account when
designing an OVP output divider involving high resistance values. Equation 7 allows setting
the desired output OVP level (ROVPH and ROVPL are the two resistors of the output divider
whose central tap is connected to the OVFB pin of the ALED6001):
Equation 7
R OVPH + R OVPL
V OUT, OVP = ------------------------------------------- V TH, OVFB – R OVPL • I OVFB, PU
R OVPL
Where VTH,OVFB = 1.2 V (typ.) and IOVFB,PU = 1 µA (typ.).
Once the OVP faulty condition is detected, the ALED6001 device suddenly stops switching.
Both GATE and PWMO are forced low and the XFAULT pin is lowered. The condition is
latched and normal operation is resumed by toggling the PWMI pin (PWMI has to be low for
more than 10 ms) after the root cause has been removed.
20/26
DocID026965 Rev 3
ALED6001
7.4.4
Device description
Output rail disconnection detection or output short-circuit to ground
If the connection between the output rail and the output sensing resistor is lost, the voltage
of both the VFBP and VFBN pins falls down to zero. The ALED6001 detects this faulty
condition by comparing the absolute voltage of both VFBP and VFBN pins with an internal
3.3 V threshold and latches-off as a consequence (the GATE and PWMO pins forced low,
XFAULT pin lowered). Normal operation is resumed by toggling the PWMI pin (PWMI has to
be low for more than 10 ms) after the root cause has been removed.
When the ALED6001 is operating with a boost topology, a similar condition occurs in case of
output-to-ground short-circuit. Of course, because of the inherent path between input and
output, a real protection against this faulty condition can be achieved only if the device is
capable of disconnecting the boost output by means of the dimming switch (e.g.: in case
a P-channel MOSFET is used as a high-side dimming switch).
Figure 12. Load disconnection (1 and 5), open feedback (2 and 3) and open OVFB faulty
conditions
L BOOST
DFW
VOUT
VIN
COUT
CIN
VIN
RGATE
1
CSNS
VDR
VLDO3
QSW
GATE
CVDR
RSLOPE
RSNS
LDO3
PGND
CLDO3
2
ALED6001
VFBP
XFAULT
VFB
PWMI
3
RVFB
VFBN
VLDO3
VOUT
RADIMH
RADIML
4
ADIM
OVFB
ROVFBH
VOVFB
RFSW
ROVFBL
FSW
PWMO
COMP
CCOMP
RCOMP
SGND
5
QDIM
AM03422V1
DocID026965 Rev 3
21/26
26
Device description
7.4.5
ALED6001
Thermal shutdown
The ALED6001 implements an autorestarting thermal protection in order to avoid damages
due to excessive die temperature. Once the chip temperature reaches the upper
overtemperature protection (OTP) threshold, the ongoing operation is suddenly stopped,
both the PWMO and XFAULT pins are held low and the 5 V linear regulator (VDR pin) is
turned off. As soon as the die temperature drops below the autorestarting threshold, a new
soft-start sequence takes place if the PWMI pin is still high and a 1 ms (typ.) deglitch delay
has expired.
The XFAULT pin goes low as soon as the OTP threshold is crossed and it is released once
the device temperature drops below a third threshold, lower than the restart one, in order to
provide a stable information to the host system.
Table 7. Faulty conditions management summary
Faulty condition
Detection mechanism
1
Output rail/load disconnection
VVFBx 1.2 V (internal pull-up)
Consequence
Device turning-off (latched condition).
GATE, PWMO and XFAULT pins are
forced low.
VOVFB > 1.2 V
Output overvoltage
Power switch overcurrent
IC overtemperature
VCSNS > 360 mV
Ongoing switching cycle terminated
TJ > 160 °C (typ.)
Device turning-off (VDR off, LDO3
active)
GATE, PWMO and XFAULT pins are
forced low
Autorestart if TJ < 140 °C (typ.) and
PWMI still high.
XFAULT pin is released
If TJ
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