ASM330LHB
Datasheet
High-accuracy automotive 6-axis inertial module for car electronic control units
Features
Product status link
ASM330LHB
Product summary
Order code
ASM330LHBTR
Temp. range
[°C]
-40 to +105
Package
LGA-14L
(2.5 x 3.0 x 0.83 mm3)
Packing
Tape and reel
Product resources
TN0018 (Design and soldering)
Product labels
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AEC-Q100 qualified
Extended temperature range from -40 to +105 °C
Embedded compensation for high stability over temperature
Android compliant
Accelerometer user-selectable full scale up to ±16 g
Extended gyroscope range from ±125 to ±4000 dps
Dual operating modes: high-performance and low-power mode
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I²C, MIPI I3CSM, and SPI serial interfaces
Six-channel synchronized output to enhance accuracy of dead-reckoning
algorithms
Programmable finite state machine
Machine learning core
Smart programmable interrupts
Embedded 3 KB FIFO available to underload host processor
ECOPACK and RoHS compliant
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Applications
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Satellite precise positioning
Vehicle-to-everything (V2X)
ADAS systems
Active suspension
Radar, lidar, and camera digital stabilization
Door/trunk modules
Motion-activated functions
Description
The ASM330LHB is a system-in-package featuring a 3-axis digital accelerometer and
a 3-axis digital gyroscope with an extended temperature range up to +105 °C.
A safety manual and a software library, certified according to ISO26262:2018, are
provided to support the development of applications using the ASM330LHB and
targeting ASIL-B requirements.
ST’s family of MEMS sensor modules leverages the robust and mature
manufacturing processes already used for the production of micromachined
accelerometers and gyroscopes to serve both the automotive and consumer market.
The ASM330LHB is AEC-Q100 compliant and industrialized through a dedicated
MEMS production flow to meet automotive reliability standards. All the parts are fully
tested with respect to temperature to ensure the highest quality level.
The sensing elements are manufactured using ST’s proprietary micromachining
processes, while the IC interfaces are developed using CMOS technology that allows
the design of a dedicated circuit, which is trimmed to better match the characteristics
of the sensing element.
DS13773 - Rev 7 - February 2023
For further information contact your local STMicroelectronics sales office.
www.st.com
ASM330LHB
The ASM330LHB has a full-scale acceleration range of ±2/±4/±8/±16 g and a wide angular rate range of
±125/±250/±500/±1000/±2000/±4000 dps that enable its usage in a broad range of automotive applications.
The device supports dual operating modes: high-performance mode and low-power mode.
All the design aspects of the ASM330LHB have been optimized to reach superior output stability, extremely low
noise, and full data synchronization to the benefit of sensor-assisted applications like dead reckoning and sensor
fusion.
The ASM330LHB is available in a 14-lead plastic land grid array (LGA) package.
DS13773 - Rev 7
page 2/131
ASM330LHB
Overview
1
Overview
The ASM330LHB is a system-in-package featuring a high-performance 3-axis digital accelerometer and 3-axis
digital gyroscope.
This device is suitable for telematics and dead-reckoning applications as well as vehicle-to-vehicle (V2X) and
impact detection as a result of its high stability over temperature and time, combined with superior sensing
precision.
Supporting dual operating modes, the device has enhanced flexibility versus application requirements, leveraging
on multiple voltage and multiple ODR selections. The device also includes digital features like a finite state
machine and an ST proprietary machine learning core, allowing defined motion pattern detection or some
complex algorithms run in the application processor to be moved to the MEMS sensor with the advantage of
consistent reduction in power consumption.
The event-detection interrupts enable efficient and reliable motion-activated functions, implementing hardware
recognition of free-fall events, 6D orientation, activity or inactivity, and wake-up events.
Like the entire portfolio of MEMS sensor modules, the ASM330LHB leverages the robust and mature in-house
manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. The
various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces
are developed using CMOS technology that allows the design of a dedicated circuit, which is trimmed to better
match the characteristics of the sensing element.
The ASM330LHB is available in a small plastic land grid array (LGA) package of 2.5 x 3.0 x 0.83 mm to address
ultra-compact solutions.
This device, used in redundancy (as two modules) and in combination with a dedicated software library, has been
evaluated as compatible to be adopted in ASIL-B automotive applications. This solution is described in detail in
application note AN5691.
DS13773 - Rev 7
page 3/131
ASM330LHB
Embedded low-power features
2
Embedded low-power features
The ASM330LHB has been designed to feature the following on-chip functions:
•
3 KB data buffering
–
–
•
Event-detection interrupts (fully configurable)
•
–
Free-fall
–
Wake-up
–
6D orientation
–
Activity/inactivity recognition
–
Stationary/motion detection
Specific IP blocks with negligible power consumption and high performance
–
–
2.1
100% efficiency with flexible configurations and partitioning
Possibility to store timestamp
Finite state machine (FSM) for the accelerometer and gyroscope
Machine learning core (MLC) for the accelerometer and gyroscope
Finite state machine
The ASM330LHB can be configured to generate interrupt signals activated by user-defined motion patterns. To
do this, up to 16 embedded finite state machines can be programmed independently for motion detection such as
vehicle status (stationary or moving), anti-theft alarm and shock detection.
Definition of finite state machine
A state machine is a mathematical abstraction used to design logic connections. It is a behavioral model
composed of a finite number of states and transitions between states, similar to a flow chart in which one can
inspect the way logic runs when certain conditions are met. The state machine begins with a start state, goes to
different states through transitions dependent on the inputs, and can finally end in a specific state (called stop
state). The current state is determined by the past states of the system. The figure below shows a generic state
machine.
Figure 1. Generic state machine
DS13773 - Rev 7
page 4/131
ASM330LHB
Finite state machine
Finite state machine in the ASM330LHB
The ASM330LHB works as a combo accelerometer-gyroscope sensor, generating acceleration and angular rate
output data. These data can be used as input of up to 16 programs in the embedded finite state machine
(Figure 2. State machine in the ASM330LHB).
All 16 finite state machines are independent: each one has its dedicated memory area and it is independently
executed. An interrupt is generated when the end state is reached or when some specific command is performed.
Figure 2. State machine in the ASM330LHB
ASM330LHB
ACC [LSB]
GYR [LSB]
SIGNAL
CONDITIONING
FSM X
FSM Output
X = 1..16
DS13773 - Rev 7
page 5/131
ASM330LHB
Machine learning core
2.2
Machine learning core
The ASM330LHB embeds a dedicated core for machine learning processing that provides system flexibility,
allowing some algorithms run in the application processor to be moved to the MEMS sensor with the advantage of
consistent reduction in power consumption.
Machine learning core logic allows identifying if a data pattern (for example motion, pressure, temperature,
magnetic data, and so forth) matches a user-defined set of classes. Typical examples of applications could be
activity detection like running, walking, driving, and so forth.
The ASM330LHB machine learning core works on data patterns coming from the accelerometer and gyro
sensors. The input data can be filtered using a dedicated configurable computation block containing filters and
features computed in a fixed time window defined by the user.
Machine learning processing is based on logical processing composed of a series of configurable nodes
characterized by "if-then-else" conditions where the "feature" values are evaluated against defined thresholds.
Figure 3. Machine learning core in the ASM330LHB
Sensor data
Machine
Learning Core
OUTPUT
Accelerometer
Filters
Results
Gyroscope
Features
Interrupts
INPUT
Machine
Learning Core
Logical processing
The ASM330LHB can be configured to run up to 8 flows simultaneously and independently and every flow can
generate up to 256 results. The total number of nodes can be up to 512.
The results of the machine learning processing are available in dedicated output registers readable from the
application processor at any time.
The ASM330LHB machine learning core can be configured to generate an interrupt when a change in the result
occurs.
DS13773 - Rev 7
page 6/131
ASM330LHB
Pin description
3
Pin description
Figure 4. Pin connections
Z
SDA
14
11
10
9
1
BOTTOM
VIEW
8
2
3
4
7
6
5
Vdd_IO
ΩR
13
NC
ΩY
NC
NC
INT2
Vdd
12
GND
Direction of detectable
accelerations (top view)
SCL
X
CS
Y
SDO/SA0
RES
RES
INT1
ΩP
Direction of detectable
angular rates (top view)
DS13773 - Rev 7
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ASM330LHB
Pin description
Table 1. Pin description
Pin#
Name
Function
SPI 4-wire interface serial data output (SDO)
1
SDO/SA0
I²C least significant bit of the device address (SA0)
MIPI I3CSM least significant bit of the static address (SA0)
2
RES
Connect to Vdd_IO or GND
3
RES
Connect to Vdd_IO or GND
4
INT1
Programmable interrupt in I²C and SPI
5
Vdd_IO(1)
6
NC
7
GND
0 V supply
8
Vdd(1)
Power supply
9
INT2
Programmable interrupt 2 (INT2) / data enable (DEN)
10
NC
Leave unconnected(2)
11
NC
Leave unconnected(2)
Power supply for I/O pins
Connect to Vdd_IO or GND or leave unconnected
I²C/MIPI I3CSM/SPI mode selection
12
CS
(1: SPI idle mode / I²C/MIPI I3CSM communication enabled;
0: SPI communication mode / I²C/MIPI I3CSM disabled)
13
SCL
I²C/MIPI I3CSM serial clock (SCL)
SPI serial port clock (SPC)
I²C/MIPI I3CSM serial data (SDA)
14
SDA
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
1. Vdd_IO: Recommended 100 nF filter capacitor. Vdd: Recommended 100 nF plus 10 μF capacitors.
2. Leave pin electrically unconnected and soldered to PCB.
DS13773 - Rev 7
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ASM330LHB
Module specifications
4
Module specifications
4.1
Mechanical characteristics
@Vdd = 3.0 V, T = -40 °C to +105 °C, up to gyroscope FS = ±2000 dps unless otherwise noted.
The product is factory calibrated at 3.0 V. The operational power supply range is from 1.71 V to 3.6 V.
Table 2. Mechanical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.(1)
Max.
Unit
±2
LA_FS
±4
Linear acceleration measurement range
g
±8
±16
±125
±250
G_FS
±500
Angular rate measurement range
dps
±1000
±2000
±4000
LA_So
G_So
LA_So%
G_So%
Linear acceleration sensitivity
Angular rate sensitivity
Sensitivity
tolerance(2)
Sensitivity tolerance - long
@LA_FS = ±2 g
0.061
@LA_FS = ±4 g
0.122
@LA_FS = ±8 g
0.244
@LA_FS = ±16 g
0.488
@G_FS = ±125 dps
4.37
@G_FS = ±250 dps
8.75
@G_FS = ±500 dps
17.5
@G_FS = ±1000 dps
35.0
@G_FS = ±2000 dps
70.0
@G_FS = ±4000 dps
140.0
@25 °C
term(3)
@25 °C
Sensitivity tolerance - long term(3)
mdps/LSB
±2
-6
Sensitivity tolerance(2)
mg/LSB
%
+6
±2
-8
%
%
+8
%
LA_SoDr
Linear acceleration sensitivity change vs. temperature
±100
ppm/°C
G_SoDr
Angular rate sensitivity change vs. temperature
±70
ppm/°C
LA_TyOff
Linear acceleration zero-g level offset accuracy(2)
±20
mg
LA_Off
Linear acceleration offset accuracy - long term(3)
G_TyOff
G_Off
Angular rate zero-rate level
accuracy(2)
Angular rate offset accuracy - long
@25 °C
-150
@25 °C
term(3)
+150
±2
-7
mg
dps
+7
dps
LA_TCOff Linear acceleration zero-g level change vs. temperature
±0.10
mg/°C
G_TCOff
±0.005
dps/°C
±1
%
LA_Cx
Angular rate typical zero-rate level change vs. temperature
Linear acceleration cross-axis sensitivity
DS13773 - Rev 7
@25 °C
page 9/131
ASM330LHB
Mechanical characteristics
Symbol
G_Cx
An
AnRMS
Parameter
Angular rate cross-axis sensitivity
Acceleration noise
density(4)(6)
Acceleration RMS noise in low-power
Test conditions
Min.
Typ.(1)
@25 °C
±1
@LA_FS = ±2 g
60
mode(5)
Max.
Unit
%
200
1.8
µg/√Hz
mg(RMS)
Rate noise density(4)(6)
5
RnRMS
Gyroscope RMS noise in low-power mode(5)
90
mdps
XL_NL
Accelerometer nonlinearity(7)
Best-fit straight line
0.5
%FS
G_NL
Gyroscope nonlinearity(7)
Best-fit straight line
0.01
% FS
@25 °C
0.03
m/sec/√h
@25 °C
40
µg
Rn
VRW
Velocity random
walk(7)
instability(7)
12
mdps/√Hz
XL_BI
Accelerometer bias
ARW
Angular random walk(7)
@25 °C
0.21
°/√h
G_BI
Gyroscope bias instability(7)
@25 °C
3
°/h
1.6(8)
12.5
26
52
LA_ODR
Linear acceleration output data rate
Hz
104
208
416
833
1667
12.5
26
52
G_ODR
104
Angular rate output data rate
Hz
208
416
833
1667
Linear acceleration self-test output change - long term(3)(9)(10)(11)
Vst
Top
Angular rate self-test output change - long term(3)(12)(13)
40
1700
mg
FS = ±250 dps
20
80
dps
FS = ±2000 dps
150
700
dps
-40
+105
°C
Operating temperature range
1. Typical specifications are not guaranteed.
2. Values after factory calibration test and trimming at T = 25 °C.
3. Long term includes the following conditions: post solder, drift in temperature in the range [-40°C to +105 °C] and over life.
4. Max. values from design and characterization at ambient temperature (T = 25 °C).
5. RMS noise is the same for all ODRs.
6. Noise density is the same for all ODRs.
7. Based on characterization data on a limited number of samples. Not measured during final test for production.
8. This ODR is available when the accelerometer is in low-power mode.
9. Accelerometer self-test limits are full-scale independent.
10. The sign of the linear acceleration self-test output change is defined by the STx_XL bits in a dedicated register for all axes.
11. The linear acceleration self-test output change is defined with the device in stationary condition as the absolute value of: OUTPUT[LSb]
(self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 0.061 mg at ±2 g full scale.
DS13773 - Rev 7
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ASM330LHB
Electrical characteristics
12. The angular rate self-test output change is defined with the device in stationary condition as the absolute value of: OUTPUT[LSb] (self-test
enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 70 mdps at ±2000 dps full scale.
13. The sign of the angular rate self-test output change is defined by the STx_G bits in a dedicated register for all axes.
4.2
Electrical characteristics
@ Vdd = 3.0 V, T = -40 °C to +105 °C, up to gyroscope FS = ±2000 dps unless otherwise noted.
Table 3. Electrical characteristics
Symbol
Vdd
Parameter
Test conditions
Min.
Typ.(1)
Max.
Unit
Supply voltage
1.71
3.6
V
Vdd_IO
Power supply for I/O
1.62
3.6
V
GA_Idd
Gyroscope and accelerometer current consumption
Vdd = 3.0 V, ODR = 1.6 kHz
-40 °C to +125 °C
1.3
1.6
mA
Accelerometer current consumption in high-performance mode
Vdd = 3.0 V, ODR = 1.6 kHz
-40 °C to +125 °C
360
530
µA
Vdd = 3.0 V, ODR = 52 Hz
@25 °C
50
150
µA
Vdd = 3.0 V, ODR = 12.5 Hz(3)
@25 °C
14
µA
Vdd = 3.0 V, ODR = 1.6 Hz(3)
@25 °C
7
µA
Vdd = 1.71 V, ODR = 52 Hz
@25 °C
40
Vdd = 1.71 V, ODR = 12.5 Hz(3)
@25 °C
11
µA
Vdd = 1.71 V, ODR = 1.6 Hz(3)
@25 °C
5.5
µA
Vdd = 3.0 V, ODR = 52 Hz
-40 °C to +125 °C
530
Vdd = 3.0 V, ODR = 12.5 Hz(3)
@25 °C
475
Vdd = 1.71 V, ODR = 52 Hz
-40 °C to +125 °C
520
Vdd = 1.71 V, ODR = 12.5 Hz(3)
@25 °C
470
A_IddHP
LA_IddLM Accelerometer current consumption in low-power mode
LC_IddLM Current consumption in low-power mode, combo mode
IddPD
Ton
Gyroscope and accelerometer current consumption during powerdown
Vdd = 3.0 V, @25 °C
Turn-on time(2)
µA
µA
µA
800
µA
µA
13
µA
ms
0.7 *
Vdd_IO
Digital high-level input voltage
VIL(3)
Digital low-level input voltage
VOH(3)
High-level output voltage
IOH = 4 mA(4)
VOL(3)
Low-level output voltage
IOL = 4 mA(4)
Operating temperature range
800
35
VIH(3)
Top
5
150
V
0.3 * Vdd_IO
V
Vdd_IO 0.2
-40
V
0.2
V
+105
°C
1. Typical specifications are not guaranteed.
2. Time to obtain stable sensitivity (within ±5% of final value) switching from power-down to normal operation
3. Evaluated by characterization - not tested in production
4. 4 mA is the minimum driving capability, that is, the minimum DC current that can be sourced/sunk by the digital pad in order to guarantee
the correct digital output voltage levels VOH and VOL.
DS13773 - Rev 7
page 11/131
ASM330LHB
Temperature sensor characteristics
4.3
Temperature sensor characteristics
@ Vdd = 3.0 V, T = 25 °C unless otherwise noted. The product is factory calibrated at 3.0 V.
Table 4. Temperature sensor characteristics
Symbol
TODR(2)
Toff
Parameter
Test condition
Min.
Temperature refresh rate
Temperature offset(3)
TSen
Temperature sensitivity
TST
Temperature stabilization time(4)
T_ADC_res
Temperature ADC resolution
Top
Operating temperature range
Typ.(1)
Max.
Unit
52
-15
Hz
+15
256
°C
LSB/°C
500
µs
16
-40
bit
+105
°C
1. Typical specifications are not guaranteed.
2. When the accelerometer is in low-power mode and the gyroscope part is turned off, the TODR value is equal to the
accelerometer ODR.
3. The output of the temperature sensor is 0 LSB (typ.) at 25 °C.
4. Time from power ON to valid output data. Based on characterization.
DS13773 - Rev 7
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ASM330LHB
Communication interface characteristics
4.4
Communication interface characteristics
4.4.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 5. SPI slave timing values (in mode 3)
Symbol
Parameter
Value(1)
Min
tc(SPC)
SPI clock cycle
fc(SPC)
SPI clock frequency
tsu(CS)
CS setup time
5
th(CS)
CS hold time
20
tsu(SI)
SDI input setup time
5
th(SI)
SDI input hold time
15
tv(SO)
SDO valid output time
th(SO)
SDO output hold time
tdis(SO)
SDO output disable time
Max
Unit
ns
100
10
MHz
ns
50
5
50
1. Values are evaluated at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production
Figure 5. SPI slave timing diagram (in mode 3)
Note: Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both input and output ports.
DS13773 - Rev 7
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ASM330LHB
Communication interface characteristics
4.4.2
I²C - inter-IC control interface
Subject to general operating conditions for Vdd and Top.
Table 6. I²C slave timing values
Symbol
f(SCL)
I²C standard mode(1)
Parameter
I²C fast mode(1)
Min
Max
Min
Max
0
100
0
400
SCL clock frequency
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
th(SDA)
SDA data hold time
0
th(ST)
START condition hold time
4
0.6
tsu(SR)
Repeated START condition setup time
4.7
0.6
tsu(SP)
STOP condition setup time
4
0.6
4.7
1.3
tw(SP:SR)
Bus free time between STOP and START condition
3.45
Unit
kHz
µs
ns
0
0.9
µs
1. Data based on standard I²C protocol requirement, not tested in production.
Figure 6. I²C slave timing diagram
REPEATED
START
START
tsu(SR)
tw(SP:SR)
SDA
tsu(SDA)
START
th(SDA)
tsu(SP)
STOP
SCL
th(ST)
tw(SCLL)
tw(SCLH)
Note: Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both ports.
DS13773 - Rev 7
page 14/131
ASM330LHB
Communication interface characteristics
Table 7. I²C high-speed mode specifications at 1 MHz
Symbol
Min.
Max.
Unit
0
1
MHz
Hold time (repeated) START condition
260
-
tLOW
Low period of the SCL clock
500
-
tHIGH
High period of the SCL clock
260
-
tSU;STA
Setup time for a repeated START condition
260
-
tHD;DAT
Data hold time
0
-
tSU;DAT
Data setup time
50
-
fSCL
tHD;STA
Fast mode plus(1)
Parameter
SCL clock frequency
trDA
Rise time of SDA signal
-
120
tfDA
Fall time of SDA signal
-
120
trCL
Rise time of SCL signal
20*Vdd/5.5
120
tfCL
Fall time of SCL signal
20*Vdd/5.5
120
260
-
Capacitive load for each bus line
-
550
tVD;DAT
Data valid time
-
450
tVD;ACK
Data valid acknowledge time
-
450
tSU;STO
Cb
Setup time for STOP condition
VnL
Noise margin at low level
0.1Vdd
-
VnH
Noise margin at high level
0.2Vdd
-
tSP
Pulse width of spikes that must be suppressed by the input filter
0
50
ns
pF
ns
V
ns
1. Data based on characterization, not tested in production
DS13773 - Rev 7
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ASM330LHB
Absolute maximum ratings
4.5
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to
maximum rating conditions for extended periods may affect device reliability.
Table 8. Absolute maximum ratings
Symbol
Ratings
Maximum value
Unit
Vdd
Supply voltage
-0.3 to 4.8
V
TSTG
Storage temperature range
-40 to +125
°C
3000
g
2
kV
-0.3 to Vdd_IO +0.3
V
Sg
ESD
Vin
Acceleration g for 0.3 ms
Electrostatic discharge protection (HBM)
Input voltage on any control pin
(including CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)
Note: Supply voltage on any pin should never exceed 4.8 V.
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.
DS13773 - Rev 7
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ASM330LHB
Terminology
4.6
4.6.1
Terminology
Sensitivity
Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device.
Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards
the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the
output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value
from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes
very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large
number of sensors (see Table 2).
An angular rate gyroscope is a device that produces a positive-going digital output for counterclockwise rotation
around the axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a
defined angular velocity to it. This value changes very little over temperature and time (see Table 2).
4.6.2
Zero-g and zero-rate level
Linear acceleration zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal
output signal if no acceleration is present. A sensor in a steady state on a horizontal surface measures 0g on both
the X-axis and Y-axis, whereas the Z-axis measures 1 g. Ideally, the output is in the middle of the dynamic range
of the sensor (content of OUT registers 00h, data expressed as two’s complement number). A deviation from the
ideal value in this case is called zero-g offset.
Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after
mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes
little over temperature, see “Linear acceleration zero-g level change vs. temperature” in Table 2. The zero-g level
tolerance (TyOff) describes the standard deviation of the range of zero-g levels of a group of sensors.
Zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of precise
MEMS sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly
change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress.
This value changes very little over temperature and time (see Table 2).
DS13773 - Rev 7
page 17/131
ASM330LHB
Digital interfaces
5
Digital interfaces
The ASM330LHB offers two communication protocols I²C / MIPI I3CSM slave interface or SPI (3- and 4-wire)
serial interface.
Figure 7. Reference design - block diagram, I²C communication protocol
INT1
INT2
VDD1
VDD2
ASM330LHB - 1
I2C/I3C
ASM330LHB - 2
I2C/I3C
MCU
INT3
INT4
Figure 8. Reference design - block diagram, SPI4 communication protocol
INT1
INT2
VDD1
ASM330LHB - 1
3
SPI
VDD2
ASM330LHB - 2
3
CS1
3
MCU
CS2
INT3
INT4
DS13773 - Rev 7
page 18/131
ASM330LHB
I²C/SPI interface
5.1
I²C/SPI interface
The registers embedded inside the ASM330LHB may be accessed through both the I²C and SPI serial interfaces.
The latter may be software-configured to operate either in 3-wire or 4-wire interface mode. The device is
compatible with SPI modes 0 and 3.
The serial interfaces are mapped onto the same pins. To select/exploit the I²C interface, the CS line must be tied
high (that is, connected to Vdd_IO).
Table 9. Serial interface pin description
Pin name
Pin description
Enable SPI
CS
I²C/SPI mode selection (1: SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
I²C serial clock (SCL)
SCL/SPC
SPI serial port clock (SPC)
I²C serial data (SDA)
SDA/SDI/SDO
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
SDO/SA0
5.1.1
SPI serial data output (SDO)
I²C less significant bit of the device address
I²C serial interface
The ASM330LHB I²C is a bus slave. The I²C is employed to write the data to the registers, whose content can
also be read back.
The relevant I²C terminology is provided in the table below.
Table 10. I²C terminology
Term
Transmitter
Receiver
Description
The device which sends data to the bus
The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a transfer
Slave
The device addressed by the master
There are two signals associated with the I²C bus: the serial clock line (SCL) and the serial data line (SDA). The
latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines must be
connected to Vdd_IO through external pull-up resistors. When the bus is free, both the lines are high.
The I²C interface is implemeted with fast mode (400 kHz) I²C standards as well as with the standard mode.
In order to disable the I²C block, (I2C_disable) = 1 must be written in CTRL4_C (13h).
DS13773 - Rev 7
page 19/131
ASM330LHB
I²C/SPI interface
5.1.1.1
I²C operation
The transaction on the bus is started through a start (ST) signal. A start condition is defined as a high to low
transition on the data line while the SCL line is held high. After this has been transmitted by the master, the bus
is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in
the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits after a start condition
with its address. If they match, the device considers itself addressed by the master.
The slave address (SAD) associated to the ASM330LHB is 110101xb. The SDO/SA0 pin can be used to modify
the less significant bit of the device address. If the SDO/SA0 pin is connected to the supply voltage, LSb is 1
(address 1101011b); else if the SDO/SA0 pin is connected to ground, the LSb value is 0 (address 1101010b). This
solution permits to connect and address two different inertial modules to the same I²C bus.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge
pulse. The receiver must then pull the data line low so that it remains stable low during the high period of the
acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each
byte of data received.
The I²C embedded inside the ASM330LHB behaves like a slave device and the following protocol must be
adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been
returned, an 8-bit subaddress (SUB) is transmitted. The increment of the address is configured by CTRL3_C
(12h) (IF_INC).
The slave address is completed with a read/write bit. If the bit is 1 (read), a repeated start (SR) condition
must be issued after the two subaddress bytes; if the bit is 0 (write) the master transmits to the slave with
direction unchanged. Table 11 explains how the SAD+read/write bit pattern is composed, listing all the possible
configurations.
Table 11. SAD+read/write patterns
Command
SAD[6:1]
SAD[0] = SA0
R/W
SAD+R/W
Read
110101
0
1
11010101 (D5h)
Write
110101
0
0
11010100 (D4h)
Read
110101
1
1
11010111 (D7h)
Write
110101
1
0
11010110 (D6h)
Table 12. Transfer when master is writing one byte to slave
Master
ST
SAD + W
SUB
Slave
DATA
SAK
SP
SAK
SAK
Table 13. Transfer when master is writing multiple bytes to slave
Master
ST
SAD + W
SUB
Slave
SAK
DATA
SAK
DATA
SP
SAK
SAK
Table 14. Transfer when master is receiving (reading) one byte of data from slave
Master
ST
SAD + W
Slave
SUB
SAK
SR
SAD + R
SAK
NMAK
SAK
SP
DATA
Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave
Master
ST
Slave
DS13773 - Rev 7
SAD+W
SUB
SAK
SR
SAK
SAD+R
MAK
SAK
DATA
MAK
DATA
NMAK
SP
DATA
page 20/131
ASM330LHB
I²C/SPI interface
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred
per transfer is unlimited. Data is transferred with the most significant bit (MSb) first. If a slave receiver doesn’t
acknowledge the slave address (that is, it is not able to receive because it is performing some real-time function)
the data line must be left high by the slave. The master can then abort the transfer. A low to high transition on the
SDA line while the SCL line is high is defined as a stop condition. Each data transfer must be terminated by the
generation of a stop (SP) condition.
In the presented communication format MAK is master acknowledge and NMAK is no master acknowledge.
5.1.2
SPI bus interface
The ASM330LHB SPI is a bus slave. The SPI allows writing to and reading from the registers of the device.
The serial interface communicates to the application using 4 wires: CS, SPC, SDI and SDO.
Figure 9. Read and write protocol (in mode 3)
CS
SPC
SDI
RW
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS enables the serial port and it is controlled by the SPI master. It goes low at the start of the transmission and
goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high
when CS is high (no transmission). SDI and SDO are, respectively, the serial port data input and output. Those
lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC.
Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case
of multiple read/write bytes. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at
the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling
edge of SPC just before the rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is
read. In the latter case, the chip drives SDO at the start of bit 8.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods are added. When the CTRL3_C (12h) (IF_INC)
bit is 0, the address used to read/write data remains the same for every block. When the CTRL3_C (12h)
(IF_INC) bit is 1, the address used to read/write data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.
DS13773 - Rev 7
page 21/131
ASM330LHB
I²C/SPI interface
5.1.2.1
SPI read
Figure 10. SPI read protocol (in mode 3)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI read command is performed with 16 clock pulses. A multiple byte read command is performed by adding
blocks of 8 clock pulses to the previous one.
bit 0: READ bit. The value is 1.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
bit 16-...: data DO(...-8). Further data in multiple byte reads.
Figure 11. Multiple byte SPI read protocol (2-byte example) (in mode 3)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14DO13DO12 DO11DO10 DO9 DO8
DS13773 - Rev 7
page 22/131
ASM330LHB
I²C/SPI interface
5.1.2.2
SPI write
Figure 12. SPI write protocol (in mode 3)
CS
SPC
SDI
RW
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
AD6 AD5 AD4 AD3 AD2 AD1 AD0
The SPI write command is performed with 16 clock pulses. A multiple byte write command is performed by adding
blocks of 8 clock pulses to the previous one.
bit 0: WRITE bit. The value is 0.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written inside the device (MSb first).
bit 16-... : data DI(...-8). Further data in multiple byte writes.
Figure 13. Multiple byte SPI write protocol (2-byte example) (in mode 3)
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DS13773 - Rev 7
page 23/131
ASM330LHB
I²C/SPI interface
5.1.2.3
SPI read in 3-wire mode
A 3-wire mode is entered by setting the CTRL3_C (12h) (SIM) bit equal to 1 (SPI serial interface mode selection).
Figure 14. SPI read protocol in 3-wire mode (in mode 3)
CS
SPC
SDI/O
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
The SPI read command is performed with 16 clock pulses:
bit 0: READ bit. The value is 1.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
A multiple read command is also available in 3-wire mode.
DS13773 - Rev 7
page 24/131
ASM330LHB
MIPI I3CSM interface
5.2
MIPI I3CSM interface
5.2.1
MIPI I3CSM slave interface
The ASM330LHB interface includes a MIPI I3CSM SDR only slave interface with MIPI I3CSM SDR embedded
features:
•
•
•
•
•
•
•
CCC command
Direct CCC communication (SET and GET)
Broadcast CCC communication
Private communications
Private read and write for single byte
Multiple read and write
Error detection and recovery methods
Refer to Section 5.3 I²C/I3C coexistence in ASM330LHB for details concerning the choice of the interface when
powering up the device.
5.2.2
MIPI I3CSM CCC supported commands
The list of MIPI I3CSM CCC commands supported by the device is detailed in the following table.
Table 16. MIPI I3CSM CCC commands
Command
Command code Default
Description
ENTDAA
0x07
DAA procedure
SETDASA
0x87
Assign dynamic address using static address 0x6B/0x6A depending on SDO pin
ENEC
0x80 / 0x00
Slave activity control (direct and broadcast)
DISEC
0x81/ 0x01
Slave activity control (direct and broadcast)
ENTAS0
0x82 / 0x02
Enter activity state (direct and broadcast)
ENTAS1
0x83 / 0x03
Enter activity state (direct and broadcast)
ENTAS2
0x84 / 0x04
Enter activity state (direct and broadcast)
ENTAS3
0x85 / 0x05
Enter activity state (direct and broadcast)
RSTDAA
0x86 / 0x06
Reset the assigned dynamic address (direct and broadcast)
SETMWL
0x89 / 0x08
Define maximum write length during private write (direct and broadcast)
SETMRL
0x8A / 0x09
Define maximum read length during private read (direct and broadcast)
SETNEWDA
0x88
GETMWL
0x8B
Change dynamic address
0x00
0x08
Get maximum write length during private write
(2 byte)
0x00
GETMRL
0x8C
0x10
0x09
Get maximum read length during private read
(3 byte)
0x02
0x08
GETPID
0x8D
0x00
0x6B
Device ID register
0x10
0x0B
DS13773 - Rev 7
page 25/131
ASM330LHB
MIPI I3CSM interface
Command
Command code Default
GETBCR
0x8E
GETDCR
0x8F
GETSTATUS
0x90
0x07
(1 byte)
0x00
Description
Bus characteristics register
MIPI I3CSM device characteristics register
0x00
0x00
Status register
(2 byte)
0x00
GETMXDS
0x94
0x38
Return max data speed(1)
(2 byte)
1. Bits[5:3] are set to "111" which indicates that Tsco is greater than 12 nsec. To calculate the effective bus frequency, Tsco
should be used together with line capacitance, number of slaves and stubs (if present).
DS13773 - Rev 7
page 26/131
ASM330LHB
I²C/I3C coexistence in ASM330LHB
5.3
I²C/I3C coexistence in ASM330LHB
In the ASM330LHB, the SDA and SCL lines are common to both I²C and I3C. The I²C bus requires anti-spike
filters on the SDA and SCL pins that are not compatible with I3C timing.
The device can be connected to both I²C and I3C or only to the I3C bus depending on the connection of the INT1
pin when the device is powered up:
•
•
INT1 pin floating (internal pull-down): I²C/I3C both active, see Figure 15
INT1 pin connected to Vdd_IO: only I3C active, see Figure 16
Figure 15. I²C and I3C both active (INT1 pin not connected)
1.
Address assignment (DAA or ENTDA) must be performed with I²C fast mode plus timing. When the slave is
addressed, the I²C slave is disabled and the timing is compatible with I3C specifications.
Figure 16. Only I3C active (INT1 pin connected to Vdd_IO)
INT1 pin connected to Vdd_IO
Only I3C active
I²C/I3C
I3C bus case
Dynamic
Address
Assignment (1)
Master resets
DA
I3C private R/W with and without 7Eh
CCC commands
Slave event management
Error detection and recovery
1.
DS13773 - Rev 7
When the slave is I3C only, the I²C slave is always disabled. The address can be assigned using I3C SDR
timing.
page 27/131
ASM330LHB
Functionality
6
Functionality
6.1
Operating modes
In the ASM330LHB, the accelerometer and the gyroscope can be turned on/off independently of each other and
are allowed to have different ODRs and power modes.
The ASM330LHB has three operating modes available:
•
•
•
only accelerometer active and gyroscope in power-down or sleep mode
only gyroscope active and accelerometer in power-down
both accelerometer and gyroscope sensors active with independent ODR
The accelerometer is activated from power-down by writing ODR_XL[3:0] in CTRL1_XL (10h) while the gyroscope
is activated from power-down by writing ODR_G[3:0] in CTRL2_G (11h). For combo mode the ODRs are totally
independent.
Note:
If the accelerometer is to be activated in high-performance operating mode while the gyroscope is already
running (that is, the gyroscope is not in power-down mode), proceed as follows:
1.
Disable the accelerometer high-performance operating mode (set the XL_HM_MODE bit to 1 in the
CTRL6_C (15h) register).
2.
Write the CTRL1_XL (10h) register to 50h.
3.
Read the OUTZ_H_A (2Dh) register to clear the XLDA bit in the STATUS_REG (1Eh) register.
4.
Wait for 1/ODR_XL time period or wait until the XLDA bit in the STATUS_REG (1Eh) register becomes
equal to 1.
5.
Enable the accelerometer high-performance operating mode (set the XL_HM_MODE bit to 0 in the
CTRL6_C (15h) register).
6.
Write the CTRL1_XL (10h) register to the desired value.
6.2
Gyroscope power modes
In the ASM330LHB, the gyroscope can be configured in two different operating modes: low-power and highperformance mode. The operating mode selected depends on the value of the G_HM_MODE bit in CTRL7_G
(16h). If G_HM_MODE is set to 0, high-performance mode is valid for all ODRs (from 12.5 Hz up to 1.67 kHz).
To enable low-power mode, the G_HM_MODE bit has to be set to 1. Low-power mode is available for ODRs
equal to 12.5 Hz, 26 Hz, 52 Hz, 104 Hz and 208 Hz.
6.3
Accelerometer power modes
In the ASM330LHB, the accelerometer can be configured in two different operating modes: low-power and highperformance mode. The operating mode selected depends on the value of the XL_HM_MODE bit in CTRL6_C
(15h). If XL_HM_MODE is set to 0, high-performance mode is valid for all ODRs (from 12.5 Hz up to 1.67 kHz).
To enable low-power mode, the XL_HM_MODE bit has to be set to 1. Low-power mode is available for ODRs
equal to 1.6 Hz, 12.5 Hz, 26 Hz, 52 Hz, 104 Hz and 208 Hz.
DS13773 - Rev 7
page 28/131
ASM330LHB
Block diagram of filters
6.4
Block diagram of filters
Figure 17. Block diagram of filters
M
E
M
S
S
E
N
S
O
R
Gyro
front-end
XL
front-end
ADC2
Low Pass
Gyro
Low Pass
XL
Regs
array,
FIFO
I2C/SPI/
MIPI I3CSM
interface
Interrupt
mng
CS
SCL/SPC
SDA/SDI/SDO
SDO/SA0
INT1
INT2
Temperature
sensor
Voltage and current
references
DS13773 - Rev 7
ADC1
Trimming circuit
and Test interface
Clock and phase
generator
Power
management
FTP
page 29/131
ASM330LHB
Block diagram of filters
6.4.1
Block diagram of the gyroscope filter
The gyroscope filtering chain appears below.
Figure 18. Gyroscope filtering chain
SPI/I 2C/
MIPI I3CSM
ADC
0
0
LPF2
HPF
1
LPF1
FIFO
1
ODR_G[3:0]
HP_EN_G
FTYPE [2:0]
LPF1_SEL_G
FSM/MLC
The gyroscope ODR is selectable from 12.5 Hz up to 1.67 kHz. A low-pass filter (LPF1) is available, for more
details about the filter characteristics see Table 58. Gyroscope LPF1 bandwidth selection. The digital LPF2 filter
cannot be configured by the user and its cutoff frequency depends on the selected gyroscope ODR, as indicated
in the following table.
Data can be acquired from the output registers and FIFO.
Table 17. Gyroscope LPF2 bandwidth selection
DS13773 - Rev 7
Gyroscope ODR [Hz]
LPF2 cutoff [Hz]
12.5
4.3
26
8.3
52
16.7
104
33
208
67
417
133
833
267
1667
539
page 30/131
ASM330LHB
Block diagram of filters
6.4.2
Block diagrams of the accelerometer filters
In the ASM330LHB, the filtering chain for the accelerometer part is composed of the following:
•
•
Digital filter (LPF1)
Composite filter
Details of the block diagram appear in the following figure.
Figure 19. Accelerometer chain
Digital
LP Filter
LPF1
Composite
Filter
ADC
ODR_XL[3:0]
Figure 20. Accelerometer composite filter
Free-fall
LOW_PASS_ON_6D
0
FSM/MLC
1
LPF2_XL_EN
USR_OFF_ON_OUT
HP_SLOPE_XL_EN
0
0
Digital
LP Filter
1
LPF1
output (1)
1
USR_OFF_W
OFS_USR[7:0]
HPCF_XL[2:0]
Digital
HP Filter
0
USER
OFFSET
LPF2
1
1
0
0
FIFO
Wake-up
Activity /
Inactivity
SPI/I 2C/
USR_OFF_ON_WU SLOPE_FDS
001
010
…
111
HPCF_XL[2:0]
SLOPE
FILTER
6D/4D
MIPI I3CSM
1
000
HPCF_XL[2:0]
1.
DS13773 - Rev 7
The cutoff value of the LPF1 output is ODR/2 when the accelerometer is in high-performance mode and
ODR up to 833 Hz. This value is equal to 780 Hz when the accelerometer is in low-power mode.
page 31/131
ASM330LHB
FIFO
6.5
FIFO
The presence of a FIFO allows consistent power saving for the system since the host processor does not need
continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out
from the FIFO.
The ASM330LHB embeds 3 KB of data in FIFO to store the following data:
•
•
•
•
Gyroscope
Accelerometer
Timestamp
Temperature
Writing data in the FIFO is triggered by the accelerometer / gyroscope data-ready signal.
The applications have maximum flexibility in choosing the rate of batching for physical sensors with FIFOdedicated configurations: accelerometer, gyroscope and temperature sensor batch rates can be selected by the
user. It is possible to select decimation for timestamp batching in FIFO with a factor of 1, 8, or 32.
The reconstruction of a FIFO stream is a simple task thanks to the FIFO_DATA_OUT_TAG byte that allows
recognizing the meaning of a word in FIFO.
FIFO allows correct reconstruction of the timestamp information for each sensor stored in FIFO. If a change in the
ODR or BDR (batch data rate) configuration is performed, the application can correctly reconstruct the timestamp
and know exactly when the change was applied without disabling FIFO batching. FIFO stores information of the
new configuration and timestamp in which the change was applied in the device.
The programmable FIFO watermark threshold can be set in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h) using the
WTM[8:0] bits. To monitor the FIFO status, dedicated registers (FIFO_STATUS1 (3Ah), FIFO_STATUS2 (3Bh))
can be read to detect FIFO overrun events, FIFO full status, FIFO empty status, FIFO watermark status and the
number of unread samples stored in the FIFO. To generate dedicated interrupts on the INT1 and INT2 pins of
these status events, the configuration can be set in INT1_CTRL (0Dh) and INT2_CTRL (0Eh).
The FIFO buffer can be configured according to six different modes:
•
•
•
•
•
•
Bypass mode
FIFO mode
Continuous mode
Continuous-to-FIFO mode
Bypass-to-continuous mode
Bypass-to-FIFO mode
Each mode is selected by the FIFO_MODE_[2:0] bits in the FIFO_CTRL4 (0Ah) register.
6.5.1
Bypass mode
In bypass mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 000), the FIFO is not operational and it remains empty.
Bypass mode is also used to reset the FIFO when in FIFO mode.
DS13773 - Rev 7
page 32/131
ASM330LHB
FIFO
6.5.2
FIFO mode
In FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 001) data from the output channels are stored in the
FIFO until it is full.
To reset FIFO content, bypass mode should be selected by writing FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0])
to 000. After this reset command, it is possible to restart FIFO mode by writing FIFO_CTRL4 (0Ah)
(FIFO_MODE_[2:0]) to 001.
The FIFO buffer memorizes up to 3 KB of data but the depth of the FIFO can be resized by setting the WTM[8:0]
bits in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h). If the STOP_ON_WTM bit in FIFO_CTRL2 (08h) is set to 1,
FIFO depth is limited up to the WTM[8:0] bits in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h).
6.5.3
Continuous mode
Continuous mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 110) provides a continuous FIFO update: as new
data arrives, the older data is discarded.
A FIFO threshold flag FIFO_STATUS2 (3Bh)(FIFO_WTM_IA) is asserted when the number of unread samples in
FIFO is greater than or equal to FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h) (WTM[8:0]).
It is possible to route the FIFO_WTM_IA flag to the INT1 pin by writing in register INT1_CTRL (0Dh)
(INT1_FIFO_TH) = 1 or to the INT2 pin by writing in register INT2_CTRL (0Eh)(INT2_FIFO_TH) = 1.
A full-flag interrupt can be enabled, INT1_CTRL (0Dh)(INT1_FIFO_FULL) = 1 or INT2_CTRL (0Eh)
(INT2_FIFO_FULL) = 1, in order to indicate FIFO saturation and eventually read its content all at once.
If an overrun occurs, at least one of the oldest samples in FIFO has been overwritten and the FIFO_OVR_IA flag
in FIFO_STATUS2 (3Bh) is asserted.
In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples
available in FIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh)(DIFF_FIFO_[9:0]).
6.5.4
Continuous-to-FIFO mode
In continuous-to-FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 011), FIFO behavior changes according to
the trigger event detected in one of the following interrupt events:
•
•
•
Wake-up
Free-fall
D6D
When the selected trigger bit is equal to 1, FIFO operates in FIFO mode.
When the selected trigger bit is equal to 0, FIFO operates in continuous mode.
6.5.5
Bypass-to-continuous mode
In bypass-to-continuous mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 100), data measurement storage inside
FIFO operates in continuous mode when selected triggers are equal to 1, otherwise FIFO content is reset (bypass
mode).
FIFO behavior changes according to the trigger event detected in one of the following interrupt events:
•
•
•
6.5.6
Wake-up
Free-fall
D6D
Bypass-to-FIFO mode
In bypass-to-FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 111), data measurement storage inside FIFO
operates in FIFO mode when selected triggers are equal to 1, otherwise FIFO content is reset (bypass mode).
FIFO behavior changes according to the trigger event detected in one of the following interrupt events:
•
•
•
DS13773 - Rev 7
Wake-up
Free-fall
D6D
page 33/131
ASM330LHB
FIFO
6.5.7
FIFO reading procedure
The data stored in FIFO are accessible from dedicated registers and each FIFO word is composed of 7
bytes: one tag byte (FIFO_DATA_OUT_TAG (78h), in order to identify the sensor, and 6 bytes of fixed data
(FIFO_DATA_OUT registers from (79h) to (7Eh)).
The DIFF_FIFO_[9:0] field in the FIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh) registers contains the number
of words (1 byte TAG + 6 bytes DATA) collected in FIFO.
In addition, it is possible to configure a counter of the batch events of accelerometer or gyroscope sensors.
The flag COUNTER_BDR_IA in FIFO_STATUS2 (3Bh) alerts that the counter reaches a selectable threshold
(CNT_BDR_TH_[10:0] field in COUNTER_BDR_REG1 (0Bh) and COUNTER_BDR_REG2 (0Ch)). This allows
triggering the reading of FIFO with the desired latency of one single sensor. The sensor is selectable using
the TRIG_COUNTER_BDR bit in COUNTER_BDR_REG1 (0Bh). As for the other FIFO status events, the flag
COUNTER_BDR_IA can be routed to the INT1 or INT2 pins by asserting the corresponding bits (INT1_CNT_BDR
of INT1_CTRL (0Dh) and INT2_CNT_BDR of INT2_CTRL (0Eh)).
Meta information about accelerometer and gyroscope sensor configuration changes can be managed by enabling
the ODR_CHG_EN bit in FIFO_CTRL2 (08h).
DS13773 - Rev 7
page 34/131
ASM330LHB
Application hints
7
Application hints
7.1
ASM330LHB electrical connections
14
CS
SCL
SDA
Figure 21. ASM330LHB electrical connections
HOST
12
I 2C /
SM
GND or Vdd_IO
11
1
TOP
VIEW
RES
RES
INT1
4
8
C2
7
NC
(2)
Vdd_IO
5
NC
NC
GND
SDO/SA0
MIPI I3C /
SPI (3/4-w)
(1)
(1)
Vdd
C1
100 nF
I2C configuration
GND
Vdd_IO
Rpu
Vdd_IO
100 nF
GND
Vdd_IO: Recommended 100 nF filter capacitor.
Vdd: Recommended 100 nF plus 10 μF capacitors.
1.
2.
ASM330LHB
Vdd
INT2
Rpu
SCL
SDA
Pull-up to be added
Rpu=10kOhm
Leave pin electrically unconnected and soldered to PCB.
Connect to Vdd_IO or GND or leave unconnected and soldered to PCB.
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic)
should be placed as near as possible to the supply pin of the device (common design practice).
The functionality of the device and the measured acceleration/angular rate data is selectable and accessible
through the SPI/I²C/MIPI I3CSM primary interface.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely
programmed by the user through the SPI/I²C/MIPI I3CSM primary interface.
DS13773 - Rev 7
page 35/131
ASM330LHB
ASM330LHB electrical connections
Table 18. Internal pin status
Pin #
1
Name
Pin function
SDO
SPI 4-wire interface serial data output (SDO)
SA0
Pin status
I²C least significant bit of the device address (SA0)
MIPI I3CSM least significant bit of the static address (SA0)
Default: input without pull-up
Pull-up is enabled if bit SDO_PU_EN = 1 in register PIN_CTRL (02h).
2
MSDA
Connect to Vdd_IO or GND
Default: input without pull-up (see Note to enable pull-up)
3
MSCL
Connect to Vdd_IO or GND
Default: input without pull-up (see Note to enable pull-up)
INT1
Programmable interrupt 1.
Default: input with pull-down(1)
4
If device is used as MIPI I3CSM pure slave, this pin must be set to 1.
Pull-down is disabled if bit PD_DIS_INT1 = 1 in register I3C_BUS_AVB
(62h).
5
Vdd_IO
Power supply for I/O pins
6
NC
Connect to Vdd_IO or GND or leave unconnected
7
GND
0 V supply
8
Vdd
Power supply
9
INT2
Programmable interrupt 2 (INT2) / data enabled (DEN)
10
NC
Leave unconnected
11
NC
Leave unconnected
Default: output forced to ground
I²C and MIPI I3CSM/SPI mode selection
12
13
CS
SCL
(1:SPI idle mode / I²C and MIPI
I3CSM
communication enabled;
Default: input with pull-up
Pull-up is disabled if bit I2C_disable = 1 in register CTRL4_C (13h)
0: SPI communication mode / I²C and MIPI I3CSM disabled)
and I3C_disable = 1 in register CTRL9_XL (18h).
I²C/MIPI I3CSM serial clock (SCL) / SPI serial port clock (SPC)
Default: input without pull-up
I²C/MIPI I3CSM serial data (SDA) /
14
SDA
SPI serial data input (SDI) /
Default: input without pull-up
3-wire interface serial data output (SDO)
1. INT1 must be set to 0 or left unconnected during power-on if the I²C/SPI interfaces are used.
Internal pull-up value is from 30 kΩ to 50 kΩ, depending on Vdd_IO.
Note:
DS13773 - Rev 7
The procedure to enable the pull-up on pins 2 and 3 is as follows:
1. From the primary I²C/I3C/SPI interface: write 40h in register at address 01h
2. From the primary I²C/I3C/SPI interface: write 08h in register at address 14h (enable the pull-up on pins 2 and 3)
3. From the primary I²C/I3C/SPI interface: write 00h in register at address 01h
page 36/131
ASM330LHB
Register map
8
Register map
The table given below provides a list of the 8/16-bit registers embedded in the device and the corresponding
addresses.
Table 19. Registers address map
Name
Type
FUNC_CFG_ACCESS
PIN_CTRL
Register address
Default
Hex
Binary
R/W
01
00000001
00000000
R/W
02
00000010
00111111
RESERVED
-
03-06
FIFO_CTRL1
R/W
07
00000111
00000000
FIFO_CTRL2
R/W
08
00001000
00000000
FIFO_CTRL3
R/W
09
00001001
00000000
FIFO_CTRL4
R/W
0A
00001010
00000000
COUNTER_BDR_REG1
R/W
0B
00001011
00000000
COUNTER_BDR_REG2
R/W
0C
00001100
00000000
INT1_CTRL
R/W
0D
00001101
00000000
INT2_CTRL
R/W
0E
00001110
00000000
WHO_AM_I
R
0F
00001111
01101011
CTRL1_XL
R/W
10
00010000
00000000
CTRL2_G
R/W
11
00010001
00000000
CTRL3_C
R/W
12
00010010
00000100
CTRL4_C
R/W
13
00010011
00000000
CTRL5_C
R/W
14
00010100
00000000
CTRL6_C
R/W
15
00010101
00000000
CTRL7_G
R/W
16
00010110
00000000
CTRL8_XL
R/W
17
00010111
00000000
CTRL9_XL
R/W
18
00011000
11100000
CTRL10_C
R/W
19
00011001
00000000
ALL_INT_SRC
R
1A
00011010
output
WAKE_UP_SRC
R
1B
00011011
output
RESERVED
-
1C
D6D_SRC
R
1D
00011101
output
STATUS_REG
R
1E
00011110
output
RESERVED
-
1F
OUT_TEMP_L
R
20
00100000
output
OUT_TEMP_H
R
21
00100001
output
OUTX_L_G
R
22
00100010
output
OUTX_H_G
R
23
00100011
output
OUTY_L_G
R
24
00100100
output
OUTY_H_G
R
25
00100101
output
OUTZ_L_G
R
26
00100110
output
DS13773 - Rev 7
Comment
Reserved
Reserved
Reserved
page 37/131
ASM330LHB
Register map
Name
Type
Register address
Hex
Binary
Default
OUTZ_H_G
R
27
00100111
output
OUTX_L_A
R
28
00101000
output
OUTX_H_A
R
29
00101001
output
OUTY_L_A
R
2A
00101010
output
OUTY_H_A
R
2B
00101011
output
OUTZ_L_A
R
2C
00101100
output
OUTZ_H_A
R
2D
00101101
output
RESERVED
-
2E-34
EMB_FUNC_STATUS_MAINPAGE
R
35
00110101
output
FSM_STATUS_A_MAINPAGE
R
36
00110110
output
FSM_STATUS_B_MAINPAGE
R
37
00110111
output
MLC_STATUS_MAINPAGE
R
38
00111000
output
RESERVED
-
39
FIFO_STATUS1
R
3A
00111010
output
FIFO_STATUS2
R
3B
00111011
output
RESERVED
-
3C-3F
TIMESTAMP0_REG
R
40
01000000
output
TIMESTAMP1_REG
R
41
01000001
output
TIMESTAMP2_REG
R
42
01000010
output
TIMESTAMP3_REG
R
43
01000011
output
RESERVED
-
44-55
R/W
56
-
57
INT_CFG1
R/W
58
01011000
00000000
THS_6D
R/W
59
01011001
00000000
-
5A
WAKE_UP_THS
R/W
5B
01011011
00000000
WAKE_UP_DUR
R/W
5C
01011100
00000000
FREE_FALL
R/W
5D
01011101
00000000
MD1_CFG
R/W
5E
01011110
00000000
MD2_CFG
R/W
5F
01011111
00000000
-
60-61
R/W
62
01100010
00000000
INTERNAL_FREQ_FINE
R
63
01100011
output
RESERVED
-
64-72
X_OFS_USR
R/W
73
01110011
00000000
Y_OFS_USR
R/W
74
01110100
00000000
Z_OFS_USR
R/W
75
01110101
00000000
RESERVED
-
76-77
FIFO_DATA_OUT_TAG
R
78
INT_CFG0
RESERVED
RESERVED
RESERVED
I3C_BUS_AVB
DS13773 - Rev 7
Comment
Reserved
Reserved
Reserved
Reserved
01010110
00000000
Reserved
Reserved
00000000
Reserved
Reserved
Reserved
01111000
output
page 38/131
ASM330LHB
Register map
Name
Type
Register address
Hex
Binary
Default
FIFO_DATA_OUT_X_L
R
79
01111001
output
FIFO_DATA_OUT_X_H
R
7A
01111010
output
FIFO_DATA_OUT_Y_L
R
7B
01111011
output
FIFO_DATA_OUT_Y_H
R
7C
01111100
output
FIFO_DATA_OUT_Z_L
R
7D
01111101
output
FIFO_DATA_OUT_Z_H
R
7E
01111110
output
Comment
Reserved registers must not be changed. Writing to those registers may cause permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration
values. Their content is automatically restored when the device is powered up.
DS13773 - Rev 7
page 39/131
ASM330LHB
Register description
9
Register description
The device contains a set of registers which are used to control its behavior and to retrieve linear acceleration,
angular rate and temperature data. The register addresses, made up of 7 bits, are used to identify them and to
write data through the serial interface.
9.1
FUNC_CFG_ACCESS (01h)
Enable embedded functions register (R/W)
Table 20. FUNC_CFG_ACCESS register
FUNC_CFG_
ACCESS
0(1)
0(1)
0(1)
0(1)
0(1)
0(1)
0(1)
1. This bit must be set to 0 for the correct operation of the device.
Table 21. FUNC_CFG_ACCESS register description
Enable access to the embedded functions configuration registers.
Default value: 0(1)
FUNC_CFG_ACCESS
1. Details concerning the embedded functions configuration registers are available in Section 10 Embedded functions register
mapping and Section 11 Embedded functions register description.
9.2
PIN_CTRL (02h)
Enable/disable SDO pin pull-up register (R/W)
Table 22. PIN_CTRL register
0(1)
SDO_
PU_EN
1(2)
1(2)
1(2)
1(2)
1(2)
1(2)
1. This bit must be set to 0 for the correct operation of the device.
2. This bit must be set to 1 for the correct operation of the device.
Table 23. PIN_CTRL register description
SDO_PU_EN
DS13773 - Rev 7
Enable pull-up on SDO pin. Default value: 0
(0: SDO pin pull-up disconnected (default); 1: SDO pin with pull-up)
page 40/131
ASM330LHB
FIFO_CTRL1 (07h)
9.3
FIFO_CTRL1 (07h)
FIFO control register 1 (R/W)
Table 24. FIFO_CTRL1 register
WTM7
WTM6
WTM5
WTM4
WTM3
WTM2
WTM1
WTM0
Table 25. FIFO_CTRL1 register description
FIFO watermark threshold, in conjunction with WTM8 in FIFO_CTRL2 (08h)
WTM[7:0] 1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO
Watermark flag rises when the number of bytes written in the FIFO is greater than or equal to the threshold level.
9.4
FIFO_CTRL2 (08h)
FIFO control register 2 (R/W)
Table 26. FIFO_CTRL2 register
STOP_ON
_WTM
0(1)
0(1)
ODRCHG
_EN
0(1)
0(1)
0(1)
WTM8
1. This bit must be set to 0 for the correct operation of the device.
Table 27. FIFO_CTRL2 register
Sensing chain FIFO stop values memorization at threshold level
STOP_ON_WTM (0: FIFO depth is not limited (default);
1: FIFO depth is limited to the threshold level, defined in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h)
ODRCHG_EN
Enables ODR CHANGE virtual sensor to be batched in FIFO
FIFO watermark threshold, in conjunction with WTM[7:0] in FIFO_CTRL1 (07h)
WTM8
1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO
Watermark flag rises when the number of bytes written in FIFO is greater than or equal to the threshold
level.
DS13773 - Rev 7
page 41/131
ASM330LHB
FIFO_CTRL3 (09h)
9.5
FIFO_CTRL3 (09h)
FIFO control register 3 (R/W)
Table 28. FIFO_CTRL3 register
BDR_GY_3
BDR_GY_2
BDR_GY_1
BDR_GY_0
BDR_XL_3
BDR_XL_2
BDR_XL_1
BDR_XL_0
Table 29. FIFO_CTRL3 register description
Selects batch data rate (write frequency in FIFO) for gyroscope data.
(0000: Gyroscopte not batched in FIFO (default);
0001: 12.5 Hz;
0010: 26 Hz;
0011: 52 Hz;
0100: 104 Hz;
BDR_GY_[3:0]
0101: 208 Hz;
0110: 417 Hz;
0111: 833 Hz;
1000: 1667 Hz;
1001: reserved;
1010: reserved;
1011: 6.5 Hz;
1100-1111: reserved)
Selects batch data rate (write frequency in FIFO) for accelerometer data.
(0000: Accelerometer not batched in FIFO (default);
0001: 12.5 Hz;
0010: 26 Hz;
0011: 52 Hz;
0100: 104 Hz;
BDR_XL_[3:0]
0101: 208 Hz;
0110: 417 Hz;
0111: 833 Hz;
1000: 1667 Hz;
1001: reserved;
1010: reserved;
1011: 1.6 Hz;
1100-1111: reserved)
DS13773 - Rev 7
page 42/131
ASM330LHB
FIFO_CTRL4 (0Ah)
9.6
FIFO_CTRL4 (0Ah)
FIFO control register 4 (R/W)
Table 30. FIFO_CTRL4 register
DEC_TS_
BATCH_1
DEC_TS_
BATCH_0
ODR_T_
BATCH_1
ODR_T_
BATCH_0
0(1)
FIFO_
MODE2
FIFO_
MODE1
FIFO_
MODE0
1. This bit must be set to 0 for the correct operation of the device.
Table 31. FIFO_CTRL4 register description
Selects decimation for timestamp batching in FIFO. The write rate is the maximum rate between the
accelerometer and gyroscope BDR divided by decimation decoder.
(00: timestamp not batched in FIFO (default);
DEC_TS_BATCH_[1:0]
01: decimation 1: max(BDR_XL[Hz],BDR_GY[Hz]) [Hz];
10: decimation 8: max(BDR_XL[Hz],BDR_GY[Hz])/8 [Hz];
11: decimation 32: max(BDR_XL[Hz],BDR_GY[Hz])/32 [Hz])
Selects batch data rate (write frequency in FIFO) for temperature data
(00: temperature not batched in FIFO (default);
ODR_T_BATCH_[1:0]
01: 1.6 Hz;
10: 12.5 Hz;
11: 52 Hz)
FIFO mode selection
(000: bypass mode: FIFO disabled;
001: FIFO mode: stops collecting data when FIFO is full;
010: reserved;
FIFO_MODE[2:0]
011: continuous-to-FIFO mode: continuous mode until trigger is deasserted, then FIFO mode;
100: bypass-to-continuous mode: bypass mode until trigger is deasserted, then continuous mode;
101: reserved;
110: continuous mode: if the FIFO is full, the new sample overwrites the older one;
111: bypass-to-FIFO mode: bypass mode until trigger is deasserted, then FIFO mode.)
DS13773 - Rev 7
page 43/131
ASM330LHB
COUNTER_BDR_REG1 (0Bh)
9.7
COUNTER_BDR_REG1 (0Bh)
Counter batch data rate register 1 (R/W)
Table 32. COUNTER_BDR_REG1 register
dataready_
pulsed
RST_COUNTER
_BDR
TRIG_COUNTER
_BDR
0(1)
0(1)
CNT_BDR_
TH_10
CNT_BDR_
TH_9
CNT_BDR_
TH_8
1. This bit must be set to 0 for the correct operation of the device.
Table 33. COUNTER_BDR_REG1 register description
Enables pulsed data-ready mode
dataready_pulsed
(0: data-ready latched mode (returns to 0 only after an interface reading) (default);
1: data-ready pulsed mode (the data ready pulses are 75 µs long)
RST_COUNTER_BDR
Resets the internal counter of batch events for a single sensor.
This bit is automatically reset to zero if it was set to 1.
Selects the trigger for the internal counter of batch events between the accelerometer and
gyroscope.
TRIG_COUNTER_BDR
(0: accelerometer batch event;
1: gyroscope batch event)
CNT_BDR_TH_[10:8]
9.8
In conjunction with CNT_BDR_TH_[7:0] in COUNTER_BDR_REG2 (0Ch), sets the threshold for the
internal counter of batch events. When this counter reaches the threshold, the counter is reset and
the COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to 1.
COUNTER_BDR_REG2 (0Ch)
Counter batch data rate register 2 (R/W)
Table 34. COUNTER_BDR_REG2 register
CNT_BDR_
TH_7
CNT_BDR_
TH_6
CNT_BDR_
TH_5
CNT_BDR_
TH_4
CNT_BDR_
TH_3
CNT_BDR_
TH_2
CNT_BDR_
TH_1
CNT_BDR_
TH_0
Table 35. COUNTER_BDR_REG2 register description
In conjunction with CNT_BDR_TH_[10:8] in COUNTER_BDR_REG1 (0Bh), sets the threshold for the
CNT_BDR_TH_[7:0] internal counter of batch events. When this counter reaches the threshold, the counter is reset and the
COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to 1.
DS13773 - Rev 7
page 44/131
ASM330LHB
INT1_CTRL (0Dh)
9.9
INT1_CTRL (0Dh)
INT1 pin control register (R/W)
Each bit in this register enables a signal to be carried over INT1 when the MIPI I3CSM dynamic address is not
assigned (I²C or SPI is used). Some bits can be also used to trigger an IBI (in-band interrupt) when the MIPI
I3CSM interface is used. The output of the pad is the OR combination of the signals selected here and in register
MD1_CFG (5Eh).
Table 36. INT1_CTRL register
DEN_DRDY
_flag
INT1_
CNT_BDR
INT1_
FIFO_FULL
INT1_
FIFO_OVR
INT1_
FIFO_TH
INT1_
BOOT
INT1_
DRDY_G
INT1_
DRDY_XL
Table 37. INT1_CTRL register description
DEN_DRDY_flag
Sends DEN_DRDY (DEN stamped on sensor data flag) to INT1 pin.
INT1_CNT_BDR
Enables COUNTER_BDR_IA interrupt on INT1.
INT1_FIFO_FULL
INT1_FIFO_OVR
INT1_FIFO_TH
INT1_BOOT
INT1_DRDY_G
INT1_DRDY_XL
DS13773 - Rev 7
Enables FIFO full flag interrupt on INT1 pin.
It can be also used to trigger an IBI when the MIPI I3CSM interface is used.
Enables FIFO overrun interrupt on INT1 pin.
It can be also used to trigger an IBI when the MIPI I3CSM interface is used.
Enables FIFO threshold interrupt on INT1 pin.
It can be also used to trigger an IBI when the MIPI I3CSM interface is used.
Enables boot status on INT1 pin.
Enables gyroscope data-ready interrupt on INT1 pin.
It can be also used to trigger an IBI when the MIPI I3CSM interface is used.
Enables accelerometer data-ready interrupt on INT1 pin.
It can be also used to trigger an IBI when the MIPI I3CSM interface is used.
page 45/131
ASM330LHB
INT2_CTRL (0Eh)
9.10
INT2_CTRL (0Eh)
INT2 pin control register (R/W)
Each bit in this register enables a signal to be carried over INT2 when the MIPI I3CSM dynamic address is not
assigned (I²C or SPI is used). Some bits can be also used to trigger an IBI when the MIPI I3CSM interface is used.
The output of the pad is the OR combination of the signals selected here and in register MD2_CFG (5Fh).
Table 38. INT2_CTRL register
0(1)
INT2_
CNT_BDR
INT2_
FIFO_FULL
INT2_
FIFO_OVR
INT2_
FIFO_TH
INT2_
DRDY_TEMP
INT2_
DRDY_G
INT2_
DRDY_XL
1. This bit must be set to 0 for the correct operation of the device.
Table 39. INT2_CTRL register description
INT2_CNT_BDR
Enables COUNTER_BDR_IA interrupt on INT2 pin.
INT2_FIFO_FULL
Enables FIFO full flag interrupt on INT2 pin.
INT2_FIFO_OVR
Enables FIFO overrun interrupt on INT2 pin.
INT2_FIFO_TH
Enables FIFO threshold interrupt on INT2 pin.
Enables temperature sensor data-ready interrupt on INT2 pin.
INT2_DRDY_TEMP It can be also used to trigger an IBI when the MIPI I3CSM interface is used and INT2_ON_INT1 = 1 in
CTRL4_C (13h).
9.11
INT2_DRDY_G
Enables gyroscope data-ready interrupt on INT2 pin.
INT2_DRDY_XL
Enables accelerometer data-ready interrupt on INT2 pin.
WHO_AM_I (0Fh)
WHO_AM_I register (R). This is a read-only register. Its value is fixed at 6Bh.
Table 40. Who_Am_I register
0
DS13773 - Rev 7
1
1
0
1
0
1
1
page 46/131
ASM330LHB
CTRL1_XL (10h)
9.12
CTRL1_XL (10h)
Accelerometer control register 1 (R/W)
Table 41. CTRL1_XL register
ODR_XL3
ODR_XL2
ODR_XL1
ODR_XL0
FS1_XL
FS0_XL
LPF2_XL_EN
0(1)
1. This bit must be set to 0 for the correct operation of the device.
Table 42. CTRL1_XL register description
ODR_XL[3:0]
Accelerometer ODR selection (see Table 43)
Accelerometer full-scale selection. Default value: 00
FS[1:0]_XL
(00: ±2 g; 01: ±16 g; 10: ±4 g; 11: ±8 g)
Accelerometer high-resolution selection
LPF2_XL_EN
(0: output from first stage digital filtering selected (default);
1: output from LPF2 second filtering stage selected)
Table 43. Accelerometer ODR register setting
ODR_XL3 ODR_XL2 ODR_XL1 ODR_XL0
DS13773 - Rev 7
ODR selection [Hz] when
ODR selection [Hz] when
XL_HM_MODE = 1 in CTRL6_C
(15h)
XL_HM_MODE = 0 in CTRL6_C
(15h)
0
0
0
0
Power-down
Power-down
1
0
1
1
1.6 Hz (low power only)
N.A.
0
0
0
1
12.5 Hz (low power)
12.5 Hz (high performance)
0
0
1
0
26 Hz (low power)
26 Hz (high performance)
0
0
1
1
52 Hz (low power)
52 Hz (high performance)
0
1
0
0
104 Hz (low power)
104 Hz (high performance)
0
1
0
1
208 Hz (low power)
208 Hz (high performance)
0
1
1
0
416 Hz (high performance)
416 Hz (high performance)
0
1
1
1
833 Hz (high performance)
833 Hz (high performance)
1
0
0
0
1.67 kHz (high performance)
1.67 kHz (high performance)
1
0
0
1
Reserved
Reserved
1
0
1
0
Reserved
Reserved
1
1
x
x
Reserved
Reserved
page 47/131
ASM330LHB
CTRL2_G (11h)
9.13
CTRL2_G (11h)
Gyroscope control register 2 (R/W)
Table 44. CTRL2_G register
ODR_G3
ODR_G2
ODR_G1
ODR_G0
FS1_G
FS0_G
FS_125
FS_4000
Table 45. CTRL2_G register description
Gyroscope output data rate selection. Default value: 0000
ODR_G[3:0]
(Refer to Table 46)
Gyroscope chain full-scale selection
(00: ±250 dps;
FS[1:0]_G
01: ±500 dps;
10: ±1000 dps;
11: ±2000 dps)
Selects gyroscope chain full-scale ±125 dps
FS_125
(0: FS selected through bits FS[1:0]_G;
1: FS set to ±125 dps)
Selects gyroscope chain full-scale ±4000 dps
FS_4000
(0: FS selected through bits FS[1:0]_G or FS_125;
1: FS set to ±4000 dps)
Table 46. Gyroscope ODR configuration setting
ODR_G3 ODR_G2 ODR_G1 ODR_G0
DS13773 - Rev 7
ODR selection [Hz] when
ODR selection [Hz] when
G_HM_MODE = 1 in CTRL7_G (16h)
G_HM_MODE = 0 in CTRL7_G (16h)
0
0
0
0
Power-down
Power-down
0
0
0
1
12.5 Hz (low power)
12.5 Hz (high performance)
0
0
1
0
26 Hz (low power)
26 Hz (high performance)
0
0
1
1
52 Hz (low power)
52 Hz (high performance)
0
1
0
0
104 Hz (low power)
104 Hz (high performance)
0
1
0
1
208 Hz (low power)
208 Hz (high performance)
0
1
1
0
416 Hz (high performance)
416 Hz (high performance)
0
1
1
1
833 Hz (high performance)
833 Hz (high performance)
1
0
0
0
1.67 kHz (high performance)
1.67 kHz (high performance)
1
0
0
1
Reserved
Reserved
1
0
1
0
Reserved
Reserved
1
0
1
1
Reserved
Reserved
page 48/131
ASM330LHB
CTRL3_C (12h)
9.14
CTRL3_C (12h)
Control register 3 (R/W)
Table 47. CTRL3_C register
BOOT
BDU
H_LACTIVE
PP_OD
SIM
IF_INC
0(1)
SW_RESET
1. This bit must be set to 0 for the correct operation of the device.
Table 48. CTRL3_C register description
Reboots memory content. Default value: 0
BOOT
(0: normal mode; 1: reboot memory content)
Note: the accelerometer must be ON. This bit is automatically cleared.
Block data update. Default value: 0
BDU
(0: continuous update;
1: output registers are not updated until MSB and LSB have been read)
H_LACTIVE
PP_OD
Interrupt activation level. Default value: 0
(0: interrupt output pins active high; 1: interrupt output pins active low
Push-pull/open-drain selection on INT1 and INT2 pins. This bit must be set to 0 when H_LACTIVE is set to 1.
Default value: 0
(0: push-pull mode; 1: open-drain mode)
SIM
IF_INC
SPI serial interface mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface)
Register address automatically incremented during a multiple byte access with a serial interface (I²C or SPI).
Default value: 1
(0: disabled; 1: enabled)
Software reset. Default value: 0
SW_RESET (0: normal mode; 1: reset device)
This bit is automatically cleared.
DS13773 - Rev 7
page 49/131
ASM330LHB
CTRL4_C (13h)
9.15
CTRL4_C (13h)
Control register 4 (R/W)
Table 49. CTRL4_C register
0(1)
SLEEP_G
INT2_on
_INT1
0(1)
DRDY_MASK
I2C_disable
LPF1_SEL_G
0(1)
1. This bit must be set to 0 for the correct operation of the device.
Table 50. CTRL4_C register description
SLEEP_G
Enables gyroscope sleep mode. Default value:0
(0: disabled; 1: enabled)
All interrupt signals available on INT1 pin enable. Default value: 0
INT2_on_INT1 (0: interrupt signals divided between INT1 and INT2 pins;
1: all interrupt signals in logic or on INT1 pin)
Enables data available
DRDY_MASK
(0: disabled;
1: mask DRDY on pin (both accelerometer and gyroscope) until filter settling ends (accelerometer and
gyroscope independently masked).
I2C_disable
LPF1_SEL_G
DS13773 - Rev 7
Disables I²C interface. Default value: 0
(0: SPI, I²C and MIPI I3CSM interfaces enabled (default); 1: I²C interface disabled)
Enables gyroscope digital LPF1; the bandwidth can be selected through FTYPE[2:0] in CTRL6_C (15h).
(0: disabled; 1: enabled)
page 50/131
ASM330LHB
CTRL5_C (14h)
9.16
CTRL5_C (14h)
Control register 5 (R/W)
Table 51. CTRL5_C register
0(1)
ROUNDING1
ROUNDING0
0(1)
ST1_G
ST0_G
ST1_XL
ST0_XL
1. This bit must be set to 0 for the correct operation of the device.
Table 52. CTRL5_C register description
Circular burst-mode (rounding) read of the output registers. Default value: 00
(00: no rounding;
ROUNDING[1:0]
01: accelerometer only;
10: gyroscope only;
11: gyroscope + accelerometer)
Enables angular rate sensor self-test. Default value: 00
ST[1:0]_G
(00: self-test disabled; Other: refer to Table 53)
Enables linear acceleration sensor self-test. Default value: 00
ST[1:0]_XL
(00: self-test disabled; Other: refer to Table 54)
Table 53. Angular rate sensor self-test mode selection
ST1_G
ST0_G
0
0
Normal mode
0
1
Positive sign self-test
1
0
Not allowed
1
1
Negative sign self-test
Self-test mode
Table 54. Linear acceleration sensor self-test mode selection
DS13773 - Rev 7
ST1_XL
ST0_XL
0
0
Normal mode
0
1
Positive sign self-test
1
0
Negative sign self-test
1
1
Not allowed
Self-test mode
page 51/131
ASM330LHB
CTRL6_C (15h)
9.17
CTRL6_C (15h)
Control register 6 (R/W)
Table 55. CTRL6_C register
TRIG_EN
LVL1_EN
LVL2_EN
XL_HM_
MODE
USR_
OFF_W
FTYPE_2
FTYPE_1
FTYPE_0
Table 56. CTRL6_C register description
TRIG_EN
Enables DEN data edge-sensitive trigger mode. Refer to Table 57.
LVL1_EN
Enables DEN data level-sensitive trigger mode. Refer to Table 57.
LVL2_EN
Enables DEN level-sensitive latched mode. Refer toTable 57.
XL_HM_MODE
(0: high-performance operating mode enabled;
Disables high-performance operating mode for accelerometer. Default value: 0
1: high-performance operating mode disabled)
Weight of XL user offset bits of registers X_OFS_USR (73h), Y_OFS_USR (74h), Z_OFS_USR (75h)
USR_OFF_W
(0: 2-10 g/LSB;
1: 2-6 g/LSB)
FTYPE[2:0]
Gyroscope low-pass filter (LPF1) bandwidth selection. Table 58 shows the selectable bandwidth values.
Table 57. Trigger mode selection
TRIG_EN, LVL1_EN, LVL2_EN
Trigger mode
100
Edge-sensitive trigger mode is selected
010
Level-sensitive trigger mode is selected
011
Level-sensitive latched mode is selected
110
Level-sensitive FIFO enable mode is selected
Table 58. Gyroscope LPF1 bandwidth selection
FTYPE[2:0]
12.5 Hz
26 Hz
52 Hz
104 Hz
208 Hz
416 Hz
833 Hz
1.67 kHz
000
4.3
8.3
16.7
33
67
133
222
274
001
4.3
8.3
16.7
33
67
128
186
212
010
4.3
8.3
16.7
33
67
112
140
150
011
4.3
8.3
16.7
33
67
134
260
390
100
4.3
8.3
16.7
34
62
86
96
99
101
4.3
8.3
16.9
31
43
48
49
50
110
4.3
8.3
13.4
19
23
24.6
25
25
111
4.3
8.3
9.8
11.6
12.2
12.4
12.6
12.6
DS13773 - Rev 7
page 52/131
ASM330LHB
CTRL7_G (16h)
9.18
CTRL7_G (16h)
Control register 7 (R/W)
Table 59. CTRL7_G register
G_HM_
MODE
HP_EN_G
HPM1_G
0(1)
HPM0_G
0(1)
USR_OFF_
ON_OUT
0(1)
1. This bit must be set to 0 for the correct operation of the device.
Disables high-performance operating mode for gyroscope. Default: 0
(0: high-performance operating mode enabled;
G_HM_MODE
1: high-performance operating mode disabled)
Enables gyroscope digital high-pass filter. The filter is enabled only if the gyroscope is in HP mode. Default value: 0
HP_EN_G
(0: HPF disabled; 1: HPF enabled)
Gyroscope digital HP filter cutoff selection. Default: 00
(00: 16 mHz;
HPM_G[1:0]
01: 65 mHz;
10: 260 mHz;
11: 1.04 Hz)
Enables accelerometer user offset correction block; it's valid for the low-pass path - see Figure 20 . Default value: 0
USR_OFF_ON_OUT
(0: accelerometer user offset correction block bypassed;
1: accelerometer user offset correction block enabled)
9.19
CTRL8_XL (17h)
Control register 8 (R/W)
Table 60. CTRL8_XL register
HPCF_XL_2
HPCF_XL_1
HPCF_XL_0
HP_REF_
MODE_XL
FASTSETTL_
MODE_XL
HP_SLOPE_
XL_EN
0(1)
LOW_PASS_
ON_6D
1. This bit must be set to 0 for the correct operation of the device.
HPCF_XL_[2:0]
Accelerometer LPF2 and HP filter configuration and cutoff setting. Refer to Table 61.
HP_REF_MODE_XL
Enables accelerometer high-pass filter reference mode (valid for high-pass path HP_SLOPE_XL_EN bit must be 1). Default value: 0(1)
(0: disabled, 1: enabled)
Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the second samples after
FASTSETTL_MODE_XL writing this bit. Active only during device exit from power- down mode. Default value: 0
(0: disabled, 1: enabled)
HP_SLOPE_XL_EN
Accelerometer slope filter / high-pass filter selection. Refer to Figure 22.
LPF2 on 6D function selection. Refer to Figure 22. Default value: 0
LOW_PASS_ON_6D
(0: ODR/2 low-pass filtered data sent to 6D interrupt function;
1: LPF2 output data sent to 6D interrupt function)
1. When enabled, the first output data have to be discarded.
DS13773 - Rev 7
page 53/131
ASM330LHB
CTRL8_XL (17h)
Table 61. Accelerometer bandwidth configurations
Filter type
HP_SLOPE_
LPF2_XL_EN
XL_EN
HPCF_XL_[2:0]
Bandwidth
0
Low pass
0
High pass
1
1
-
-
ODR/2
000
ODR/4
001
ODR/10
010
ODR/20
011
ODR/45
100
ODR/100
101
ODR/200
110
ODR/400
111
ODR/800
000
SLOPE (ODR/4)
001
ODR/10
010
ODR/20
011
ODR/45
100
ODR/100
101
ODR/200
110
ODR/400
111
ODR/800
Figure 22. Accelerometer block diagram
Free-fall
LOW_PASS_ON_6D
0
FSM/MLC
1
LPF2_XL_EN
USR_OFF_ON_OUT
HP_SLOPE_XL_EN
0
0
Digital
LP Filter
1
LPF1
output (1)
1
USR_OFF_W
OFS_USR[7:0]
HPCF_XL[2:0]
Digital
HP Filter
0
USER
OFFSET
LPF2
1
1
0
0
FIFO
Wake-up
Activity /
Inactivity
SPI/I 2C/
USR_OFF_ON_WU SLOPE_FDS
001
010
…
111
HPCF_XL[2:0]
SLOPE
FILTER
6D/4D
MIPI I3CSM
1
000
HPCF_XL[2:0]
1.
DS13773 - Rev 7
The cutoff value of the LPF1 output is ODR/2 when the accelerometer is in high-performance mode and
ODR up to 833 Hz. This value is equal to 780 Hz when the accelerometer is in low-power mode.
page 54/131
ASM330LHB
CTRL9_XL (18h)
9.20
CTRL9_XL (18h)
Control register 9 (R/W)
Table 62. CTRL9_XL register
DEN_X
DEN_Y
DEN_Z
DEN_XL_G
DEN_XL_EN
DEN_LH
I3C_
disable
0(1)
1. This bit must be set to 0 for the correct operation of the device.
Table 63. CTRL9_XL register description
DEN_X
DEN_Y
DEN_Z
DEN value stored in LSB of X-axis. Default value: 1
(0: DEN not stored in X-axis LSB; 1: DEN stored in X-axis LSB)
DEN value stored in LSB of Y-axis. Default value: 1
(0: DEN not stored in Y-axis LSB; 1: DEN stored in Y-axis LSB)
DEN value stored in LSB of Z-axis. Default value: 1
(0: DEN not stored in Z-axis LSB; 1: DEN stored in Z-axis LSB)
DEN stamping sensor selection. Default value: 0
DEN_XL_G
(0: DEN pin info stamped in the gyroscope axis selected by bits [7:5];
1: DEN pin info stamped in the accelerometer axis selected by bits [7:5])
DEN_XL_EN
DEN_LH
Extends DEN functionality to accelerometer sensor. Default value: 0
(0: disabled; 1: enabled)
DEN active level configuration. Default value: 0
(0: active low; 1: active high)
Disables MIPI I3CSM communication protocol(1)
I3C_disable
(0: SPI, I²C, MIPI I3CSM interfaces enabled (default);
1: MIPI I3CSM interface disabled)
1. It is recommended to set this bit to 1 during the initial device configuration phase, when the I3C interface is not used.
9.21
CTRL10_C (19h)
Control register 10 (R/W)
Table 64. CTRL10_C register
0(1)
0(1)
TIMESTAMP
_EN
0(1)
0(1)
0(1)
0(1)
0(1)
1. This bit must be set to 0 for the correct operation of the device.
Table 65. CTRL10_C register description
Enables timestamp counter. Default value: 0
TIMESTAMP_EN
(0: disabled; 1: enabled)
The counter is readable in TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and
TIMESTAMP3 (43h).
DS13773 - Rev 7
page 55/131
ASM330LHB
ALL_INT_SRC (1Ah)
9.22
ALL_INT_SRC (1Ah)
Source register for all interrupts (R)
Table 66. ALL_INT_SRC register
TIMESTAMP
_ENDCOUNT
SLEEP_
CHANGE_IA
0
D6D_IA
0
0
WU_IA
FF_IA
Table 67. ALL_INT_SRC register description
TIMESTAMP_ENDCOUNT Alerts timestamp overflow within 6.4 ms
SLEEP_CHANGE_IA
(0: change status not detected; 1: change status detected)
Interrupt active for change in position of portrait, landscape, face-up, face-down. Default value: 0
D6D_IA
(0: change in position not detected; 1: change in position detected)
Wake-up event status. Default value: 0
WU_IA
(0: event not detected, 1: event detected)
Free-fall event status. Default value: 0
FF_IA
9.23
Detects change event in activity/inactivity status. Default value: 0
(0: event not detected, 1: event detected)
WAKE_UP_SRC (1Bh)
Wake-up interrupt source register (R)
Table 68. WAKE_UP_SRC register
0
SLEEP_
CHANGE_IA
FF_IA
SLEEP_
STATE
WU_IA
X_WU
Y_WU
Z_WU
Table 69. WAKE_UP_SRC register description
SLEEP_CHANGE_IA
FF_IA
SLEEP_STATE
WU_IA
X_WU
Y_WU
Z_WU
DS13773 - Rev 7
Detects change event in activity/inactivity status. Default value: 0
(0: change status not detected; 1: change status detected)
Free-fall event detection status. Default: 0
(0: free-fall event not detected; 1: free-fall event detected)
Sleep event status. Default value: 0
(0: sleep event not detected; 1: sleep event detected)
Wake-up event detection status. Default value: 0
(0: wake-up event not detected; 1: wake-up event detected.)
Wake-up event detection status on X-axis. Default value: 0
(0: wake-up event on X-axis not detected; 1: wake-up event on X-axis detected)
Wake-up event detection status on Y-axis. Default value: 0
(0: wake-up event on Y-axis not detected; 1: wake-up event on Y-axis detected)
Wake-up event detection status on Z-axis. Default value: 0
(0: wake-up event on Z-axis not detected; 1: wake-up event on Z-axis detected)
page 56/131
ASM330LHB
DRD_SRC (1Dh)
9.24
DRD_SRC (1Dh)
Portrait, landscape, face-up and face-down source register (R)
Table 70. D6D_SRC register
DEN_DRDY
D6D_IA
ZH
ZL
YH
YL
XH
XL
Table 71. D6D_SRC register description
DEN_DRDY
D6D_IA
ZH
ZL
YH
YL
XH
XL
DEN data-ready signal. It is set high when data output is related to the data coming from a DEN active
condition. (1)
Interrupt active for change position portrait, landscape, face-up, face-down. Default value: 0
(0: change position not detected; 1: change position detected)
Z-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over threshold) detected)
Z-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
Y-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over threshold) detected)
Y-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
X-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over threshold) detected)
X-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
1. The DEN data-ready signal can be latched or pulsed depending on the value of the dataready_pulsed bit of the
COUNTER_BDR_REG1 (0Bh) register.
DS13773 - Rev 7
page 57/131
ASM330LHB
STATUS_REG (1Eh)
9.25
STATUS_REG (1Eh)
Status register (R)
Table 72. STATUS_REG register
0
0
0
0
BOOT_
CHECK_FAIL
TDA
GDA
XLDA
Table 73. STATUS_REG register description
BOOT_CHECK_FAIL
Embedded CRC check status after boot/reboot. Default value: 0
(0: boot check passed; 1: boot check failed)
Temperature new data available. Default: 0
TDA
(0: no set of data is available at temperature sensor output;
1: a new set of data is available at temperature sensor output)
Gyroscope new data available. Default value: 0
GDA
(0: no set of data available at gyroscope output;
1: a new set of data is available at gyroscope output)
Accelerometer new data available. Default value: 0
XLDA
(0: no set of data available at accelerometer output;
1: a new set of data is available at accelerometer output)
9.26
OUT_TEMP_L (20h), OUT_TEMP_H (21h)
Temperature data output register (R). L and H registers together express a 16-bit word in two’s complement.
Table 74. OUT_TEMP_L register
Temp7
Temp6
Temp5
Temp4
Temp3
Temp2
Temp1
Temp0
Temp10
Temp9
Temp8
Table 75. OUT_TEMP_H register
Temp15
Temp14
Temp13
Temp12
Temp11
Table 76. OUT_TEMP register description
Temp[15:0]
DS13773 - Rev 7
Temperature sensor output data
The value is expressed as two’s complement sign extended on the MSB.
page 58/131
ASM330LHB
OUTX_H_C (23h), OUTX_L_G (22h)
9.27
OUTX_H_C (23h), OUTX_L_G (22h)
Angular rate sensor pitch axis (X) angular rate output register (R). The value is expressed as a 16-bit word in
two’s complement.
Table 77. OUTX_H_G register
D15
D14
D13
D12
D11
D10
D9
D8
D2
D1
D0
Table 78. OUTX_L_G register
D7
D6
D5
D4
D3
Table 79. OUTX_H_G, OUTX_L_G register description
D[15:0]
9.28
Gyroscope pitch axis output expressed in two’s complement
OUTY_H_G (25h), OUTY_L_G (24h)
Angular rate sensor roll axis (Y) angular rate output register (R). The value is expressed as a 16-bit word in two’s
complement.
Table 80. OUTY_H_G register
D15
D14
D13
D12
D11
D10
D9
D8
D2
D1
D0
Table 81. OUTY_L_G register
D7
D6
D5
D4
D3
Table 82. OUTY_H_G, OUTY_L_G register description
D[15:0]
DS13773 - Rev 7
Gyroscope roll axis output expressed in two’s complement
page 59/131
ASM330LHB
OUTZ_H_G (27h), OUTZ_L_G (26h)
9.29
OUTZ_H_G (27h), OUTZ_L_G (26h)
Angular rate sensor pitch yaw (Z) angular rate output register (R). The value is expressed as a 16-bit word in
two’s complement.
Table 83. OUTZ_H_G register
D15
D14
D13
D12
D11
D10
D9
D8
D2
D1
D0
Table 84. OUTZ_L_G register
D7
D6
D5
D4
D3
Table 85. OUTZ_H_G, OUTZ_L_G register description
D[15:0]
9.30
Gyroscope yaw axis output expressed in two’s complement
OUTX_H_A (29h), OUTX_L_A (28h)
Linear acceleration sensor X-axis output register (R). The value is expressed as a 16-bit word in two’s
complement.
Table 86. OUTX_H_A register
D15
D14
D13
D12
D11
D10
D9
D8
D2
D1
D0
Table 87. OUTX_L_A register
D7
D6
D5
D4
D3
Table 88. OUTX_H_A, OUTX_L_A register description
D[15:0]
DS13773 - Rev 7
Accelerometer X-axis output expressed as two’s complement
page 60/131
ASM330LHB
OUTY_H_A (2Bh), OUTY_L_A (2Ah)
9.31
OUTY_H_A (2Bh), OUTY_L_A (2Ah)
Linear acceleration sensor Y-axis output register (R). The value is expressed as a 16-bit word in two’s
complement.
Table 89. OUTY_H_A register
D15
D14
D13
D12
D11
D10
D9
D8
D2
D1
D0
Table 90. OUTY_L_A register
D7
D6
D5
D4
D3
Table 91. OUTY_H_A, OUTY_L_A register description
D[15:0]
9.32
Accelerometer Y-axis output expressed as two’s complement
OUTZ_H_A (2Dh), OUTZ_L_A (2Ch)
Linear acceleration sensor Z-axis output register (R). The value is expressed as a 16-bit word in two’s
complement.
Table 92. OUTZ_H_A register
D15
D14
D13
D12
D11
D10
D9
D8
D2
D1
D0
Table 93. OUTZ_L_A register
D7
D6
D5
D4
D3
Table 94. OUTZ_H_A, OUTZ_L_A register description
D[15:0]
DS13773 - Rev 7
Accelerometer Z-axis output expressed as two’s complement
page 61/131
ASM330LHB
EMB_FUNC_STATUS_MAINPAGE (35h)
9.33
EMB_FUNC_STATUS_MAINPAGE (35h)
Embedded function status register (R)
Table 95. EMB_FUNC_STATUS_MAINPAGE register
IS_FSM_LC
0
0
0
0
0
0
0
IS_FSM2
IS_FSM1
Table 96. EMB_FUNC_STATUS_MAINPAGE register description
IS_FSM_LC
9.34
Interrupt status bit for FSM long counter timeout interrupt event.
(1: interrupt detected; 0: no interrupt)
FSM_STATUS_A_MAINPAGE (36h)
Finite state machine status register (R)
Table 97. FSM_STATUS_A_MAINPAGE register
IS_FSM8
IS_FSM7
IS_FSM6
IS_FSM5
IS_FSM4
IS_FSM3
Table 98. FSM_STATUS_A_MAINPAGE register description
DS13773 - Rev 7
IS_FSM8
Interrupt status bit for FSM8 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM7
Interrupt status bit for FSM7 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM6
Interrupt status bit for FSM6 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM5
Interrupt status bit for FSM5 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM4
Interrupt status bit for FSM4 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM3
Interrupt status bit for FSM3 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM2
Interrupt status bit for FSM2 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM1
Interrupt status bit for FSM1 interrupt event.
(1: interrupt detected; 0: no interrupt)
page 62/131
ASM330LHB
FSM_STATUS_B_MAINPAGE (37h)
9.35
FSM_STATUS_B_MAINPAGE (37h)
Finite state machine status register (R)
Table 99. FSM_STATUS_B_MAINPAGE register
IS_FSM16
IS_FSM15
IS_FSM14
IS_FSM13
IS_FSM12
IS_FSM11
IS_FSM10
IS_FSM9
Table 100. FSM_STATUS_B_MAINPAGE register description
9.36
IS_FSM16
Interrupt status bit for FSM16 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM15
Interrupt status bit for FSM15 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM14
Interrupt status bit for FSM14 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM13
Interrupt status bit for FSM13 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM12
Interrupt status bit for FSM12 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM11
Interrupt status bit for FSM11 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM10
Interrupt status bit for FSM10 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM9
Interrupt status bit for FSM9 interrupt event.
(1: interrupt detected; 0: no interrupt)
MLC_STATUS_MAINPAGE (38h)
Machine learning core status register (R)
Table 101. MLC_STATUS_MAINPAGE register
IS_MLC8
IS_MLC7
IS_MLC6
IS_MLC5
IS_MLC4
IS_MLC3
IS_MLC2
IS_MLC1
Table 102. MLC_STATUS_MAINPAGE register description
DS13773 - Rev 7
IS_MLC8
Interrupt status bit for MLC8 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC7
Interrupt status bit for MLC7 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC6
Interrupt status bit for MLC6 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC5
Interrupt status bit for MLC5 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC4
Interrupt status bit for MLC4 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC3
Interrupt status bit for MLC3 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC2
Interrupt status bit for MLC2 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_MLC1
Interrupt status bit for MLC1 interrupt event.
(1: interrupt detected; 0: no interrupt)
page 63/131
ASM330LHB
FIFO_STATUS1 (3Ah)
9.37
FIFO_STATUS1 (3Ah)
FIFO status register 1 (R)
Table 103. FIFO_STATUS1 register
DIFF_FIFO_7 DIFF_FIFO_6 DIFF_FIFO_5 DIFF_FIFO_4 DIFF_FIFO_3 DIFF_FIFO_2 DIFF_FIFO_1 DIFF_FIFO_0
Table 104. FIFO_STATUS1 register description
Number of unread sensor data (TAG + 6 bytes) stored in FIFO
DIFF_FIFO_[7:0]
9.38
In conjunction with DIFF_FIFO[9:8] in FIFO_STATUS2 (3Bh).
FIFO_STATUS2 (3Bh)
FIFO status register 2 (R)
Table 105. FIFO_STATUS2 register
FIFO_
WTM_IA
FIFO_
OVR_IA
FIFO_
FULL_IA
COUNTER_
BDR_IA
FIFO_OVR_
LATCHED
0
DIFF_FIFO_9 DIFF_FIFO_8
Table 106. FIFO_STATUS2 register description
FIFO watermark status. Default value: 0
FIFO_WTM_IA
(0: FIFO filling is lower than WTM;
1: FIFO filling is equal to or greater than WTM)
Watermark is set through bits WTM[8:0] in FIFO_CTRL2 (08h) and FIFO_CTRL1 (07h).
FIFO_OVR_IA
FIFO_FULL_IA
COUNTER_BDR_IA
FIFO overrun status. Default value: 0
(0: FIFO is not completely filled; 1: FIFO is completely filled)
Smart FIFO full status. Default value: 0
(0: FIFO is not full; 1: FIFO will be full at the next ODR)
Counter BDR reaches the CNT_BDR_TH_[10:0] threshold set in COUNTER_BDR_REG1 (0Bh) and
COUNTER_BDR_REG2 (0Ch). Default value: 0
This bit is reset when these registers are read.
FIFO_OVR_LATCHED
DIFF_FIFO_[9:8]
DS13773 - Rev 7
Latched FIFO overrun status. Default value: 0
This bit is reset when this register is read.
Number of unread sensor data (TAG + 6 bytes) stored in FIFO. Default value: 00
In conjunction with DIFF_FIFO[7:0] in FIFO_STATUS1 (3Ah)
page 64/131
ASM330LHB
TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h)
9.39
TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3
(43h)
Timestamp first data output register (R). The value is expressed as a 32-bit word and the bit resolution is 25 µs.
Table 107. TIMESTAMP3 register
D31
D30
D29
D28
D27
D26
D25
D24
D18
D17
D16
D10
D9
D8
D2
D1
D0
Table 108. TIMESTAMP2 register
D23
D22
D21
D20
D19
Table 109. TIMESTAMP1 register
D15
D14
D13
D12
D11
Table 110. TIMESTAMP0 register
D7
D[31:0]
D6
D5
D4
D3
Timestamp output registers: 1LSB = 25 µs
The formula below can be used to calculate a better estimation of the actual timestamp resolution:
TS_Res = 1 / (40000 + (0.0015 * INTERNAL_FREQ_FINE * 40000))
where INTERNAL_FREQ_FINE is the content of INTERNAL_FREQ_FINE (63h).
DS13773 - Rev 7
page 65/131
ASM330LHB
INT_CFG0 (56h)
9.40
INT_CFG0 (56h)
Activity/inactivity functions, configuration of filtering, and interrupt latch mode configuration (R/W)
Table 111. INT_CFG0 register
0(1)
INT_CLR_
ON_READ
SLEEP_
STATUS_ON
_INT
SLOPE_
FDS
0(1)
0(1)
0(1)
LIR
1. This bit must be set to 0 for the correct operation of the device.
Table 112. INT_CFG0 register description
This bit allows immediately clearing the latched interrupts of an event detection upon the read of
the corresponding status register. It must be set to 1 together with LIR. Default value: 0
INT_CLR_ON_READ
(0: latched interrupt signal cleared at the end of the ODR period;
1: latched interrupt signal immediately cleared)
Activity/inactivity interrupt mode configuration.
SLEEP_STATUS_ON_INT
If INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits are enabled, drives the sleep status or
sleep change on INT pins. Default value: 0
(0: sleep change notification on INT pins; 1: sleep status reported on INT pins)
HPF or SLOPE filter selection on wake-up and activity/inactivity functions. Default value: 0
SLOPE_FDS
(0: SLOPE filter applied; 1: HPF applied)
Latched interrupt. Default value: 0
LIR
9.41
(0: interrupt request not latched; 1: interrupt request latched)
INT_CFG1 (58h)
Enable interrupt function register (R/W)
Table 113. INT_CFG1 register
INTERRUPTS_
ENABLE
INACT_EN1
INACT_EN0
0(1)
0(1)
0(1)
0(1)
0(1)
1. This bit must be set to 0 for the correct operation of the device.
Table 114. INT_CFG1 register description
INTERRUPTS_ENABLE
Enables hardcoded functions
Enables activity/inactivity (sleep) function. Default value: 00
(00: stationary/motion-only interrupts generated, accelerometer and gyroscope do not change;
INACT_EN[1:0]
01: sets accelerometer ODR to 12.5 Hz (low-power mode), gyroscope does not change;
10: sets accelerometer ODR to 12.5 Hz (low-power mode), gyroscope to sleep mode;
11: sets accelerometer ODR to 12.5 Hz (low-power mode), gyroscope to power-down mode)
DS13773 - Rev 7
page 66/131
ASM330LHB
THS_6D (59h)
9.42
THS_6D (59h)
Portrait/landscape position register (R/W)
Table 115. THS_6D register
D4D_EN
SIXD_THS1
SIXD_THS0
0(1)
0(1)
0(1)
0(1)
0(1)
1. This bit must be set to 0 for the correct operation of the device.
Table 116. THS_6D register description
Enables detection of 4D orientation. Z-axis position detection is disabled. Default value: 0
D4D_EN
(0: disabled; 1: enabled)
Threshold for 4D/6D function
(00: 80 degrees (default);
SIXD_THS[1:0]
01: 70 degrees;
10: 60 degrees;
11: 50 degrees)
9.43
WAKE_UP_THS (5Bh)
Wake-up configuration register (R/W)
Table 117. WAKE_UP_THS register
0(1)
USR_OFF_
ON_WU
WK_THS5
WK_THS4
WK_THS3
WK_THS2
WK_THS1
WK_THS0
1. This bit must be set to 0 for the correct operation of the device.
Table 118. WAKE_UP_THS register description
DS13773 - Rev 7
USR_OFF_ON_WU
Sends the low-pass filtered data with user offset correction (instead of high-pass filtered data) to the
wake-up and the activity/inactivity functions. Default value: 0
WK_THS[5:0]
Threshold for wake-up: 1 LSB weight depends on WAKE_THS_W in WAKE_UP_DUR (5Ch). Default
value: 000000
page 67/131
ASM330LHB
WAKE_UP_DUR (5Ch)
9.44
WAKE_UP_DUR (5Ch)
Free-fall, wake-up and sleep mode functions duration setting register (R/W)
Table 119. WAKE_UP_DUR register
FF_DUR5
WAKE_DUR1 WAKE_DUR0
WAKE_
THS_W
SLEEP_
DUR3
SLEEP_
DUR2
SLEEP_
DUR1
SLEEP_
DUR0
Table 120. WAKE_UP_DUR register description
Free-fall duration event. Default: 0
For the complete configuration of the free-fall duration, refer to FF_DUR[4:0] in FREE_FALL (5Dh)
configuration.
FF_DUR5
1 LSB = 1 ODR_time
WAKE_DUR[1:0]
Wake-up duration event. Default: 00
1LSB = 1 ODR_time
Weight of 1 LSB of wake-up threshold. Default: 0
WAKE_THS_W
(0: 1 LSB =FS_XL / (26);
1: 1 LSB = FS_XL / (28))
SLEEP_DUR[3:0]
9.45
Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR)
1 LSB = 512 ODR
FREE_FALL (5Dh)
Free-fall function duration setting register (R/W)
Table 121. FREE_FALL register
FF_DUR4
FF_DUR3
FF_DUR2
FF_DUR1
FF_DUR0
FF_THS2
FF_THS1
FF_THS0
Table 122. FREE_FALL register description
Free-fall duration event. Default: 0
FF_DUR[4:0] For the complete configuration of the free fall duration, refer to FF_DUR5 in WAKE_UP_DUR (5Ch)
configuration
Free-fall threshold setting
(000: 156 mg (default);
001: 219 mg;
010: 250 mg;
FF_THS[2:0] 011: 312 mg;
100: 344 mg;
101: 406 mg;
110: 469 mg;
111: 500 mg)
DS13773 - Rev 7
page 68/131
ASM330LHB
MD1_CFG (5Eh)
9.46
MD1_CFG (5Eh)
Functions routing to INT1 pin register (R/W)
Table 123. MD1_CFG register
INT1_SLEEP
_CHANGE
0(1)
INT1_WU
INT1_FF
0(1)
INT1_6D
INT1_
EMB_FUNC
0(1)
1. This bit must be set to 0 for the correct operation of the device.
Table 124. MD1_CFG register description
Routing activity/inactivity recognition event to INT1. Default: 0
INT1_SLEEP_CHANGE(1)
(0: routing activity/inactivity event to INT1 disabled;
1: routing activity/inactivity event to INT1 enabled)
Routing wake-up event to INT1. Default value: 0
INT1_WU
(0: routing wake-up event to INT1 disabled;
1: routing wake-up event to INT1 enabled)
Routing free-fall event to INT1. Default value: 0
INT1_FF
(0: routing free-fall event to INT1 disabled;
1: routing free-fall event to INT1 enabled)
Routing 6D event to INT1. Default value: 0
INT1_6D
(0: routing 6D event to INT1 disabled;
1: routing 6D event to INT1 enabled)
Routing embedded functions event to INT1. Default value: 0
INT1_EMB_FUNC
(0: routing embedded functions event to INT1 disabled;
1: routing embedded functions event to INT1 enabled)
1. Activity/inactivity interrupt mode (sleep change or sleep status) depends on the SLEEP_STATUS_ON_INT bit in the
INT_CFG0 (56h) register.
DS13773 - Rev 7
page 69/131
ASM330LHB
MD2_CFG (5Fh)
9.47
MD2_CFG (5Fh)
Functions routing to INT2 pin register (R/W)
Table 125. MD2_CFG register
INT2_SLEEP
_CHANGE
0(1)
INT2_WU
INT2_FF
0(1)
INT2_6D
INT2_
EMB_FUNC
INT2_
TIMESTAMP
1. This bit must be set to 0 for the correct operation of the device.
Table 126. MD2_CFG register description
Routing activity/inactivity recognition event to INT2. Default: 0
INT2_SLEEP_CHANGE(1)
(0: routing activity/inactivity event to INT2 disabled;
1: routing activity/inactivity event to INT2 enabled)
Routing wake-up event to INT2. Default value: 0
INT2_WU
(0: routing wake-up event to INT2 disabled;
1: routing wake-up event to INT2 enabled)
Routing free-fall event to INT2. Default value: 0
INT2_FF
(0: routing free-fall event to INT2 disabled;
1: routing free-fall event to INT2 enabled)
Routing 6D event to INT2. Default value: 0
INT2_6D
(0: routing 6D event to INT2 disabled;
1: routing 6D event to INT2 enabled)
Routing embedded functions event to INT2. Default value: 0
INT2_EMB_FUNC
(0: routing embedded functions event to INT2 disabled;
1: routing embedded functions event to INT2 enabled)
INT2_TIMESTAMP
Enables routing to INT2 pin of the alert for timestamp overflow within 6.4 ms.
1. Activity/inactivity interrupt mode (sleep change or sleep status) depends on the SLEEP_STATUS_ON_INT bit in the
INT_CFG0 (56h) register.
DS13773 - Rev 7
page 70/131
ASM330LHB
I3C_BUS_AVB (62h)
9.48
I3C_BUS_AVB (62h)
I3C_BUS_AVB register (R/W)
Table 127. I3C_BUS_AVB register
0(1)
0(1)
0(1)
I3C_Bus_
Avb_Sel1
I3C_Bus_
Avb_Sel0
0(1)
0(1)
PD_DIS_
INT1
1. This bit must be set to 0 for the correct operation of the device.
Table 128. I3C_BUS_AVB register description
These bits are used to select the bus available time when I3C IBI is used.
Default value: 00
I3C_Bus_Avb_Sel[1:0]
(00: bus available time equal to 50 µs (default);
01: bus available time equal to 2 µs;
10: bus available time equal to 1 ms;
11: bus available time equal to 25 ms)
This bit allows disabling the INT1 pull-down.
PD_DIS_INT1
(0: Pull-down on INT1 enabled (pull-down is effectively connected only when no interrupts are routed
to the INT1 pin or when the I3C dynamic address is assigned);
1: Pull-down on INT1 disabled (pull-down not connected))
Note:
DS13773 - Rev 7
The IBI (in-band interrupt) is continuously generated (each time a bus available condition is satisfied) until an
interrupt is served. The master should execute the interrupt service routine (ISR) at a time lower than the
configured bus available time, otherwise the master should disable the interrupt (I3C DISEC in order to disable
the interrupt request) at a time lower than the bus available time.
If the master needs more time to analyze and start the correct ISR, then the master can change the bus
available time from 50 µs (default) to a higher time.
page 71/131
ASM330LHB
INTERNAL_FREQ_FINE (63h)
9.49
INTERNAL_FREQ_FINE (63h)
Internal frequency register (R)
Table 129. INTERNAL_FREQ_FINE register
FREQ_FINE7 FREQ_FINE6 FREQ_FINE5 FREQ_FINE4 FREQ_FINE3 FREQ_FINE2 FREQ_FINE1 FREQ_FINE0
Table 130. INTERNAL_FREQ_FINE register description
FREQ_FINE[7:0]
Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.15%.
8-bit format, two's complement.
The formula below can be used to calculate a better estimation of the actual ODR:
ODR_Actual = (6667 + ((0.0015 * INTERNAL_FREQ_FINE) * 6667)) / ODR_Coeff
Selected_ODR
ODR_Coeff
12.5
512
26
256
52
128
104
64
208
32
416
16
833
8
1667
4
The Selected_ODR parameter has to be derived from the ODR_XL selection (Table 42. CTRL1_XL register
description) in order to estimate the accelerometer ODR and from the ODR_G selection (Table 45. CTRL2_G
register description) in order to estimate the gyroscope ODR.
DS13773 - Rev 7
page 72/131
ASM330LHB
X_OFS_USR (73h)
9.50
X_OFS_USR (73h)
Accelerometer X-axis user offset correction (R/W). The offset value set in the X_OFS_USR offset register is
internally subtracted from the acceleration value measured on the X-axis.
Table 131. X_OFS_USR register
X_OFS_
USR_7
X_OFS_
USR_6
X_OFS_
USR_5
X_OFS_
USR_4
X_OFS_
USR_3
X_OFS_
USR_2
X_OFS_
USR_1
X_OFS_
USR_0
Table 132. X_OFS_USR register description
X_OFS_USR_[7:0]
9.51
Accelerometer X-axis user offset correction expressed in two’s complement, weight depends on
USR_OFF_W in CTRL6_C (15h). The value must be in the range [-127 127].
Y_OFS_USR (74h)
Accelerometer Y-axis user offset correction (R/W). The offset value set in the Y_OFS_USR offset register is
internally subtracted from the acceleration value measured on the Y-axis.
Table 133. Y_OFS_USR register
Y_OFS_
USR_7
Y_OFS_
USR_6
Y_OFS_USR_[7:0]
9.52
Y_OFS_
USR_5
Y_OFS_
USR_4
Y_OFS_
USR_3
Y_OFS_
USR_2
Y_OFS_
USR_1
Y_OFS_
USR_0
Accelerometer Y-axis user offset calibration expressed in two’s complement, weight depends on
USR_OFF_W in CTRL6_C (15h). The value must be in the range [-127, +127].
Z_OFS_USR (75h)
Accelerometer Z-axis user offset correction (R/W). The offset value set in the Z_OFS_USR offset register is
internally subtracted from the acceleration value measured on the Z-axis.
Table 134. Z_OFS_USR register
Z_OFS_
USR_7
Z_OFS_
USR_6
Z_OFS_
USR_5
Z_OFS_
USR_4
Z_OFS_
USR_3
Z_OFS_
USR_2
Z_OFS_
USR_1
Z_OFS_
USR_0
Table 135. Z_OFS_USR register description
Z_OFS_USR_[7:0]
DS13773 - Rev 7
Accelerometer Z-axis user offset calibration expressed in two’s complement, weight depends on
USR_OFF_W in CTRL6_C (15h). The value must be in the range [-127, +127].
page 73/131
ASM330LHB
FIFO_DATA_OUT_TAG (78h)
9.53
FIFO_DATA_OUT_TAG (78h)
FIFO tag register (R)
Table 136. FIFO_DATA_OUT_TAG register
TAG_
SENSOR_4
TAG_
SENSOR_3
TAG_
SENSOR_2
TAG_
SENSOR_1
TAG_
SENSOR_0
TAG_CNT_1
TAG_CNT_0
TAG_
PARITY
Table 137. FIFO_DATA_OUT_TAG register description
Identifies the sensor in:
TAG_SENSOR_[4:0] FIFO_DATA_OUT_X_H (7Ah) and FIFO_DATA_OUT_X_L (79h), FIFO_DATA_OUT_Y_H (7Ch) and
FIFO_DATA_OUT_Y_L (7Bh), and FIFO_DATA_OUT_Z_H (7Eh) and FIFO_DATA_OUT_Z_L (7Dh)
TAG_CNT_[1:0]
2-bit counter which identifies sensor time slot
TAG_PARITY
Parity check of TAG content
Table 138. FIFO tag
DS13773 - Rev 7
TAG_SENSOR_[4:0]
Sensor name
0x01
Gyroscope
0x02
Accelerometer
0x03
Temperature
0x04
Timestamp
0x05
CFG_Change
page 74/131
ASM330LHB
FIFO_DATA_OUT_X_H (7Ah) and FIFO_DATA_OUT_X_L (79h)
9.54
FIFO_DATA_OUT_X_H (7Ah) and FIFO_DATA_OUT_X_L (79h)
FIFO data output X (R)
Table 139. FIFO_DATA_OUT_X_H register
D15
D14
D13
D12
D11
D10
D9
D8
D1
D0
Table 140. FIFO_DATA_OUT_X_L register
D7
D6
D5
D4
D3
D2
Table 141. FIFO_DATA_OUT_X_H, FIFO_DATA_OUT_X_L register description
D[15:0]
9.55
FIFO X-axis output
FIFO_DATA_OUT_Y_H (7Ch) and FIFO_DATA_OUT_Y_L (7Bh)
FIFO data output Y (R)
Table 142. FIFO_DATA_OUT_Y_H register
D15
D14
D13
D12
D11
D10
D9
D8
D1
D0
Table 143. FIFO_DATA_OUT_Y_L register
D7
D6
D5
D4
D3
D2
Table 144. FIFO_DATA_OUT_Y_H, FIFO_DATA_OUT_Y_L register description
D[15:0]
9.56
FIFO Y-axis output
FIFO_DATA_OUT_Z_H (7Eh) and FIFO_DATA_OUT_Z_L (7Dh)
FIFO data output Z (R)
Table 145. FIFO_DATA_OUT_Z_H register
D15
D14
D13
D12
D11
D10
D9
D8
D1
D0
Table 146. FIFO_DATA_OUT_Z_L register
D7
D6
D5
D4
D3
D2
Table 147. FIFO_DATA_OUT_Z_H, FIFO_DATA_OUT_Z_L register description
D[15:0]
DS13773 - Rev 7
FIFO Z-axis output
page 75/131
ASM330LHB
Embedded functions register mapping
10
Embedded functions register mapping
The table given below provides a list of the registers for the embedded functions available in the device and
the corresponding addresses. Embedded functions registers are accessible when FUNC_CFG_EN is set to 1 in
FUNC_CFG_ACCESS (01h).
Table 148. Register address map - embedded functions
Name
Type
PAGE_SEL
RESERVED
Register address
Default
Hex
Binary
R/W
02
00000010
-
03-04
EMB_FUNC_EN_B
R/W
05
00000101
00000000
PAGE_ADDRESS
R/W
08
00001000
00000000
PAGE_VALUE
R/W
09
00001001
00000000
EMB_FUNC_INT1
R/W
0A
00001010
00000000
FSM_INT1_A
R/W
0B
00001011
00000000
FSM_INT1_B
R/W
0C
00001100
00000000
MLC_INT1
R/W
0D
00001101
00000000
EMB_FUNC_INT2
R/W
0E
00001110
00000000
FSM_INT2_A
R
0F
00001111
01101011
FSM_INT2_B
R/W
10
00010000
00000000
MLC_INT2
R/W
11
00010001
00000000
EMB_FUNC_STATUS
R
12
00010010
output
FSM_STATUS_A
R
13
00010011
output
FSM_STATUS_B
R
14
00010100
output
MLC_STATUS
R
15
00010101
output
PAGE_RW
R/W
17
00010111
00000000
RESERVED
-
18-45
FSM_ENABLE_A
R/W
46
01000110
00000000
FSM_ENABLE_B
R/W
47
01000111
00000000
FSM_LONG_COUNTER_L
R/W
48
01001000
00000000
FSM_LONG_COUNTER_H
R/W
49
01001001
00000000
FSM_LONG_COUNTER_CLEAR
R/W
4A
01001010
00000000
FSM_OUTS1
R
4C
01001100
output
FSM_OUTS2
R
4D
01001101
output
FSM_OUTS3
R
4E
01001110
output
FSM_OUTS4
R
4F
01001111
output
FSM_OUTS5
R
50
01010000
output
FSM_OUTS6
R
51
01010001
output
FSM_OUTS7
R
52
01010010
output
FSM_OUTS8
R
53
01010011
output
FSM_OUTS9
R
54
01010100
output
FSM_OUTS10
R
55
01010101
output
DS13773 - Rev 7
Comment
00000001
Reserved
Reserved
page 76/131
ASM330LHB
Embedded functions register mapping
Name
Type
Register address
Hex
Binary
Default
FSM_OUTS11
R
56
01010110
output
FSM_OUTS12
R
57
01010111
output
FSM_OUTS13
R
58
01011000
output
FSM_OUTS14
R
59
01011001
output
FSM_OUTS15
R
5A
01011010
output
FSM_OUTS16
R
5B
01011011
output
RESERVED
-
5C-5E
EMB_FUNC_ODR_CFG_B
R/W
5F
01011111
01001011
EMB_FUNC_ODR_CFG_C
R/W
60
01100000
00010101
-
61-66
R/W
67
01100111
00000000
MLC0_SRC
R
70
01110000
output
MLC1_SRC
R
71
01110001
output
MLC2_SRC
R
72
01110010
output
MLC3_SRC
R
73
01110011
output
MLC4_SRC
R
74
01110100
output
MLC5_SRC
R
75
01110101
output
MLC6_SRC
R
76
01110110
output
MLC7_SRC
R
77
01110111
output
RESERVED
EMB_FUNC_INIT_B
Comment
Reserved
Reserved
Reserved registers must not be changed. Writing to those registers may cause permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration
values. Their content is automatically restored when the device is powered up.
DS13773 - Rev 7
page 77/131
ASM330LHB
Embedded functions register description
11
Embedded functions register description
11.1
PAGE_SEL (02h)
Enable advanced features dedicated page (R/W)
Table 149. PAGE_SEL register
PAGE_SEL3
PAGE_SEL2
PAGE_SEL1
PAGE_SEL0
0(1)
0(1)
EMB_FUNC
_CLK_DIS
1(2)
1. This bit must be set to 0 for the correct operation of the device.
2. This bit must be set to 1 for the correct operation of the device.
Table 150. PAGE_SEL register description
PAGE_SEL[3:0]
Selects the advanced features dedicated page. Default value: 0000
EMB_FUNC_CLK_DIS
11.2
Disables the embedded functions clock. Default value: 0
(0: clock enabled; 1: clock disabled)
EMB_FUNC_EN_B (05h)
Enable embedded functions register (R/W)
Table 151. EMB_FUNC_EN_B register
0(1)
0(1)
0(1)
MLC_EN
0(1)
0(1)
0(1)
FSM_EN
PAGE_
ADDR1
PAGE_
ADDR0
1. This bit must be set to 0 for the correct operation of the device.
Table 152. EMB_FUNC_EN_B register description
Enables machine learning core feature. Default value: 0
MLC_EN
(0: machine learning core feature disabled;
1: machine learning core feature enabled)
FSM_EN
11.3
Enables finite state machine (FSM) feature. Default value: 0
(0: FSM feature disabled; 1: FSM feature enabled)
PAGE_ADDRESS (08h)
Page address register (R/W)
Table 153. PAGE_ADDRESS register
PAGE_
ADDR7
PAGE_
ADDR6
PAGE_
ADDR5
PAGE_
ADDR4
PAGE_
ADDR3
PAGE_
ADDR2
Table 154. PAGE_ADDRESS register description
After setting the bit PAGE_WRITE / PAGE_READ in register PAGE_RW (17h), this register is used to set
PAGE_ADDR[7:0] the address of the register to be written/read in the advanced features page selected through the bits
PAGE_SEL[3:0] in register PAGE_SEL (02h).
DS13773 - Rev 7
page 78/131
ASM330LHB
PAGE_VALUE (09h)
11.4
PAGE_VALUE (09h)
Page value register (R/W)
Table 155. PAGE_VALUE register
PAGE_
VALUE7
PAGE_
VALUE6
PAGE_
VALUE5
PAGE_
VALUE4
PAGE_
VALUE3
PAGE_
VALUE2
PAGE_
VALUE1
PAGE_
VALUE0
Table 156. PAGE_VALUE register description
These bits are used to write (if the bit PAGE_WRITE = 1 in register PAGE_RW (17h)) or read (if the bit
PAGE_VALUE[7:0] PAGE_READ = 1 in register PAGE_RW (17h)) the data at the address PAGE_ADDR[7:0] of the selected
advanced features page.
11.5
EMB_FUNC_INT1 (0Ah)
INT1 pin control register (R/W)
Each bit in this register enables a signal to be carried over INT1. The pin's output supplies the OR combination of
the selected signals.
Table 157. EMB_FUNC_INT1 register
INT1_
FSM_LC
0(1)
0(1)
0(1)
0(1)
0(1)
0(1)
0(1)
1. This bit must be set to 0 for the correct operation of the device.
Table 158. EMB_FUNC_INT1 register description
INT1_FSM_LC(1)
Routing FSM long counter timeout interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
1. This bit is activated if the INT1_EMB_FUNC bit of MD1_CFG (5Eh) is set to 1.
DS13773 - Rev 7
page 79/131
ASM330LHB
FSM_INT1_A (0Bh)
11.6
FSM_INT1_A (0Bh)
INT1 pin control register (R/W)
Each bit in this register enables a signal to be carried over INT1. The pin's output supplies the OR combination of
the selected signals.
Table 159. FSM_INT1_A register
INT1_FSM8
INT1_FSM7
INT1_FSM6
INT1_FSM5
INT1_FSM4
INT1_FSM3
INT1_FSM2
INT1_FSM1
Table 160. FSM_INT1_A register description
INT1_FSM8(1)
INT1_FSM7(1)
INT1_FSM6(1)
INT1_FSM5(1)
INT1_FSM4(1)
INT1_FSM3(1)
INT1_FSM2(1)
INT1_FSM1(1)
Routing FSM8 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing FSM7 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing FSM6 interrupt event INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing FSM5 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing FSM4 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing FSM3 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing FSM2 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing FSM1 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
1. This bit is activated if the INT1_EMB_FUNC bit of MD1_CFG (5Eh) is set to 1.
DS13773 - Rev 7
page 80/131
ASM330LHB
FSM_INT1_B (0Ch)
11.7
FSM_INT1_B (0Ch)
INT1 pin control register (R/W)
Each bit in this register enables a signal to be carried over INT1. The pin's output supplies the OR combination of
the selected signals.
Table 161. FSM_INT1_B register
INT1_FSM16
INT1_FSM15
INT1_FSM14
INT1_FSM13
INT1_FSM12
INT1_FSM11
INT1_FSM10
INT1_FSM9
Table 162. FSM_INT1_B register description
INT1_FSM16(1)
INT1_FSM15(1)
INT1_FSM14(1)
INT1_FSM13(1)
INT1_FSM12(1)
INT1_FSM11(1)
INT1_FSM10(1)
INT1_FSM9(1)
Routing FSM16 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing FSM15 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing FSM14 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing FSM13 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing FSM12 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing FSM11 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing FSM10 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing FSM9 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
1. This bit is activated if the INT1_EMB_FUNC bit of MD1_CFG (5Eh) is set to 1.
DS13773 - Rev 7
page 81/131
ASM330LHB
MLC_INT1 (0Dh)
11.8
MLC_INT1 (0Dh)
INT1 pin control register (R/W)
Each bit in this register enables a signal to be carried over INT1. The pin's output supplies the OR combination of
the selected signals.
Table 163. MLC_INT1 register
INT1_MLC8
INT1_MLC7
INT1_MLC6
INT1_MLC5
INT1_MLC4
INT1_MLC3
INT1_MLC2
INT1_MLC1
Table 164. MLC_INT1 register description
INT1_MLC8
INT1_MLC7
INT1_MLC6
INT1_MLC5
INT1_MLC4
INT1_MLC3
INT1_MLC2
INT1_MLC1
DS13773 - Rev 7
Routing MLC8 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing MLC7 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing MLC6 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing MLC5 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing MLC4 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing MLC3 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing MLC2 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
Routing MLC1 interrupt event to INT1. Default value: 0
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
page 82/131
ASM330LHB
EMB_FUNC_INT2 (0Eh)
11.9
EMB_FUNC_INT2 (0Eh)
INT2 pin control register (R/W)
Each bit in this register enables a signal to be carried over INT2. The pin's output supplies the OR combination of
the selected signals.
Table 165. EMB_FUNC_INT2 register
INT2_
FSM_LC
0(1)
0(1)
0(1)
0(1)
0(1)
0(1)
0(1)
1. This bit must be set to 0 for the correct operation of the device.
Table 166. EMB_FUNC_INT2 register description
INT2_FSM_LC(1)
Routing FSM long counter timeout interrupt event to INT2. Default value: 0
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
1. This bit is activated if the INT2_EMB_FUNC bit of MD2_CFG (5Fh) is set to 1.
11.10
FSM_INT2_A (0Fh)
INT2 pin control register (R/W)
Each bit in this register enables a signal to be carried over INT2. The pin's output supplies the OR combination of
the selected signals.
Table 167. FSM_INT2_A register
INT2_FSM8
INT2_FSM7
INT2_FSM6
INT2_FSM5
INT2_FSM4
INT2_FSM3
INT2_FSM2
INT2_FSM1
Table 168. FSM_INT2_A register description
INT2_FSM8(1)
INT2_FSM7(1)
INT2_FSM6(1)
INT2_FSM5(1)
INT2_FSM4(1)
Routing FSM8 interrupt event to INT2. Default value: 0
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing FSM7 interrupt event to INT2. Default value: 0
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing FSM6 interrupt event to INT2. Default value: 0
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing FSM5 interrupt event to INT2. Default value: 0
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing FSM4 interrupt event to INT2. Default value: 0
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing FSM3 interrupt event to INT2. Default value: 0
INT2_FSM3(1)
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
(0: routing to INT1 disabled; 1: routing to INT1 enabled)
INT2_FSM2(1)
INT2_FSM1(1)
Routing FSM2 interrupt event to INT2. Default value: 0
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing FSM1 interrupt event to INT2. Default value: 0
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
1. This bit is activated if the INT2_EMB_FUNC bit of MD2_CFG (5Fh) is set to 1.
DS13773 - Rev 7
page 83/131
ASM330LHB
FSM_INT2_B (10h)
11.11
FSM_INT2_B (10h)
INT2 pin control register (R/W)
Each bit in this register enables a signal to be carried over INT2. The pin's output supplies the OR combination of
the selected signals.
Table 169. FSM_INT2_B register
INT2_FSM16
INT2_FSM15
INT2_FSM14
INT2_FSM13
INT2_FSM12
INT2_FSM11
INT2_FSM10
INT2_FSM9
Table 170. FSM_INT2_B register description
INT2_FSM16(1)
INT2_FSM15(1)
INT2_FSM14(1)
INT2_FSM13(1)
INT2_FSM12(1)
INT2_FSM11(1)
INT2_FSM10(1)
INT2_FSM9(1)
Routing FSM16 interrupt event to INT2. Default value: 0
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing FSM15 interrupt event to INT2. Default value: 0
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing FSM14 interrupt event to INT2. Default value: 0
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing FSM13 interrupt event to INT2. Default value: 0
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing FSM12 interrupt event to INT2. Default value: 0
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing FSM11 interrupt event to INT2. Default value: 0
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing FSM10 interrupt event to INT2. Default value: 0
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing FSM9 interrupt event to INT2. Default value: 0
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
1. This bit is activated if the INT2_EMB_FUNC bit of MD2_CFG (5Fh) is set to 1.
DS13773 - Rev 7
page 84/131
ASM330LHB
MLC_INT2 (11h)
11.12
MLC_INT2 (11h)
INT2 pin control register (R/W)
Each bit in this register enables a signal to be carried over INT2. The pin's output supplies the OR combination of
the selected signals.
Table 171. MLC_INT2 register
INT2_MLC8
INT2_MLC7
INT2_MLC6
INT2_MLC5
INT2_MLC4
INT2_MLC3
INT2_MLC2
INT2_MLC1
0
0
Table 172. MLC_INT2 register description
Routing MLC8 interrupt event to INT2. Default value: 0
INT2_MLC8
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing MLC7 interrupt event to INT2. Default value: 0
INT2_MLC7
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing MLC6 interrupt event to INT2. Default value: 0
INT2_MLC6
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing MLC5 interrupt event to INT2. Default value: 0
INT2_MLC5
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing MLC4 interrupt event to INT2. Default value: 0
INT2_MLC4
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing MLC3 interrupt event to INT2. Default value: 0
INT2_MLC3
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing MLC2 interrupt event to INT2. Default value: 0
INT2_MLC2
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
Routing MLC1 interrupt event to INT2. Default value: 0
INT2_MLC1
11.13
(0: routing to INT2 disabled; 1: routing to INT2 enabled)
EMB_FUNC_STATUS (12h)
Embedded function status register (R)
Table 173. EMB_FUNC_STATUS register
IS_FSM_LC
0
0
0
0
0
Table 174. EMB_FUNC_STATUS register description
IS_FSM_LC
DS13773 - Rev 7
Interrupt status bit for FSM long counter timeout interrupt event.
(1: interrupt detected; 0: no interrupt)
page 85/131
ASM330LHB
FSM_STATUS_A (13h)
11.14
FSM_STATUS_A (13h)
Finite state machine status register (R)
Table 175. FSM_STATUS_A register
IS_FSM8
IS_FSM7
IS_FSM6
IS_FSM5
IS_FSM4
IS_FSM3
IS_FSM2
IS_FSM1
Table 176. FSM_STATUS_A register description
IS_FSM8
IS_FSM7
IS_FSM6
IS_FSM5
IS_FSM4
IS_FSM3
IS_FSM2
IS_FSM1
DS13773 - Rev 7
Interrupt status bit for FSM8 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM7 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM6 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM5 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM4 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM3 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM2 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM1 interrupt event.
(1: interrupt detected; 0: no interrupt)
page 86/131
ASM330LHB
FSM_STATUS_B (14h)
11.15
FSM_STATUS_B (14h)
Finite state machine status register (R)
Table 177. FSM_STATUS_B register
IS_FSM16
IS_FSM15
IS_FSM14
IS_FSM13
IS_FSM12
IS_FSM11
IS_FSM10
IS_FSM9
Table 178. FSM_STATUS_B register description
IS_FSM16
IS_FSM15
IS_FSM14
IS_FSM13
IS_FSM12
IS_FSM11
IS_FSM10
IS_FSM9
DS13773 - Rev 7
Interrupt status bit for FSM16 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM15 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM14 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM13 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM12 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM11 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM10 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM9 interrupt event.
(1: interrupt detected; 0: no interrupt)
page 87/131
ASM330LHB
MLC_STATUS (15h)
11.16
MLC_STATUS (15h)
Machine learning core status register (R)
Table 179. MLC_STATUS register
IS_MLC8
IS_MLC7
IS_MLC6
IS_MLC5
IS_MLC4
IS_MLC3
IS_MLC2
IS_MLC1
Table 180. MLC_STATUS register description
IS_MLC8
IS_MLC7
IS_MLC6
IS_MLC5
IS_MLC4
IS_MLC3
IS_MLC2
IS_MLC1
DS13773 - Rev 7
Interrupt status bit for MLC8 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC7 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC6 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC5 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC4 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC3 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC2 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for MLC1 interrupt event.
(1: interrupt detected; 0: no interrupt)
page 88/131
ASM330LHB
PAGE_RW (17h)
11.17
PAGE_RW (17h)
Enable read and write mode of advanced features dedicated page (R/W)
Table 181. PAGE_RW register
EMB_
FUNC_LIR
PAGE_
WRITE
PAGE_
READ
0(1)
0(1)
0(1)
0(1)
0(1)
1. This bit must be set to 0 for the correct operation of the device.
Table 182. PAGE_RW register description
Latched interrupt mode for embedded functions. Default value: 0
EMB_FUNC_LIR
(0: embedded functions interrupt request not latched;
1: embedded functions interrupt request latched)
PAGE_WRITE
PAGE_READ
Enables writes to the selected advanced features dedicated page.(1) Default value: 0
(1: enable; 0: disable)
Enables reads from the selected advanced features dedicated page.(1) Default value: 0
(1: enable; 0: disable)
1. Page selected by PAGE_SEL[3:0] in PAGE_SEL (02h) register.
DS13773 - Rev 7
page 89/131
ASM330LHB
FSM_ENABLE_A (46h)
11.18
FSM_ENABLE_A (46h)
Enable FSM register (R/W)
Table 183. FSM_ENABLE_A register
FSM8_EN
FSM7_EN
FSM6_EN
FSM5_EN
FSM4_EN
FSM3_EN
FSM2_EN
FSM1_EN
FSM10_EN
FSM9_EN
Table 184. FSM_ENABLE_A register description
11.19
FSM8_EN
Enables FSM8. Default value: 0 (0: FSM8 disabled; 1: FSM8 enabled)
FSM7_EN
Enables FSM7. Default value: 0 (0: FSM7 disabled; 1: FSM7 enabled)
FSM6_EN
Enables FSM6. Default value: 0 (0: FSM6 disabled; 1: FSM6 enabled)
FSM5_EN
Enables FSM5. Default value: 0 (0: FSM5 disabled; 1: FSM5 enabled)
FSM4_EN
Enables FSM4. Default value: 0 (0: FSM4 disabled; 1: FSM4 enabled)
FSM3_EN
Enables FSM3. Default value: 0 (0: FSM3 disabled; 1: FSM3 enabled)
FSM2_EN
Enables FSM2. Default value: 0 (0: FSM2 disabled; 1: FSM2 enabled)
FSM1_EN
Enables FSM1. Default value: 0 (0: FSM1 disabled; 1: FSM1 enabled)
FSM_ENABLE_B (47h)
Enable FSM register (R/W)
Table 185. FSM_ENABLE_B register
FSM16_EN
FSM15_EN
FSM14_EN
FSM13_EN
FSM12_EN
FSM11_EN
Table 186. FSM_ENABLE_B register description
DS13773 - Rev 7
FSM16_EN
Enables FSM16. Default value: 0 (0: FSM16 disabled; 1: FSM16 enabled)
FSM15_EN
Enables FSM15. Default value: 0 (0: FSM15 disabled; 1: FSM15 enabled)
FSM14_EN
Enables FSM14. Default value: 0 (0: FSM14 disabled; 1: FSM14 enabled)
FSM13_EN
Enables FSM13. Default value: 0 (0: FSM13 disabled; 1: FSM13 enabled)
FSM12_EN
Enables FSM12. Default value: 0 (0: FSM12 disabled; 1: FSM12 enabled)
FSM11_EN
Enables FSM11. Default value: 0 (0: FSM11 disabled; 1: FSM11 enabled)
FSM10_EN
Enables FSM10. Default value: 0 (0: FSM10 disabled; 1: FSM10 enabled)
FSM9_EN
Enables FSM9. Default value: 0 (0: FSM9 disabled; 1: FSM9 enabled)
page 90/131
ASM330LHB
FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h)
11.20
FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h)
FSM long counter status register (R/W)
Long counter value is an unsigned integer value (16-bit format); this value can be reset using the LC_CLEAR bit
in FSM_LONG_COUNTER_CLEAR (4Ah) register.
Table 187. FSM_LONG_COUNTER_L register
FSM_LC_7
FSM_LC_6
FSM_LC_5
FSM_LC_4
FSM_LC_3
FSM_LC_2
FSM_LC_1
FSM_LC_0
FSM_LC_9
FSM_LC_8
FSM_LC_
CLEARED
FSM_LC_
CLEAR
Table 188. FSM_LONG_COUNTER_L register description
FSM_LC_[7:0]
Long counter current value (LSbyte). Default value: 00000000
Table 189. FSM_LONG_COUNTER_H register
FSM_LC_15
FSM_LC_14
FSM_LC_13
FSM_LC_12
FSM_LC_11
FSM_LC_10
Table 190. FSM_LONG_COUNTER_H register description
FSM_LC_[15:8]
11.21
Long counter current value (MSbyte). Default value: 00000000
FSM_LONG_COUNTER_CLEAR (4Ah)
FSM long counter reset register (R/W)
Table 191. FSM_LONG_COUNTER_CLEAR register
0(1)
0(1)
0(1)
0(1)
0(1)
0(1)
1. This bit must be set to 0 for the correct operation of the device.
Table 192. FSM_LONG_COUNTER_CLEAR register description
DS13773 - Rev 7
FSM_LC_CLEARED
This read-only bit is automatically set to 1 when the long counter reset is done. Default value: 0
FSM_LC_CLEAR
Clear FSM long counter value. Default value: 0
page 91/131
ASM330LHB
FSM_OUTS1 (4Ch)
11.22
FSM_OUTS1 (4Ch)
FSM1 output register (R)
Table 193. FSM_OUTS1 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 194. FSM_OUTS1 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS13773 - Rev 7
FSM1 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM1 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM1 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM1 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM1 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM1 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM1 output: positive event detected on the vector.
(0: event not detected; 1: event detected)
FSM1 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 92/131
ASM330LHB
FSM_OUTS2 (4Dh)
11.23
FSM_OUTS2 (4Dh)
FSM2 output register (R)
Table 195. FSM_OUTS2 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 196. FSM_OUTS2 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS13773 - Rev 7
FSM2 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM2 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM2 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM2 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM2 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM2 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM2 output: positive event detected on the vector.
(0: event not detected; 1: event detected)
FSM2 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 93/131
ASM330LHB
FSM_OUTS3 (4Eh)
11.24
FSM_OUTS3 (4Eh)
FSM3 output register (R)
Table 197. FSM_OUTS3 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 198. FSM_OUTS3 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS13773 - Rev 7
FSM3 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM3 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM3 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM3 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM3 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM3 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM3 output: positive event detected on the vector.
(0: event not detected; 1: event detected)
FSM3 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 94/131
ASM330LHB
FSM_OUTS4 (4Fh)
11.25
FSM_OUTS4 (4Fh)
FSM4 output register (R)
Table 199. FSM_OUTS4 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 200. FSM_OUTS4 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS13773 - Rev 7
FSM4 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM4 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM4 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM4 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM4 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM4 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM4 output: positive event detected on the vector.
(0: event not detected; 1: event detected)
FSM4 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 95/131
ASM330LHB
FSM_OUTS5 (50h)
11.26
FSM_OUTS5 (50h)
FSM5 output register (R)
Table 201. FSM_OUTS5 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 202. FSM_OUTS5 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS13773 - Rev 7
FSM5 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM5 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM5 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM5 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM5 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM5 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM5 output: positive event detected on the vector.
(0: event not detected; 1: event detected)
FSM5 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 96/131
ASM330LHB
FSM_OUTS6 (51h)
11.27
FSM_OUTS6 (51h)
FSM6 output register (R)
Table 203. FSM_OUTS6 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 204. FSM_OUTS6 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS13773 - Rev 7
FSM6 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM6 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM6 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM6 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM6 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM6 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM6 output: positive event detected on the vector.
(0: event not detected; 1: event detected)
FSM6 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 97/131
ASM330LHB
FSM_OUTS7 (52h)
11.28
FSM_OUTS7 (52h)
FSM7 output register (R)
Table 205. FSM_OUTS7 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 206. FSM_OUTS7 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS13773 - Rev 7
FSM7 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM7 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM7 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM7 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM7 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM7 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM7 output: positive event detected on the vector.
(0: event not detected; 1: event detected)
FSM7 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 98/131
ASM330LHB
FSM_OUTS8 (53h)
11.29
FSM_OUTS8 (53h)
FSM8 output register (R)
Table 207. FSM_OUTS8 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 208. FSM_OUTS8 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS13773 - Rev 7
FSM8 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM8 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM8 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM8 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM8 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM8 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM8 output: positive event detected on the vector.
(0: event not detected; 1: event detected)
FSM8 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 99/131
ASM330LHB
FSM_OUTS9 (54h)
11.30
FSM_OUTS9 (54h)
FSM9 output register (R)
Table 209. FSM_OUTS9 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 210. FSM_OUTS9 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS13773 - Rev 7
FSM9 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM9 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM9 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM9 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM9 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM9 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM9 output: positive event detected on the vector.
(0: event not detected; 1: event detected)
FSM9 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 100/131
ASM330LHB
FSM_OUTS10 (55h)
11.31
FSM_OUTS10 (55h)
FSM10 output register (R)
Table 211. FSM_OUTS10 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 212. FSM_OUTS10 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS13773 - Rev 7
FSM10 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM10 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM10 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM10 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM10 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM10 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM10 output: positive event detected on the vector.
(0: event not detected; 1: event detected)
FSM10 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 101/131
ASM330LHB
FSM_OUTS11 (56h)
11.32
FSM_OUTS11 (56h)
FSM11 output register (R)
Table 213. FSM_OUTS11 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 214. FSM_OUTS11 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS13773 - Rev 7
FSM11 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM11 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM11 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM11 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM11 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM11 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM11 output: positive event detected on the vector.
(0: event not detected; 1: event detected)
FSM11 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 102/131
ASM330LHB
FSM_OUTS12 (57h)
11.33
FSM_OUTS12 (57h)
FSM12 output register (R)
Table 215. FSM_OUTS12 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 216. FSM_OUTS12 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS13773 - Rev 7
FSM12 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM12 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM12 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM12 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM12 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM12 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM12 output: positive event detected on the vector.
(0: event not detected; 1: event detected)
FSM12 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 103/131
ASM330LHB
FSM_OUTS13 (58h)
11.34
FSM_OUTS13 (58h)
FSM13 output register (R)
Table 217. FSM_OUTS13 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 218. FSM_OUTS13 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS13773 - Rev 7
FSM13 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM13 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM13 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM13 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM13 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM13 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM13 output: positive event detected on the vector.
(0: event not detected; 1: event detected)
FSM13 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 104/131
ASM330LHB
FSM_OUTS14 (59h)
11.35
FSM_OUTS14 (59h)
FSM14 output register (R)
Table 219. FSM_OUTS14 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 220. FSM_OUTS14 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS13773 - Rev 7
FSM14 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM14 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM14 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM14 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM14 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM14 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM14 output: positive event detected on the vector.
(0: event not detected; 1: event detected)
FSM14 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 105/131
ASM330LHB
FSM_OUTS15 (5Ah)
11.36
FSM_OUTS15 (5Ah)
FSM15 output register (R)
Table 221. FSM_OUTS15 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 222. FSM_OUTS15 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS13773 - Rev 7
FSM15 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM15 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM15 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM15 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM15 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM15 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM15 output: positive event detected on the vector.
(0: event not detected; 1: event detected)
FSM15 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 106/131
ASM330LHB
FSM_OUTS16 (5Bh)
11.37
FSM_OUTS16 (5Bh)
FSM16 output register (R)
Table 223. FSM_OUTS16 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
1(2)
1(2)
Table 224. FSM_OUTS16 register description
FSM16 output: positive event detected on the X-axis.
P_X
(0: event not detected; 1: event detected)
FSM16 output: negative event detected on the X-axis.
N_X
(0: event not detected; 1: event detected)
FSM16 output: positive event detected on the Y-axis.
P_Y
(0: event not detected; 1: event detected)
FSM16 output: negative event detected on the Y-axis.
N_Y
(0: event not detected; 1: event detected)
FSM16 output: positive event detected on the Z-axis.
P_Z
(0: event not detected; 1: event detected)
FSM16 output: negative event detected on the Z-axis.
N_Z
(0: event not detected; 1: event detected)
FSM16 output: positive event detected on the vector.
P_V
(0: event not detected; 1: event detected)
FSM16 output: negative event detected on the vector.
N_V
11.38
(0: event not detected; 1: event detected)
EMB_FUNC_ODR_CFG_B (5Fh)
Finite state machine output data rate configuration register (R/W)
Table 225. EMB_FUNC_ODR_CFG_B register
0(1)
1(2)
0(1)
FSM_ODR1
FSM_ODR0
0(1)
1. This bit must be set to 0 for the correct operation of the device.
2. This bit must be set to 1 for the correct operation of the device
Table 226. EMB_FUNC_ODR_CFG_B register description
Finite state machine ODR configuration:
(00: 12.5 Hz;
FSM_ODR[1:0]
01: 26 Hz (default);
10: 52 Hz;
11: 104 Hz)
DS13773 - Rev 7
page 107/131
ASM330LHB
EMB_FUNC_ODR_CFG_C (60h)
11.39
EMB_FUNC_ODR_CFG_C (60h)
Machine learning core output data rate configuration register (R/W)
Table 227. EMB_FUNC_ODR_CFG_C register
0(1)
0(1)
MLC_ODR1
MLC_ODR0
0(1)
1(2)
0(1)
1(2)
0(1)
FSM_INIT
MLC0_
SRC_1
MLC0_
SRC_0
1. This bit must be set to 0 for the correct operation of the device.
2. This bit must be set to 1 for the correct operation of the device.
Table 228. EMB_FUNC_ODR_CFG_C register description
Machine learning core ODR configuration:
(00: 12.5 Hz;
MLC_ODR[1:0]
01: 26 Hz (default);
10: 52 Hz;
11: 104 Hz)
11.40
EMB_FUNC_INIT_B (67h)
Embedded functions initialization register (R/W)
Table 229. EMB_FUNC_INIT_B register
0(1)
0(1)
0(1)
MLC_INIT
0(1)
0(1)
1. This bit must be set to 0 for the correct operation of the device.
Table 230. EMB_FUNC_INIT_B register description
11.41
MLC_INIT
Machine learning core initialization request. Default value: 0
FSM_INIT
FSM initialization request. Default value: 0
MLC0_SRC (70h)
Machine learning core source register (R)
Table 231. MLC0_SRC register
MLC0_
SRC_7
MLC0_
SRC_6
MLC0_
SRC_5
MLC0_
SRC_4
MLC0_
SRC_3
MLC0_
SRC_2
Table 232. MLC0_SRC register description
MLC0_SRC_[7:0]
DS13773 - Rev 7
Output value of MLC0 decision tree
page 108/131
ASM330LHB
MLC1_SRC (71h)
11.42
MLC1_SRC (71h)
Machine learning core source register (R)
Table 233. MLC1_SRC register
MLC1_
SRC_7
MLC1_
SRC_6
MLC1_
SRC_5
MLC1_
SRC_4
MLC1_
SRC_3
MLC1_
SRC_2
MLC1_
SRC_1
MLC1_
SRC_0
MLC2_
SRC_1
MLC2_
SRC_0
MLC3_
SRC_1
MLC3_
SRC_0
MLC4_
SRC_1
MLC4_
SRC_0
Table 234. MLC1_SRC register description
MLC1_SRC_[7:0]
11.43
Output value of MLC1 decision tree
MLC2_SRC (72h)
Machine learning core source register (R)
Table 235. MLC2_SRC register
MLC2_
SRC_7
MLC2_
SRC_6
MLC2_
SRC_5
MLC2_
SRC_4
MLC2_
SRC_3
MLC2_
SRC_2
Table 236. MLC2_SRC register description
MLC2_SRC_[7:0]
11.44
Output value of MLC2 decision tree
MLC3_SRC (73h)
Machine learning core source register (R)
Table 237. MLC3_SRC register
MLC3_
SRC_7
MLC3_
SRC_6
MLC3_
SRC_5
MLC3_
SRC_4
MLC3_
SRC_3
MLC3_
SRC_2
Table 238. MLC3_SRC register description
MLC3_SRC_[7:0]
11.45
Output value of MLC3 decision tree
MLC4_SRC (74h)
Machine learning core source register (R)
Table 239. MLC4_SRC register
MLC4_
SRC_7
MLC4_
SRC_6
MLC4_
SRC_5
MLC4_
SRC_4
MLC4_
SRC_3
MLC4_
SRC_2
Table 240. MLC4_SRC register description
MLC4_SRC_[7:0]
DS13773 - Rev 7
Output value of MLC4 decision tree
page 109/131
ASM330LHB
MLC5_SRC (75h)
11.46
MLC5_SRC (75h)
Machine learning core source register (R)
Table 241. MLC5_SRC register
MLC5_
SRC_7
MLC5_
SRC_6
MLC5_
SRC_5
MLC5_
SRC_4
MLC5_
SRC_3
MLC5_
SRC_2
MLC5_
SRC_1
MLC5_
SRC_0
MLC6_
SRC_1
MLC6_
SRC_0
MLC7_
SRC_1
MLC7_
SRC_0
Table 242. MLC5_SRC register description
MLC5_SRC_[7:0]
11.47
Output value of MLC5 decision tree
MLC6_SRC (76h)
Machine learning core source register (R)
Table 243. MLC6_SRC register
MLC6_
SRC_7
MLC6_
SRC_6
MLC6_
SRC_5
MLC6_
SRC_4
MLC6_
SRC_3
MLC6_
SRC_2
Table 244. MLC6_SRC register description
MLC6_SRC_[7:0]
11.48
Output value of MLC6 decision tree
MLC7_SRC (77h)
Machine learning core source register (R)
Table 245. MLC7_SRC register
MLC7_
SRC_7
MLC7_
SRC_6
MLC7_
SRC_5
MLC7_
SRC_4
MLC7_
SRC_3
MLC7_
SRC_2
Table 246. MLC7_SRC register description
MLC7_SRC_[7:0]
DS13773 - Rev 7
Output value of MLC7 decision tree
page 110/131
ASM330LHB
Embedded advanced features
12
Embedded advanced features
The following table provides a list of the registers for the embedded advanced features page 1. These registers
are accessible when PAGE_SEL[3:0] are set to 0001 in PAGE_SEL (02h).
Table 247. Register address map - embedded advanced features page 1
Register address
Name
Type
Default
Hex
Binary
7A
01111010
00000000
FSM_LC_TIMEOUT_L
R/W
FSM_LC_TIMEOUT_H
R/W
7B
01111011
00000000
FSM_PROGRAMS
R/W
7C
01111100
00000000
FSM_START_ADD_L
R/W
7E
01111110
00000000
FSM_START_ADD_H
R/W
7F
01111111
00000000
Comment
Reserved registers must not be changed. Writing to those registers may cause permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration
values. Their content is automatically restored when the device is powered up.
Write procedure example:
Example: write value 01h in register at address 7Ch (FSM_PROGRAMS) in page 1
1.
Write bit FUNC_CFG_EN = 1
in FUNC_CFG_ACCESS (01h)
// Enable access to embedded functions registers
2.
Write bit PAGE_WRITE = 1
in PAGE_RW (17h) register
// Select write operation mode
3.
Write 0001 in PAGE_SEL[3:0] field
of register PAGE_SEL (02h)
// Select page 1
4.
Write 7Ch in PAGE_ADDR register (08h)
// Set address
5.
Write 01h in PAGE_DATA register (09h)
// Set value to be written
6.
Write bit PAGE_WRITE = 0
in PAGE_RW (17h) register
// Write operation disabled
7.
Write bit FUNC_CFG_EN = 0
in FUNC_CFG_ACCESS (01h)
// Disable access to embedded functions registers
Read procedure example:
Example: read value of register at address 7Ch (FSM_PROGRAMS) in page 1
DS13773 - Rev 7
1.
Write bit FUNC_CFG_EN = 1
in FUNC_CFG_ACCESS (01h)
// Enable access to embedded functions registers
2.
Write bit PAGE_READ = 1
in PAGE_RW (17h) register
// Select read operation mode
3.
Write 0001 in PAGE_SEL[3:0] field
of register PAGE_SEL (02h)
// Select page 1
4.
Write 7Ch in PAGE_ADDR register (08h)
// Set address
5.
Read value of PAGE_DATA register (09h)
// Get register value
6.
Write bit PAGE_READ = 0
in PAGE_RW (17h) register
// Read operation disabled
7.
Write bit FUNC_CFG_EN = 0
in FUNC_CFG_ACCESS (01h)
// Disable access to embedded functions registers
page 111/131
ASM330LHB
Embedded advanced features
Note:
DS13773 - Rev 7
Steps 1 and 2 of both procedures are intended to be performed at the beginning of the procedure. Steps 6 and 7
of both procedures are intended to be performed at the end of the procedure. If the procedure involves multiple
operations, only steps 3, 4 and 5 must be repeated for each operation. If, in particular, the multiple operations
involve consecutive registers, only step 5 can be performed.
page 112/131
ASM330LHB
Embedded advanced features register description
13
Embedded advanced features register description
13.1
Page 1 - Embedded advanced features registers
13.1.1
FSM_LC_TIMEOUT_L (7Ah) and FSM_LC_TIMEOUT_H (7Bh)
FSM long counter timeout register (R/W)
The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reaches
this value, the FSM generates an interrupt.
Table 248. FSM_LC_TIMEOUT_L register
FSM_LC_
TIMEOUT7
FSM_LC_
TIMEOUT6
FSM_LC_
TIMEOUT5
FSM_LC_
TIMEOUT4
FSM_LC_
TIMEOUT3
FSM_LC_
TIMEOUT2
FSM_LC_
TIMEOUT1
FSM_LC_
TIMEOUT0
Table 249. FSM_LC_TIMEOUT_L register description
FSM_LC_TIMEOUT[7:0]
FSM long counter timeout value (LSbyte). Default value: 00000000
Table 250. FSM_LC_TIMEOUT_H register
FSM_LC_
TIMEOUT15
FSM_LC_
TIMEOUT14
FSM_LC_
TIMEOUT13
FSM_LC_
TIMEOUT12
FSM_LC_
TIMEOUT11
FSM_LC_
TIMEOUT10
FSM_LC_
TIMEOUT9
FSM_LC_
TIMEOUT8
Table 251. FSM_LC_TIMEOUT_H register description
FSM_LC_TIMEOUT[15:8]
13.1.2
FSM long counter timeout value (MSbyte). Default value: 00000000
FSM_PROGRAMS (7Ch)
FSM number of programs register (R/W)
Table 252. FSM_PROGRAMS register
FSM_N_
PROG7
FSM_N_
PROG6
FSM_N_
PROG5
FSM_N_
PROG4
FSM_N_
PROG3
FSM_N_
PROG2
FSM_N_
PROG1
FSM_N_
PROG0
Table 253. FSM_PROGRAMS register description
FSM_N_PROG[7:0]
DS13773 - Rev 7
Number of FSM programs; must be less than or equal to 16. Default value: 00000000
page 113/131
ASM330LHB
Page 1 - Embedded advanced features registers
13.1.3
FSM_START_ADD_L (7Eh) and FSM_START_ADD_H (7Fh)
FSM start address register (R/W). First available address is 0x033C.
Table 254. FSM_START_ADD_L register
FSM_
START7
FSM_
START6
FSM_
START5
FSM_
START4
FSM_
START3
FSM_
START2
FSM_
START1
FSM_
START0
FSM_
START9
FSM_
START8
Table 255. FSM_START_ADD_L register description
FSM_START[7:0]
FSM start address value (LSbyte). Default value: 00000000
Table 256. FSM_START_ADD_H register
FSM_
START15
FSM_
START14
FSM_
START13
FSM_
START12
FSM_
START11
FSM_
START10
Table 257. FSM_START_ADD_H register description
FSM_START[15:8]
DS13773 - Rev 7
FSM start address value (MSbyte). Default value: 00000000
page 114/131
ASM330LHB
Soldering information
14
Soldering information
The LGA package is compliant with the ECOPACK and RoHS standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
For land pattern and soldering recommendations, consult technical note TN0018 available on www.st.com.
DS13773 - Rev 7
page 115/131
ASM330LHB
Package information
15
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
15.1
LGA-14L package information
Figure 23. LGA-14L 2.5 x 3.0 x 0.86 mm package outline and mechanical data
Pin1 indicator
C
W
H
0.5
4x
(0.1)
14x
0.5
L
1.5
Pin 1 indicator
1
14x
0.05
TOP VIEW
0.25±0.05
0.475±0.05
C
BOTTOM VIEW
Dimensions are in millimeter unless otherwise specified
General tolerance is +/-0.1mm unless otherwise specified
OUTER DIMENSIONS
ITEM
Length [L]
Width [W]
Height [H]
DIMENSION [mm]
2.50
3.00
0.86
TOLERANCE [mm]
±0.1
±0.1
MA X
DM00249496_5
DS13773 - Rev 7
page 116/131
ASM330LHB
LGA-14 packing information
15.2
LGA-14 packing information
Figure 24. Carrier tape information for LGA-14 package
Figure 25. LGA-14 package orientation in carrier tape
DS13773 - Rev 7
page 117/131
ASM330LHB
LGA-14 packing information
Figure 26. Reel information for carrier tape of LGA-14 package
T
40mm min.
Access hole at
slot location
B
C
N
D
A
Full radius
G measured at hub
Tape slot
in core for
tape start
2.5mm min. width
Table 258. Reel dimensions for carrier tape of LGA-14 package
Reel dimensions (mm)
DS13773 - Rev 7
A (max)
330
B (min)
1.5
C
13 ±0.25
D (min)
20.2
N (min)
60
G
12.4 +2/-0
T (max)
18.4
page 118/131
ASM330LHB
Revision history
Table 259. Document revision history
DS13773 - Rev 7
Date
Version
Changes
12-Jan-2023
6
First public release
01-Feb-2023
7
Minor textual updates
page 119/131
ASM330LHB
Contents
Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2
Embedded low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Finite state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Machine learning core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4
Module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
4.1
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4.2
I²C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5
Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6.1
Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6.2
Zero-g and zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.1
5.2
5.3
6
4.4.1
I²C/SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.1
I²C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.2
SPI bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MIPI I3CSM interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.1
MIPI I3CSM slave interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.2
MIPI I3CSM CCC supported commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I²C/I3C coexistence in ASM330LHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
6.1
Operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2
Gyroscope power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3
Accelerometer power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4
Block diagram of filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.5
DS13773 - Rev 7
6.4.1
Block diagram of the gyroscope filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.4.2
Block diagrams of the accelerometer filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.5.1
Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.5.2
FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
page 120/131
ASM330LHB
Contents
7
6.5.3
Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5.4
Continuous-to-FIFO mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5.5
Bypass-to-continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5.6
Bypass-to-FIFO mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5.7
FIFO reading procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
7.1
ASM330LHB electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
9
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
9.1
FUNC_CFG_ACCESS (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.2
PIN_CTRL (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.3
FIFO_CTRL1 (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.4
FIFO_CTRL2 (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.5
FIFO_CTRL3 (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.6
FIFO_CTRL4 (0Ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.7
COUNTER_BDR_REG1 (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.8
COUNTER_BDR_REG2 (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.9
INT1_CTRL (0Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.10
INT2_CTRL (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.11
WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.12
CTRL1_XL (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.13
CTRL2_G (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.14
CTRL3_C (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.15
CTRL4_C (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.16
CTRL5_C (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.17
CTRL6_C (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.18
CTRL7_G (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.19
CTRL8_XL (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.20
CTRL9_XL (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.21
CTRL10_C (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.22
ALL_INT_SRC (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.23
WAKE_UP_SRC (1Bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.24
DRD_SRC (1Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.25
STATUS_REG (1Eh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.26
OUT_TEMP_L (20h), OUT_TEMP_H (21h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.27
OUTX_H_C (23h), OUTX_L_G (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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9.28
OUTY_H_G (25h), OUTY_L_G (24h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.29
OUTZ_H_G (27h), OUTZ_L_G (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.30
OUTX_H_A (29h), OUTX_L_A (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.31
OUTY_H_A (2Bh), OUTY_L_A (2Ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.32
OUTZ_H_A (2Dh), OUTZ_L_A (2Ch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.33
EMB_FUNC_STATUS_MAINPAGE (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.34
FSM_STATUS_A_MAINPAGE (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.35
FSM_STATUS_B_MAINPAGE (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.36
MLC_STATUS_MAINPAGE (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.37
FIFO_STATUS1 (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.38
FIFO_STATUS2 (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.39
TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h) 65
9.40
INT_CFG0 (56h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.41
INT_CFG1 (58h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.42
THS_6D (59h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.43
WAKE_UP_THS (5Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.44
WAKE_UP_DUR (5Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.45
FREE_FALL (5Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.46
MD1_CFG (5Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.47
MD2_CFG (5Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9.48
I3C_BUS_AVB (62h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.49
INTERNAL_FREQ_FINE (63h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
9.50
X_OFS_USR (73h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9.51
Y_OFS_USR (74h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9.52
Z_OFS_USR (75h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9.53
FIFO_DATA_OUT_TAG (78h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
9.54
FIFO_DATA_OUT_X_H (7Ah) and FIFO_DATA_OUT_X_L (79h) . . . . . . . . . . . . . . . . . . . . . 75
9.55
FIFO_DATA_OUT_Y_H (7Ch) and FIFO_DATA_OUT_Y_L (7Bh) . . . . . . . . . . . . . . . . . . . . . 75
9.56
FIFO_DATA_OUT_Z_H (7Eh) and FIFO_DATA_OUT_Z_L (7Dh) . . . . . . . . . . . . . . . . . . . . . 75
10
Embedded functions register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
11
Embedded functions register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
11.1
PAGE_SEL (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
11.2
EMB_FUNC_EN_B (05h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
11.3
PAGE_ADDRESS (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
11.4
PAGE_VALUE (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
11.5
EMB_FUNC_INT1 (0Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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11.6
FSM_INT1_A (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.7
FSM_INT1_B (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
11.8
MLC_INT1 (0Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.9
EMB_FUNC_INT2 (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
11.10 FSM_INT2_A (0Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
11.11 FSM_INT2_B (10h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.12 MLC_INT2 (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.13 EMB_FUNC_STATUS (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.14 FSM_STATUS_A (13h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.15 FSM_STATUS_B (14h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.16 MLC_STATUS (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.17 PAGE_RW (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.18 FSM_ENABLE_A (46h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.19 FSM_ENABLE_B (47h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.20 FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h) . . . . . . . . . . . . . . . 91
11.21 FSM_LONG_COUNTER_CLEAR (4Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.22 FSM_OUTS1 (4Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.23 FSM_OUTS2 (4Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.24 FSM_OUTS3 (4Eh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.25 FSM_OUTS4 (4Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.26 FSM_OUTS5 (50h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.27 FSM_OUTS6 (51h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.28 FSM_OUTS7 (52h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
11.29 FSM_OUTS8 (53h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11.30 FSM_OUTS9 (54h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
11.31 FSM_OUTS10 (55h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.32 FSM_OUTS11 (56h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
11.33 FSM_OUTS12 (57h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.34 FSM_OUTS13 (58h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
11.35 FSM_OUTS14 (59h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
11.36 FSM_OUTS15 (5Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.37 FSM_OUTS16 (5Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.38 EMB_FUNC_ODR_CFG_B (5Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.39 EMB_FUNC_ODR_CFG_C (60h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.40 EMB_FUNC_INIT_B (67h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.41 MLC0_SRC (70h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
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11.42 MLC1_SRC (71h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.43 MLC2_SRC (72h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.44 MLC3_SRC (73h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.45 MLC4_SRC (74h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.46 MLC5_SRC (75h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
11.47 MLC6_SRC (76h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
11.48 MLC7_SRC (77h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
12
Embedded advanced features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
13
Embedded advanced features register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.1
Page 1 - Embedded advanced features registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.1.1
FSM_LC_TIMEOUT_L (7Ah) and FSM_LC_TIMEOUT_H (7Bh). . . . . . . . . . . . . . . . . . . 113
13.1.2
FSM_PROGRAMS (7Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.1.3
FSM_START_ADD_L (7Eh) and FSM_START_ADD_H (7Fh) . . . . . . . . . . . . . . . . . . . . 114
14
Soldering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
15
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
15.1
LGA-14L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
15.2
LGA-14 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI slave timing values (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I²C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I²C high-speed mode specifications at 1 MHz . . . . . . . . . . . . . . . . . . . . . .
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I²C terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAD+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transfer when master is writing one byte to slave. . . . . . . . . . . . . . . . . . . .
Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . .
Transfer when master is receiving (reading) one byte of data from slave . . . .
Transfer when master is receiving (reading) multiple bytes of data from slave
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. 8
. 9
11
12
13
14
15
16
19
19
20
20
20
20
20
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
MIPI I3CSM CCC commands . . . . . . . . . . . .
Gyroscope LPF2 bandwidth selection . . . . . .
Internal pin status . . . . . . . . . . . . . . . . . . .
Registers address map . . . . . . . . . . . . . . . .
FUNC_CFG_ACCESS register . . . . . . . . . .
FUNC_CFG_ACCESS register description . .
PIN_CTRL register. . . . . . . . . . . . . . . . . . .
PIN_CTRL register description . . . . . . . . . .
FIFO_CTRL1 register . . . . . . . . . . . . . . . . .
FIFO_CTRL1 register description. . . . . . . . .
FIFO_CTRL2 register . . . . . . . . . . . . . . . . .
FIFO_CTRL2 register . . . . . . . . . . . . . . . . .
FIFO_CTRL3 register . . . . . . . . . . . . . . . . .
FIFO_CTRL3 register description. . . . . . . . .
FIFO_CTRL4 register . . . . . . . . . . . . . . . . .
FIFO_CTRL4 register description. . . . . . . . .
COUNTER_BDR_REG1 register . . . . . . . . .
COUNTER_BDR_REG1 register description .
COUNTER_BDR_REG2 register . . . . . . . . .
COUNTER_BDR_REG2 register description .
INT1_CTRL register . . . . . . . . . . . . . . . . . .
INT1_CTRL register description . . . . . . . . . .
INT2_CTRL register . . . . . . . . . . . . . . . . . .
INT2_CTRL register description . . . . . . . . . .
Who_Am_I register . . . . . . . . . . . . . . . . . .
CTRL1_XL register . . . . . . . . . . . . . . . . . .
CTRL1_XL register description . . . . . . . . . .
Accelerometer ODR register setting . . . . . . .
CTRL2_G register . . . . . . . . . . . . . . . . . . .
CTRL2_G register description . . . . . . . . . . .
Gyroscope ODR configuration setting . . . . . .
CTRL3_C register . . . . . . . . . . . . . . . . . . .
CTRL3_C register description . . . . . . . . . . .
CTRL4_C register . . . . . . . . . . . . . . . . . . .
CTRL4_C register description . . . . . . . . . . .
CTRL5_C register . . . . . . . . . . . . . . . . . . .
CTRL5_C register description . . . . . . . . . . .
Angular rate sensor self-test mode selection .
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25
30
36
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51
DS13773 - Rev 7
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page 125/131
ASM330LHB
List of tables
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Linear acceleration sensor self-test mode selection . . .
CTRL6_C register . . . . . . . . . . . . . . . . . . . . . . . . . .
CTRL6_C register description . . . . . . . . . . . . . . . . . .
Trigger mode selection . . . . . . . . . . . . . . . . . . . . . . .
Gyroscope LPF1 bandwidth selection . . . . . . . . . . . . .
CTRL7_G register . . . . . . . . . . . . . . . . . . . . . . . . . .
CTRL8_XL register . . . . . . . . . . . . . . . . . . . . . . . . .
Accelerometer bandwidth configurations . . . . . . . . . . .
CTRL9_XL register . . . . . . . . . . . . . . . . . . . . . . . . .
CTRL9_XL register description . . . . . . . . . . . . . . . . .
CTRL10_C register . . . . . . . . . . . . . . . . . . . . . . . . .
CTRL10_C register description . . . . . . . . . . . . . . . . .
ALL_INT_SRC register . . . . . . . . . . . . . . . . . . . . . . .
ALL_INT_SRC register description. . . . . . . . . . . . . . .
WAKE_UP_SRC register . . . . . . . . . . . . . . . . . . . . .
WAKE_UP_SRC register description . . . . . . . . . . . . .
D6D_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . .
D6D_SRC register description . . . . . . . . . . . . . . . . . .
STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . .
STATUS_REG register description . . . . . . . . . . . . . . .
OUT_TEMP_L register . . . . . . . . . . . . . . . . . . . . . . .
OUT_TEMP_H register. . . . . . . . . . . . . . . . . . . . . . .
OUT_TEMP register description. . . . . . . . . . . . . . . . .
OUTX_H_G register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTX_L_G register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTX_H_G, OUTX_L_G register description . . . . . . .
OUTY_H_G register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTY_L_G register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTY_H_G, OUTY_L_G register description . . . . . . .
OUTZ_H_G register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTZ_L_G register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTZ_H_G, OUTZ_L_G register description. . . . . . . .
OUTX_H_A register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTX_L_A register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTX_H_A, OUTX_L_A register description . . . . . . . .
OUTY_H_A register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTY_L_A register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTY_H_A, OUTY_L_A register description . . . . . . . .
OUTZ_H_A register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTZ_L_A register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTZ_H_A, OUTZ_L_A register description . . . . . . . .
EMB_FUNC_STATUS_MAINPAGE register . . . . . . . .
EMB_FUNC_STATUS_MAINPAGE register description
FSM_STATUS_A_MAINPAGE register . . . . . . . . . . . .
FSM_STATUS_A_MAINPAGE register description . . . .
FSM_STATUS_B_MAINPAGE register . . . . . . . . . . . .
FSM_STATUS_B_MAINPAGE register description . . . .
MLC_STATUS_MAINPAGE register . . . . . . . . . . . . . .
MLC_STATUS_MAINPAGE register description . . . . . .
FIFO_STATUS1 register . . . . . . . . . . . . . . . . . . . . . .
FIFO_STATUS1 register description . . . . . . . . . . . . . .
FIFO_STATUS2 register . . . . . . . . . . . . . . . . . . . . . .
FIFO_STATUS2 register description . . . . . . . . . . . . . .
TIMESTAMP3 register . . . . . . . . . . . . . . . . . . . . . . .
TIMESTAMP2 register . . . . . . . . . . . . . . . . . . . . . . .
DS13773 - Rev 7
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51
52
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56
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page 126/131
ASM330LHB
List of tables
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
Table 136.
Table 137.
Table 138.
Table 139.
Table 140.
Table 141.
Table 142.
Table 143.
Table 144.
Table 145.
Table 146.
Table 147.
Table 148.
Table 149.
Table 150.
Table 151.
Table 152.
Table 153.
Table 154.
Table 155.
Table 156.
Table 157.
Table 158.
Table 159.
Table 160.
Table 161.
Table 162.
Table 163.
TIMESTAMP1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMESTAMP0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INT_CFG0 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INT_CFG0 register description . . . . . . . . . . . . . . . . . . . . . . . . . .
INT_CFG1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INT_CFG1 register description . . . . . . . . . . . . . . . . . . . . . . . . . .
THS_6D register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
THS_6D register description . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WAKE_UP_THS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WAKE_UP_THS register description . . . . . . . . . . . . . . . . . . . . . .
WAKE_UP_DUR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WAKE_UP_DUR register description . . . . . . . . . . . . . . . . . . . . . .
FREE_FALL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FREE_FALL register description . . . . . . . . . . . . . . . . . . . . . . . . .
MD1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MD1_CFG register description. . . . . . . . . . . . . . . . . . . . . . . . . . .
MD2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MD2_CFG register description. . . . . . . . . . . . . . . . . . . . . . . . . . .
I3C_BUS_AVB register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I3C_BUS_AVB register description. . . . . . . . . . . . . . . . . . . . . . . .
INTERNAL_FREQ_FINE register. . . . . . . . . . . . . . . . . . . . . . . . .
INTERNAL_FREQ_FINE register description. . . . . . . . . . . . . . . . .
X_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
X_OFS_USR register description . . . . . . . . . . . . . . . . . . . . . . . . .
Y_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z_OFS_USR register description . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_DATA_OUT_TAG register. . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_DATA_OUT_TAG register description . . . . . . . . . . . . . . . . .
FIFO tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_DATA_OUT_X_H register. . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_DATA_OUT_X_L register . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_DATA_OUT_X_H, FIFO_DATA_OUT_X_L register description
FIFO_DATA_OUT_Y_H register. . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_DATA_OUT_Y_L register . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_DATA_OUT_Y_H, FIFO_DATA_OUT_Y_L register description
FIFO_DATA_OUT_Z_H register. . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_DATA_OUT_Z_L register . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_DATA_OUT_Z_H, FIFO_DATA_OUT_Z_L register description
Register address map - embedded functions . . . . . . . . . . . . . . . . .
PAGE_SEL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE_SEL register description . . . . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_EN_B register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_EN_B register description . . . . . . . . . . . . . . . . . . . .
PAGE_ADDRESS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE_ADDRESS register description . . . . . . . . . . . . . . . . . . . . .
PAGE_VALUE register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE_VALUE register description . . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_INT1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_INT1 register description . . . . . . . . . . . . . . . . . . . . .
FSM_INT1_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_INT1_A register description. . . . . . . . . . . . . . . . . . . . . . . . .
FSM_INT1_B register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_INT1_B register description. . . . . . . . . . . . . . . . . . . . . . . . .
MLC_INT1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS13773 - Rev 7
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page 127/131
ASM330LHB
List of tables
Table 164.
Table 165.
Table 166.
Table 167.
Table 168.
Table 169.
Table 170.
Table 171.
Table 172.
Table 173.
Table 174.
Table 175.
Table 176.
Table 177.
Table 178.
Table 179.
Table 180.
Table 181.
Table 182.
Table 183.
Table 184.
Table 185.
Table 186.
Table 187.
Table 188.
Table 189.
Table 190.
Table 191.
Table 192.
Table 193.
Table 194.
Table 195.
Table 196.
Table 197.
Table 198.
Table 199.
Table 200.
Table 201.
Table 202.
Table 203.
Table 204.
Table 205.
Table 206.
Table 207.
Table 208.
Table 209.
Table 210.
Table 211.
Table 212.
Table 213.
Table 214.
Table 215.
Table 216.
Table 217.
Table 218.
MLC_INT1 register description . . . . . . . . . . . . . . . .
EMB_FUNC_INT2 register . . . . . . . . . . . . . . . . . . .
EMB_FUNC_INT2 register description . . . . . . . . . . .
FSM_INT2_A register. . . . . . . . . . . . . . . . . . . . . . .
FSM_INT2_A register description. . . . . . . . . . . . . . .
FSM_INT2_B register. . . . . . . . . . . . . . . . . . . . . . .
FSM_INT2_B register description. . . . . . . . . . . . . . .
MLC_INT2 register. . . . . . . . . . . . . . . . . . . . . . . . .
MLC_INT2 register description . . . . . . . . . . . . . . . .
EMB_FUNC_STATUS register. . . . . . . . . . . . . . . . .
EMB_FUNC_STATUS register description. . . . . . . . .
FSM_STATUS_A register . . . . . . . . . . . . . . . . . . . .
FSM_STATUS_A register description . . . . . . . . . . . .
FSM_STATUS_B register . . . . . . . . . . . . . . . . . . . .
FSM_STATUS_B register description . . . . . . . . . . . .
MLC_STATUS register . . . . . . . . . . . . . . . . . . . . . .
MLC_STATUS register description . . . . . . . . . . . . . .
PAGE_RW register . . . . . . . . . . . . . . . . . . . . . . . .
PAGE_RW register description . . . . . . . . . . . . . . . .
FSM_ENABLE_A register . . . . . . . . . . . . . . . . . . . .
FSM_ENABLE_A register description . . . . . . . . . . . .
FSM_ENABLE_B register . . . . . . . . . . . . . . . . . . . .
FSM_ENABLE_B register description . . . . . . . . . . . .
FSM_LONG_COUNTER_L register . . . . . . . . . . . . .
FSM_LONG_COUNTER_L register description . . . . .
FSM_LONG_COUNTER_H register . . . . . . . . . . . . .
FSM_LONG_COUNTER_H register description. . . . .
FSM_LONG_COUNTER_CLEAR register. . . . . . . . .
FSM_LONG_COUNTER_CLEAR register description.
FSM_OUTS1 register . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS1 register description. . . . . . . . . . . . . . .
FSM_OUTS2 register . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS2 register description. . . . . . . . . . . . . . .
FSM_OUTS3 register . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS3 register description. . . . . . . . . . . . . . .
FSM_OUTS4 register . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS4 register description. . . . . . . . . . . . . . .
FSM_OUTS5 register . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS5 register description. . . . . . . . . . . . . . .
FSM_OUTS6 register . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS6 register description. . . . . . . . . . . . . . .
FSM_OUTS7 register . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS7 register description. . . . . . . . . . . . . . .
FSM_OUTS8 register . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS8 register description. . . . . . . . . . . . . . .
FSM_OUTS9 register . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS9 register description. . . . . . . . . . . . . . .
FSM_OUTS10 register . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS10 register description . . . . . . . . . . . . . .
FSM_OUTS11 register . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS11 register description . . . . . . . . . . . . . .
FSM_OUTS12 register . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS12 register description . . . . . . . . . . . . . .
FSM_OUTS13 register . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS13 register description . . . . . . . . . . . . . .
DS13773 - Rev 7
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page 128/131
ASM330LHB
List of tables
Table 219.
Table 220.
Table 221.
Table 222.
Table 223.
Table 224.
Table 225.
Table 226.
Table 227.
Table 228.
Table 229.
Table 230.
Table 231.
Table 232.
Table 233.
Table 234.
Table 235.
Table 236.
Table 237.
Table 238.
Table 239.
Table 240.
Table 241.
Table 242.
Table 243.
Table 244.
Table 245.
Table 246.
Table 247.
Table 248.
Table 249.
Table 250.
Table 251.
Table 252.
Table 253.
Table 254.
Table 255.
Table 256.
Table 257.
Table 258.
Table 259.
FSM_OUTS14 register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS14 register description . . . . . . . . . . . . . . . . . . . .
FSM_OUTS15 register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS15 register description . . . . . . . . . . . . . . . . . . . .
FSM_OUTS16 register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS16 register description . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_ODR_CFG_B register . . . . . . . . . . . . . . . . . . .
EMB_FUNC_ODR_CFG_B register description . . . . . . . . . . .
EMB_FUNC_ODR_CFG_C register . . . . . . . . . . . . . . . . . . .
EMB_FUNC_ODR_CFG_C register description . . . . . . . . . . .
EMB_FUNC_INIT_B register . . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_INIT_B register description. . . . . . . . . . . . . . . .
MLC0_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MLC0_SRC register description . . . . . . . . . . . . . . . . . . . . . .
MLC1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MLC1_SRC register description . . . . . . . . . . . . . . . . . . . . . .
MLC2_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MLC2_SRC register description . . . . . . . . . . . . . . . . . . . . . .
MLC3_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MLC3_SRC register description . . . . . . . . . . . . . . . . . . . . . .
MLC4_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MLC4_SRC register description . . . . . . . . . . . . . . . . . . . . . .
MLC5_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MLC5_SRC register description . . . . . . . . . . . . . . . . . . . . . .
MLC6_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MLC6_SRC register description . . . . . . . . . . . . . . . . . . . . . .
MLC7_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MLC7_SRC register description . . . . . . . . . . . . . . . . . . . . . .
Register address map - embedded advanced features page 1 .
FSM_LC_TIMEOUT_L register . . . . . . . . . . . . . . . . . . . . . .
FSM_LC_TIMEOUT_L register description . . . . . . . . . . . . . .
FSM_LC_TIMEOUT_H register . . . . . . . . . . . . . . . . . . . . . .
FSM_LC_TIMEOUT_H register description . . . . . . . . . . . . . .
FSM_PROGRAMS register . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_PROGRAMS register description. . . . . . . . . . . . . . . . .
FSM_START_ADD_L register . . . . . . . . . . . . . . . . . . . . . . .
FSM_START_ADD_L register description . . . . . . . . . . . . . . .
FSM_START_ADD_H register . . . . . . . . . . . . . . . . . . . . . . .
FSM_START_ADD_H register description. . . . . . . . . . . . . . .
Reel dimensions for carrier tape of LGA-14 package . . . . . . .
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . .
DS13773 - Rev 7
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105
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109
.110
.110
.110
.110
.110
.110
.111
.113
.113
.113
.113
.113
.113
.114
.114
.114
.114
.118
.119
page 129/131
ASM330LHB
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
DS13773 - Rev 7
Generic state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State machine in the ASM330LHB . . . . . . . . . . . . . . . . . . . . . . .
Machine learning core in the ASM330LHB . . . . . . . . . . . . . . . . . .
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI slave timing diagram (in mode 3) . . . . . . . . . . . . . . . . . . . . .
I²C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference design - block diagram, I²C communication protocol. . . .
Reference design - block diagram, SPI4 communication protocol . .
Read and write protocol (in mode 3) . . . . . . . . . . . . . . . . . . . . . .
SPI read protocol (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiple byte SPI read protocol (2-byte example) (in mode 3) . . . . .
SPI write protocol (in mode 3). . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiple byte SPI write protocol (2-byte example) (in mode 3) . . . . .
SPI read protocol in 3-wire mode (in mode 3) . . . . . . . . . . . . . . . .
I²C and I3C both active (INT1 pin not connected) . . . . . . . . . . . . .
Only I3C active (INT1 pin connected to Vdd_IO) . . . . . . . . . . . . . .
Block diagram of filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gyroscope filtering chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accelerometer chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accelerometer composite filter . . . . . . . . . . . . . . . . . . . . . . . . . .
ASM330LHB electrical connections . . . . . . . . . . . . . . . . . . . . . . .
Accelerometer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .
LGA-14L 2.5 x 3.0 x 0.86 mm package outline and mechanical data
Carrier tape information for LGA-14 package . . . . . . . . . . . . . . . .
LGA-14 package orientation in carrier tape. . . . . . . . . . . . . . . . . .
Reel information for carrier tape of LGA-14 package . . . . . . . . . . .
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page 130/131
ASM330LHB
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