BALF-NRF01J5

BALF-NRF01J5 Datasheet 50 Ω ultra thin balun with integrated harmonic filter / conjugate match balun to nRF51822-CTAA/CTAC in WLCSP Features • • • 50 Ω nominal input / conjugate match to Nordic Semiconductor chips nRF51822 WLCSP Low insertion loss Low amplitude imbalance Low phase imbalance • • • • Small footprint: < 1.2 mm2 Extra low profile < 350 μm after reflow High RF performance RF BOM and area reduction • Applications • • • 2.45 GHz impedance matched balun filter Optimized for Nordic's chip set nRF51822-CTAA, CTAC Wearable applications Description This device is an ultraminiature extra thin balun that integrates matching network and harmonics filter. Product status Matching impedance has been customized for the nRF51822-CTAA and CTAC WLCSP Nordic Semiconductor circuits. BALF-NRF01J5 Based on IPD technology on high resistivity silicium it optimizes the RF performance. The BALF-NRF01J5 has been tested and approved by Nordic Semiconductor. STMicroelectronics qualified this product intended to be used in System in Package module based on standard reliability procedure. For more details, please contact ST representatives. It is the responsibility of the customer to perform qualification reliability verifications as it is related to customer specific application / mission profile and module design / process. DS12205 - Rev 3 - April 2018 For further information contact your local STMicroelectronics sales office. www.st.com BALF-NRF01J5 Characteristics 1 Characteristics Table 1. Absolute ratings (limiting values) Value Symbol Parameter PIN Min. Typ. Max. Input power RFIN VESD TOP - ESD ratings human body model (JESD22-A114-C), all I/O one at a time while others connected to GND 2000 - ESD ratings charge device model (JESD22-C101-C) 500 - ESD ratings machine model, all I/O 200 - Operating temperature -40 - 20 Unit dBm V +85 °C Table 2. Impedances (Tamb = 25 °C) Symbol ZOUT ZIN Value Parameter Unit Min. Typ. Max. Nominal differential output impedance - matched - Ω Nominal input impedance - 50 - Ω Table 3. RF performances (Tamb = 25 °C) Symbol DS12205 - Rev 3 Value Parameter f Frequency range (bandwidth) IL Insertion loss in bandwidth RL Return loss in bandwidth Min. Typ. 2400 2.2 9 12 Max. Unit 2540 MHz 2.4 dB dB φimb Phase imbalance -7.2 7 7.2 ° Aimb Amplitude imbalance -0.5 0.3 0.5 dB 2f0 2nd harmonic S21 attenuation 4880 MHz 12 13.5 dB 3f0 3rd harmonic S21 attenuation 7320 MHz 24 25 dB page 2/9 BALF-NRF01J5 On-board measurements 1.1 On-board measurements Figure 1. Transmission (Tamb = 25 °C) Figure 2. Insertion loss (Tamb = 25 °C) Figure 3. Return loss on SE port (Tamb = 25 °C) Figure 4. Return loss on DIFF port (Tamb = 25 °C) Figure 5. Amplitude imbalance (Tamb = 25 °C) Figure 6. Phase imbalance (Tamb = 25 °C) DS12205 - Rev 3 page 3/9 BALF-NRF01J5 Package information 2 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 2.1 Ultra thin Flip-Chip 5 bumps package information • • Epoxy meets UL94, V0 Lead-free package Figure 7. Ultra thin Flip-Chip 5 bumps package outline Table 4. Ultra thin Flip-Chip 5 bumps package mechanical data Parameter DS12205 - Rev 3 Description Min. Typ. Max. X X dimension of the die 1315 1345 1375 Y Y dimension of the die 785 815 845 A X pitch 500 B Y pitch 400 A1 Distance from bump to edge of die on X axis 172.5 B1 Distance from bump to edge of die on Y axis 207.5 B2 Distance from bump to center of die on Y axis 200 D Bump diameter 202 227 252 T Substrate thickness 190 200 210 H Bump height 117 142 167 Unit µm page 4/9 BALF-NRF01J5 Ultra thin Flip-Chip 5 bumps package information Figure 8. Recommended land pattern Note: Screenprinting, stencil windows 290 x 290 x 100 µm3 (coeff 0.725) Note: to achieve minimum component height after PCB reflow, the below recommendations must be followed : in assembly process, a flux must be used, not a solder paste DS12205 - Rev 3 page 5/9 BALF-NRF01J5 Flip-chip 5 bumps packing information Figure 9. PCB stack-up recommendation 2.2 Flip-chip 5 bumps packing information Figure 10. Marking Note: More packing information is available in the application note: • AN2348 Flip-Chip: “Package description and recommendations for use” Figure 11. Footprint - non solder mask defined DS12205 - Rev 3 Figure 12. Footprint - solder mask defined page 6/9 BALF-NRF01J5 Ordering information 3 Ordering information Table 5. Ordering information DS12205 - Rev 3 Order code Marking Package Weight Base qty. Delivery mode BALF-NRF01J5 TL Flip-Chip 5 bumps 0.631 mg 5000 Tape and reel page 7/9 BALF-NRF01J5 Revision history Table 6. Document revision history DS12205 - Rev 3 Date Revision Changes 20-Jun-2017 1 Initial release. 22-Feb-2018 2 Updated Description and Table 4. Ultra thin Flip-Chip 5 bumps package mechanical data. 04-Apr-018 3 Updated Table 4. Ultra thin Flip-Chip 5 bumps package mechanical data. page 8/9 BALF-NRF01J5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS12205 - Rev 3 page 9/9