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BALF-SPI2-01D3

BALF-SPI2-01D3

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    FlipChip

  • 描述:

    BALF-SPI2-01D3

  • 数据手册
  • 价格&库存
BALF-SPI2-01D3 数据手册
BALF-SPI2-01D3 Datasheet 50 Ω nominal input / conjugate matched balun to ST S2-LP,860-930 MHz with integrated harmonic filter Features • • • • • • • 50 Ω nominal input / conjugate matched to ST S2-LP for 860 - 930 MHz frequency operation Low insertion loss Low amplitude imbalance Low phase imbalance Small footprint Very low profile < 620 μm after reflow High RF performance RF BOM and area reduction • ECOPACK®2 compliant component • Flip-Chip (6 bumps) package GND RXP ANT RXN GND TX Applications • • 860 - 930 MHz impedance matched balun filter Optimized for ST S2-LP sub GHz RFIC Description Product status This device is an ultra-miniature balun. The BALF-SPI2-01D3 integrates matching network and harmonics filter. Matching impedance has been customized for the ST S2-LP transceiver. The BALF-SPI2-01D3 uses STMicroelectronics IPD technology on non-conductive glass substrate which optimize RF performance. BALF-SPI2-01D3 DS12249 - Rev 2 - February 2018 For further information contact your local STMicroelectronics sales office. www.st.com BALF-SPI2-01D3 Characteristics 1 Characteristics Table 1. Absolute ratings (Tamb = 25 °C) Symbol Parameter PIN Input power RFIN VESD TOP Value Unit 20 dBm ESD ratings human body model (JESD22-A114-C), all I/O one at a time while others connected to GND 2000 ESD ratings machine model, all I/O 200 V Operating temperature -40 to +105 °C Table 2. Impedances (Tamb = 25 °C) Symbol Value Parameter ZRX Nominal differential RX balun impedance ZTX Nominal TX filter impedance ZANT Antenna impedance Unit Min. Typ. Max. - matched ST S2-LP - Ω - 50 - Ω Table 3. Electrical characteristics and RF performances (Tamb = 25 °C) Symbol f Test condition Frequency range (bandwidth) Value Min. Typ. 860 Max. Unit 930 MHz IL_RX-ANT Insertion loss in bandwidth without mismatch loss (RX balun) 1.7 2.0 dB IL_TX-ANT Insertion loss in bandwidth without mismatch loss (TX filter) 1.7 2.1 dB RL_RX-ANT Input return loss in bandwidth (RX balun) 10 14 dB RL_TX-ANT Input return loss in bandwidth (TX filter) 15 20 dB | ɸimb | Output phase imbalance (RX balun) - absolute value 5 9 13 ° | Aimb | Output amplitude imbalance (RX balun) - absolute value 1.4 1.6 1.8 dB Attenuation at 2fo 40 45 Attenuation at 3fo 47 51 Attenuation at 4fo 60 65 Attenuation at 5fo 66 72 Attenuation at 6fo 50 57 Attenuation at 7fo 46 50 Att DS12249 - Rev 2 Parameter Harmonic levels (TX filter) dB page 2/13 BALF-SPI2-01D3 RF measurements (Rx balun) 1.1 RF measurements (Rx balun) Figure 2. Return loss on antenna Figure 1. Insertion loss (dB) (dB) 0 0.0 -0.2 -0.4 -5 -0.6 -0.8 -10 -1.0 -1.2 -15 -1.4 -1.6 -20 -1.8 -2.0 f(MHz) -2.2 860 870 880 890 900 910 920 f(MHz) -25 860 930 870 Figure 3. Amplitude imbalance 2.0 880 890 900 910 920 930 Figure 4. Phase imbalance (dB) (deg) 15 1.5 10 1.0 5 0.5 0.0 0 -0.5 -5 -1.0 -10 -1.5 f(MHz) -2.0 860 DS12249 - Rev 2 870 880 890 900 910 920 930 f(MHz) -15 860 870 880 890 900 910 920 930 page 3/13 BALF-SPI2-01D3 RF measurements (Tx filter) 1.2 RF measurements (Tx filter) Figure 6. Insertion loss Figure 5. Transmission (dB) H1 H2 H4 H3 H6 H5 H7 0.0 0 (dB) -0.2 -0.4 -20 -0.6 -0.8 -40 -1.0 -1.2 -60 -1.4 -1.6 -1.8 -80 -2.0 f(GHz) -100 0 1 2 3 4 5 6 7 f(MHz) -2.2 8 860 870 880 890 900 910 920 930 Figure 7. Return loss on antenna (dB) 0 -5 -10 -15 -20 f(MHz) -25 860 DS12249 - Rev 2 870 880 890 900 910 920 930 page 4/13 BALF-SPI2-01D3 ST S2-LP evaluation board with BALF-SPI2-01D3 1.3 ST S2-LP evaluation board with BALF-SPI2-01D3 Figure 8. Evaluation board with BALF-SPI2-01D3 DS12249 - Rev 2 page 5/13 BALF-SPI2-01D3 Package information 2 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 2.1 Flip-Chip 6 bumps package information Figure 9. Flip-Chip 6 bumps package outline (bottom and side view) D1 D2 A2 fD1 A1 fE2 fD2 E1 E fE1 Diam : b D A Table 4. Flip-Chip 6 bumps dimensions (in mm) Parameter Min. Typ. Max. A 0.580 0.630 0.680 A1 0.180 0.205 0.230 A2 0.380 0.400 0.420 b 0.230 0.255 0.280 D 2.050 2.100 2.150 D1 1.210 D2 0.500 E DS12249 - Rev 2 1.500 1.550 E1 1.060 fD1 0.195 fD2 0.195 fE1 0.195 fE2 0.295 1.600 page 6/13 BALF-SPI2-01D3 Flip-chip 6 bumps packing information 2.2 Flip-chip 6 bumps packing information Figure 10. Marking Dot, ST logo ECOPACK grade xx = marking z = manufacturing location yww = datecode x x z y ww Figure 11. Flip Chip tape and reel specifications Dot identifying Pin A1 location 2.0 Ø 1.50 4.0 8.0 3.5 2.19 1.75 0.22 x x z y ww x x z y ww x x z y ww 1.64 4.0 0.72 All dimensions are typical values in mm Note: DS12249 - Rev 2 User direction of unreeling More packing information is available in the application note: • AN2348 Flip-Chip: “Package description and recommendations for use” page 7/13 BALF-SPI2-01D3 PCB assembly recommendations 3 PCB assembly recommendations 3.1 Land pattern Figure 12. Recommended balun land pattern Note: (*)Clearance 250 µm is needed to ensure good sensitivity. (**)1000 µm length between S2-LP & balun (between center QFN pads to center IPD pads). Figure 13. PCB stack-up recommendations DS12249 - Rev 2 page 8/13 BALF-SPI2-01D3 Stencil opening design 3.2 Stencil opening design Figure 14. Footprint - 3 mils stencil -non solder mask defined Copper pad diameter: 220 µm recommended 180 µm minimum 260 µm maximum Solder mask opening: 220 µm recommended 180 µm minimum 260 µm maximum Solder mask opening: 320 µm recommended 300 µm minimum 340 µm maximum Copper pad diameter: 320 µm recommended 300 µm minimum Solder stencil opening: 220 µm recommended Solder stencil opening: 220 µm recommended Figure 16. Footprint - 5 mils stencil -non solder mask defined Solder mask opening: 220 µm recommended 180 µm minimum 260 µm maximum Solder mask opening: 320 µm recommended 300 µm minimum 340 µm maximum Copper pad diameter: 320 µm recommended 300 µm minimum Solder stencil opening: 330 µm recommended* Solder stencil opening: 330 µm recommended* Halide-free flux qualification ROL0 according to ANSI/J-STD-004. “No clean” solder paste is recommended. Offers a high tack force to resist component movement during high speed. Use solder paste with fine particles: powder particle size 20-38 µm. Placement 1. 2. 3. 4. 5. 6. DS12249 - Rev 2 *depending on paste, it can go down to 270 µm Solder paste 1. 2. 3. 4. 3.4 Figure 17. Footprint - 5 mils stencil - solder mask defined Copper pad diameter: 220 µm recommended 180 µm minimum 260 µm maximum *depending on paste, it can go down to 270 µm 3.3 Figure 15. Footprint - 3 mils stencil - solder mask defined Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering Standard tolerance of ±0.05 mm is recommended. 1.0 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. page 9/13 BALF-SPI2-01D3 PCB design preference 3.5 PCB design preference 1. 2. 3.6 To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. A symmetrical layout is recommended, to avoid any tilt phenomena caused by asymmetrical solder paste due to solder flow away. Reflow profile Figure 18. ST ECOPACK® recommended soldering reflow profile for PCB mounting 250 240-245 °C Temperature (°C) -2 °C/s 2 - 3 °C/s 60 sec (90 max) 200 -3 °C/s 150 -6 °C/s 100 0.9 °C/s 50 Time (s) 0 Note: DS12249 - Rev 2 30 60 90 120 150 180 210 240 270 300 Minimize air convection currents in the reflow oven to avoid component movement. page 10/13 BALF-SPI2-01D3 Ordering information 4 Ordering information Table 5. Ordering information DS12249 - Rev 2 Order code Marking Package Weight Base qty. Delivery mode BALF-SPI2-01D3 TM Flip-Chip 6 bumps 3.4 mg 5000 Tape and reel page 11/13 BALF-SPI2-01D3 Revision history Table 6. Document revision history Date Revision 08-Aug-2017 1 Initial release. 2 Updated Section 1.1 RF measurements (Rx balun), Section 1.2 RF measurements (Tx filter) and Section 1.3 ST S2-LP evaluation board with BALF-SPI2-01D3. Updated Section 1 Characteristics. Updated Figure 9. Flip-Chip 6 bumps package outline (bottom and side view), Figure 12. Recommended balun land pattern and Figure 13. PCB stack-up recommendations. 23-Feb-2018 DS12249 - Rev 2 Changes page 12/13 BALF-SPI2-01D3 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS12249 - Rev 2 page 13/13
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