BLUENRGCSP

BlueNRG Upgradable Bluetooth® Low Energy network processor Datasheet - production data x x x x x x x x x x x Features x x x x x x x x x x x x Bluetooth specification v4.0 compliant, slave single-mode Bluetooth low energy network processor Embedded Bluetooth low energy protocol stack: GAP, GATT, SM, L2CAP, LL, RFPHY Bluetooth low energy profiles provided separately Operating supply voltage: from 2.0 to 3.6 V 8.2 mA maximum TX current (@0 dBm, 3.0 V) Down to 1.7 μA current consumption with active BLE stack Integrated linear regulator and DC-DC stepdown converter Up to +8 dBm available output power (at antenna connector) Excellent RF link budget (up to 96 dB) Accurate RSSI to allow power control Proprietary application controller interface (ACI), SPI based, allows interfacing with an external host application microcontroller Full link controller and host security January 2016 High performance, ultra-low power CortexM0 32-bit based architecture core Upgradable BLE stack (stored in embedded Flash memory, via SPI) AES security co-processor Low power modes 16 or 32 MHz crystal oscillator 12 MHz ring oscillator 32 kHz crystal oscillator 32 kHz ring oscillator Compliant with the following radio frequency regulations: ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15, ARIB STD-T66 Available in QFN32 (5 x 5 mm) and WLCSP34 (2.66 x 2.56 mm) packages Operating temperature range: -40 °C to 85 °C Applications x x x x x x x x x Watches Fitness, wellness and sports Consumer medical Security/proximity Remote control Home and industrial automation Assisted living Mobile phone peripherals PC peripherals Table 1: Device summary Order code Package Packing BLUENRGQTR QFN32 (5 x 5 mm) Tape and reel BLUENRGCSP WLCSP34 (2.66 x 2.56 mm) Tape and reel DocID025108 Rev 10 This is information on a product in full production. 1/44 www.st.com Contents BlueNRG Contents 1 Description....................................................................................... 5 2 General description......................................................................... 6 3 Pin description ................................................................................ 8 4 5 Application circuits ....................................................................... 11 Block diagram and descriptions .................................................. 15 5.1 Core, memory and peripherals........................................................ 15 5.2 Power management ........................................................................ 16 5.3 Clock management ......................................................................... 17 5.4 Bluetooth low energy radio.............................................................. 17 6 Operating modes ........................................................................... 19 7 Application controller interface.................................................... 22 8 9 Absolute maximum ratings and thermal data ............................. 23 General characteristics................................................................. 24 10 Electrical specification.................................................................. 25 10.1 Electrical characteristics.................................................................. 25 10.2 RF general characteristics .............................................................. 27 10.3 RF transmitter characteristics.......................................................... 28 10.4 RF receiver characteristics.............................................................. 29 10.5 High speed crystal oscillator (HSXOSC) characteristics ................. 30 10.5.1 11 High speed crystal oscillator (HSXOSC) .......................................... 31 10.6 Low speed crystal oscillator (LSXOSC) characteristics................... 32 10.7 High speed ring oscillator (HSROSC) characteristics ..................... 32 10.8 Low speed ring oscillator (LSROSC) characteristics....................... 32 10.9 N-fractional frequency synthesizer characteristics .......................... 33 10.10 SPI characteristics .......................................................................... 33 Package information ..................................................................... 35 11.1 QFN32 package information ........................................................... 36 11.2 WLCSP34 package information ...................................................... 38 12 PCB assembly guidelines ............................................................. 40 13 Revision history ............................................................................ 42 2/44 DocID025108 Rev 10 BlueNRG List of tables List of tables Table 1: Device summary ........................................................................................................................... 1 Table 2: Pinout description ......................................................................................................................... 9 Table 3: External component list ..............................................................................................................13 Table 4: SPI interface ...............................................................................................................................15 Table 5: Operating modes ........................................................................................................................20 Table 6: Transition times...........................................................................................................................21 Table 7: Absolute maximum ratings .........................................................................................................23 Table 8: Thermal data...............................................................................................................................23 Table 9: Recommended operating conditions ..........................................................................................24 Table 10: Electrical characteristics ...........................................................................................................25 Table 11: RF general characteristics ........................................................................................................27 Table 12: RF Transmitter characteristics..................................................................................................28 Table 13: RF receiver characteristics .......................................................................................................29 Table 14: High speed crystal oscillator characteristics.............................................................................30 Table 15: Low speed crystal oscillator characteristics..............................................................................32 Table 16: High speed ring oscillator characteristics .................................................................................32 Table 17: Low speed ring oscillator characteristics ..................................................................................32 Table 18: N-fractional frequency synthesizer characteristics ...................................................................33 Table 19: SPI characteristics ....................................................................................................................33 Table 20: QFN32 (5 x 5 x 1 pitch 0.5 mm) mechanical data ....................................................................37 Table 21: WLCSP34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) mechanical data..................................................39 Table 22: Flip Chip CSP (2.66 x 2.56 x 0.5 pitch 0.4 mm) package reflow profile recommendation .......40 Table 23: Document revision history ........................................................................................................42 DocID025108 Rev 10 3/44 List of figures BlueNRG List of figures Figure 1: BlueNRG application block diagram............................................................................................ 7 Figure 2: Pinout top view (QFN32) ............................................................................................................. 8 Figure 3: Pinout top view (WLCSP34) ........................................................................................................ 8 Figure 4: Pinout bottom view (WLCSP34) .................................................................................................. 9 Figure 5: BlueNRG application circuit: active DC-DC converter QFN32 package ...................................11 Figure 6: BlueNRG application circuit: non active DC-DC converter QFN32 package ............................12 Figure 7: BlueNRG application circuit: active DC-DC converter WLCSP package ..................................12 Figure 8: BlueNRG application circuit: non active DC-DC converter WLCSP package...........................13 Figure 9: Block diagram ............................................................................................................................15 Figure 10: Power management strategy using LDO ................................................................................16 Figure 11: Power management strategy using step-down DC-DC converter ..........................................17 Figure 12: Simplified state machine..........................................................................................................20 Figure 13: Simplified block diagram of the amplitude regulated oscillator ...............................................31 Figure 14: SPI timings...............................................................................................................................34 Figure 15: QFN32 (5 x 5 x 1 pitch 0.5 mm) package outline ....................................................................36 Figure 16: QFN32 (5 x 5 x 1 pitch 0.5 mm) package detail "A" ................................................................37 Figure 17: WLCSP34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) package outline..................................................38 Figure 18: Flip Chip CSP (2.66 x 2.56 x 0.5 pitch 0.4 mm) package reflow profile recommendation ......40 4/44 DocID025108 Rev 10 BlueNRG 1 Description Description The BlueNRG is a very low power Bluetooth Low Energy (BLE) single-mode network processor, compliant with Bluetooth specification v4.0. The BlueNRG can act as slave. The Bluetooth Low Energy stack runs on the embedded ARM Cortex-M0 core. The stack is stored on the on-chip non-volatile Flash memory and can be easily upgraded via SPI. The device comes pre-programmed with a production-ready stack image (whose version could change at any time without notice). A different or more up-to-date stack image can be downloaded from the ST web site and programmed on the device through the ST provided software tools. The BlueNRG allows applications to meet the tight advisable peak current requirements imposed by the use of standard coin cell batteries. The maximum peak current is only 10 mA at 1 dBm of output power. Ultra low-power sleep modes and very short transition times between operating modes allow very low average current consumption, resulting in longer battery life. The BlueNRG offers the option of interfacing with external microcontrollers using SPI transport layer. DocID025108 Rev 10 5/44 General description 2 BlueNRG General description The BlueNRG is a single-mode Bluetooth low energy slave network processor, compliant with the Bluetooth specification v4.0. It integrates a 2.4 GHz RF transceiver and a powerful Cortex-M0 microcontroller, on which a complete power-optimized stack for Bluetooth single mode protocol runs, providing: x x x x x x Slave role support GAP: peripheral, broadcaster roles ATT/GATT: client and server SM: privacy, authentication and authorization L2CAP Link Layer: AES-128 encryption and decryption An on-chip non-volatile Flash memory allows on-field Bluetooth low energy stack upgrade. The device allows applications to meet the tight advisable peak current requirements imposed by the use of standard coin cell batteries. If the high efficiency embedded DC-DC step-down converter is used, the maximum input current is only 15 mA at the highest output power (+8 dBm). Even if the DC-DC converter is not used, the maximum input current is only 29 mA at the highest output power, still preserving battery life. Ultra low-power sleep modes and very short transition time between operating modes result in very low average current consumption during real operating conditions, providing very long battery life. Two different external matching networks are suggested: standard mode (TX output power up to +5 dBm) and high power mode (TX output power up to +8 dBm). The external host application processor, where the application resides, is interfaced with the BlueNRG through an application controller interface protocol based on a standard SPI interface. 6/44 DocID025108 Rev 10 BlueNRG General description Figure 1: BlueNRG application block diagram Application processor Application Bluetooth Low Energy Profiles BlueNRG Application Controller Interface SPI Application Controller Interface Bluetooth Low Energy Stack 2.4GHz Radio GAMS20150507EC-1213 DocID025108 Rev 10 7/44 Pin description 3 BlueNRG Pin description The device pinout is shown in Figure 2: "Pinout top view (QFN32)", Figure 3: "Pinout top view (WLCSP34)" and Figure 4: "Pinout bottom view (WLCSP34)". In Table 2: "Pinout description" a short description of the pins is provided. Figure 2: Pinout top view (QFN32) Figure 3: Pinout top view (WLCSP34) Note: Top view (balls are underneath). 8/44 DocID025108 Rev 10 BlueNRG Pin description Figure 4: Pinout bottom view (WLCSP34) Table 2: Pinout description Pins Name I/O Description E2 SPI_MOSI I SPI_MOSI 2 E1 SPI_CLK I SPI_CLK 3 D2 SPI_IRQ O SPI_IRQ 4 D1 TEST1 I/O Test pin 5 C1 VBAT3 VDD 2.0-3.6 battery voltage input 6 C2 TEST2 I/O Test pin connected to GND 7 B1 TEST3 I/O Test pin connected to GND 8 B2 TEST4 I/O Test pin connected to GND 9 A1 TEST5 I/O Test pin connected to GND 10 B3 TEST6 I/O Test pin connected to GND QFN32 WLCSP 1 11 A2 TEST7 I/O Test pin connected to GND 12 A3 VDD1V8 O 1.8 V digital core 13 A4 TEST8 I/O Test pin not connected 14 A5 TEST9 I/O Test pin not connected 15 B4 TEST11 I/O Test pin not connected (QFN32) Test pin connected to GND (WLCSP) 16 B5 TEST12 I/O Test pin not connected (QFN32) Test pin connected to GND (WLCSP) 17 A6 FXTAL1 I 16/32 MHz crystal 18 B6 FXTAL0 I 16/32 MHz crystal 19 - VBAT2 VDD 2.0-3.6 battery voltage input 20 C6 RF1 I/O Antenna + matching circuit 21 D6 RF0 I/O Antenna + matching circuit 22 E6 SXTAL1 I 32 kHz crystal 23 E5 SXTAL0 I 32 kHz crystal 24 D5 VBAT1 VDD 2.0-3.6 battery voltage input 25 E4 RESETN I Reset DocID025108 Rev 10 9/44 Pin description BlueNRG Pins 10/44 Name I/O F6 SMPSFILT1 O SMPS output - NO_SMPS I Power management strategy selection 28 F5 SMPSFILT2 I/O SMPS input/output 29 F3 VDD1V2 O 1.2 V digital core 30 E3 TEST10 I/O TEST pin connected to GND 31 F2 SPI_CS I SPI_CS 32 F1 SPI_MISO O SPI_MISO - C3 GND GND Ground - D3 GND GND Ground - D4 GND GND Ground - F4 SMPS-GND GND SMPS ground QFN32 WLCSP 26 27 DocID025108 Rev 10 Description BlueNRG 4 Application circuits Application circuits The schematics below are purely indicative. For more detailed schematics, please refer to the "Reference design" and "Layout guidelines" which are provided as separate documents. Figure 5: BlueNRG application circuit: active DC-DC converter QFN32 package DocID025108 Rev 10 11/44 Application circuits BlueNRG Figure 6: BlueNRG application circuit: non active DC-DC converter QFN32 package Figure 7: BlueNRG application circuit: active DC-DC converter WLCSP package 12/44 DocID025108 Rev 10 BlueNRG Application circuits Figure 8: BlueNRG application circuit: non active DC-DC converter WLCSP package Table 3: External component list Component Description C1 Decoupling capacitor C2 DC-DC converter output capacitor C3 DC-DC converter output capacitor C4 Decoupling capacitor for 1.2 V digital regulator C5 Decoupling capacitor for 1.2 V digital regulator C6 Decoupling capacitor C7 32 kHz crystal loading capacitor (1) C8 32 kHz crystal loading capacitor (1) C9 RF balun/matching network capacitor High Performance RF balun/matching network capacitor Standard mode C10 RF balun/matching network capacitor High Performance RF balun/matching network capacitor Standard mode C11 RF balun/matching network capacitor High Performance RF balun/matching network capacitor Standard mode C12 Decoupling capacitor C13 Decoupling capacitor C14 RF balun/matching network capacitor High Performance RF balun/matching network capacitor Standard mode C15 RF balun/matching network capacitor High Performance RF balun/matching network capacitor Standard mode C16 RF balun/matching network capacitor High Performance RF balun/matching network capacitor Standard mode DocID025108 Rev 10 13/44 Application circuits BlueNRG Component Description C17 16/32 MHz crystal loading capacitor C18 16/32 MHz crystal loading capacitor C19 Decoupling capacitor for 1.8 V digital regulator C20 Decoupling capacitor for 1.8 V digital regulator C21 RF balun/matching network capacitor High Performance, RF balun/matching network capacitor Standard mode L1 DC-DC converter input inductor, Isat > 100 mA, Q > 25 L2 RF balun/matching network inductor High Performance RF balun/matching network inductor Standard mode L3 RF balun/matching network inductor High Performance RF balun/matching network inductor Standard mode L4 RF balun/matching network inductor High Performance RF balun/matching network inductor Standard mode R1 Pull-down resistor on the SPI_IRQ line (can be replaced by the internal pull-down of the Application MCU) XTAL1 32 kHz crystal (optional) XTAL2 16/32 MHz crystal Notes: (1)Values valid only for the crystal NDK NX3215SA-32.768 kHz-EXS00A-MU00003. For other crystals refer to what specified in their datasheet. 14/44 DocID025108 Rev 10 BlueNRG 5 Block diagram and descriptions Block diagram and descriptions A block diagram of the device is shown in Figure 9: "Block diagram". In the following subsections a short description of each module is given. Figure 9: Block diagram 5.1 Core, memory and peripherals The device contains an ARM Cortex-M0 microcontroller core that supports ultra-low leakage state retention mode and almost instantaneously returning to fully active mode on critical events. The memory subsystem consists of 64 KB Flash, and 12 KB RAM , divided in two blocks of 6 KB (RAM1 and RAM2). Flash is used for the M0 program. No RAM or FLASH resources are available to the external microcontroller driving the BlueNRG. The application controller interface (ACI) uses a standard SPI slave interface as transport layer, basing in five physical wires: x x x 2 control wires (clock and slave select) 2 data wires with serial shift-out (MOSI and MISO) in full duplex 1 wire to indicate data availability from the slave Table 4: SPI interface Name Direction Width Description SPI_CS In 1 SPI slave select = SPI enable. SPI_CLK In 1 SPI clock (max 8 MHz). SPI_MOSI In 1 Master output, slave input. SPI_MISO Out 1 Master input, slave output. DocID025108 Rev 10 15/44 Block diagram and descriptions Name SPI_IRQ BlueNRG Direction Width Out 1 Description Slave has data for master. All the SPI pins have an internal pull-down except for the CSN that has a pull-up. All the SPI pins, except the CSN, are in high impedance state during the low-power states. The IRQ pin needs a pull-down external resistor. 5.2 Power management The device integrates both a low dropout voltage regulator (LDO) and a step-down DC-DC converter, and one of them can be used to power the internal circuitry. However even when the LDO is used, the stringent maximum current requirements, which are advisable when coin cell batteries are used, can be met and further improvements can be obtained with the DC-DC converter at the sole additional cost of an inductor and a capacitor. The internal LDOs supplying both the 1.8 V digital blocks and 1.2 V digital blocks require decoupling capacitors for stable operation. Figure 10: "Power management strategy using LDO" and Figure 11: "Power management strategy using step-down DC-DC converter", show the simplified power management schemes using LDO and DC-DC converter. Figure 10: Power management strategy using LDO 16/44 DocID025108 Rev 10 BlueNRG Block diagram and descriptions Figure 11: Power management strategy using step-down DC-DC converter 5.3 Clock management The device integrates two low-speed frequency oscillators (LSOSC) and two High speed (16 MHz or 32 MHz) frequency oscillators (HSOSC). The low frequency clock is used in Low Power mode and can be supplied either by a 32.7 kHz oscillator that uses an external crystal and guarantee up to ±50 ppm frequency tolerance, or by a ring oscillator with maximum ±500 ppm frequency tolerance, which does not require any external components. The primary high frequency clock is a 16 MHz or 32 MHz crystal oscillator. There is also a fast-starting 12 MHz ring oscillator that provides the clock while the crystal oscillator is starting up. Frequency tolerance of high speed crystal oscillator is ±50 ppm. The usage of the 16 MHz (or 32 MHz) crystal is strictly necessary. 5.4 Bluetooth low energy radio The device integrates an RF transceiver compliant with the Bluetooth specification and the standard national regulations in the unlicensed 2.4 GHz ISM band. The RF transceiver requires very few external discrete components. It provides 96 dB link budgets with excellent link reliability, keeping the maximum peak current below 15 mA. In Transmit mode, the power amplifier (PA) drives the signal generated by the frequency synthesizer out to the antenna terminal through a very simple external network. The power delivered as well as the harmonic content depends on the external impedance seen by the PA. DocID025108 Rev 10 17/44 Block diagram and descriptions BlueNRG The output power is programmable from -18 dBm to +8 dBm, to allow a user-defined power control system and to guarantee optimum power consumption for each scenario. 18/44 DocID025108 Rev 10 BlueNRG 6 Operating modes Operating modes Several operating modes are defined for the BlueNRG: x x x x x Reset mode Sleep mode Standby mode Active mode Radio mode  Receive Radio mode  Transmit Radio mode In Reset mode, the device is in ultra-low power consumption: all voltage regulators, clocks and the RF interface are not powered. The device enters Reset mode by asserting the external reset signal. As soon as it is de-asserted, the device follows the normal activation sequence to transit to Active mode. In Sleep mode either the low speed crystal oscillator or the low speed ring oscillator are running, whereas the high speed oscillators are powered down as well as the RF interface. The state of the device is retained and the content of the RAM is preserved. Depending on the application, part of the RAM (RAM2 block) can be switched off during sleep to save more power (refer to stack mode 1, described in UM1868). While in Sleep mode, the device waits until an internal timer expires and then it goes into Active mode. The transition from Sleep mode to Active mode can also be activated through the SPI interface. Standby mode and Sleep mode are equivalent but the low speed frequency oscillators are powered down. In Standby mode the device can be activated through the SPI interface. In Active mode the device is fully operational: all interfaces, including SPI and RF, are active as well as all internal power supplies together with the high speed frequency oscillator. The MCU core is also running. Radio mode differs from Active mode as also the RF transceiver is active and it is capable of either transmitting or receiving. Figure 12: "Simplified state machine" reports the simplified state machine: DocID025108 Rev 10 19/44 Operating modes BlueNRG Figure 12: Simplified state machine Table 5: Operating modes State Digital LDO SPI LSOSC HSOSC Core RF synt. RX chain TX chain OFF OFF OFF OFF OFF OFF OFF ON OFF OFF OFF OFF OFF OFF ON ON OFF OFF OFF OFF OFF ON - ON ON OFF OFF OFF ON - ON ON ON ON OFF ON - ON ON ON OFF ON OFF Reset Register contents lost ON Standby Register contents retained ON Sleep Register contents retained ON Active Register contents retained ON RX Register contents retained ON TX 20/44 Register contents retained DocID025108 Rev 10 BlueNRG Operating modes Table 6: Transition times Transition Maximum time 1.5 ms Reset-active (1) Standby-active Sleep-active (1) Active-RX Active-TX RX-TX or TX-RX 32 kHz not available 7 ms 32 kHz RO 94 ms 32 kHz XO 0.42 ms (1) Condition 32 kHz not available 6.2 ms 32 kHz RO 93 ms 32 kHz XO 0.42 ms 125 μs Channel change 61 μs No channel change 131 μs Channel change 67 μs No channel change 150 μs Notes: (1) These measurements are taken using NX3225SA-16.000 MHz-EXS00A-CS05997. DocID025108 Rev 10 21/44 Application controller interface 7 BlueNRG Application controller interface The application controller interface (ACI) is based on a standard SPI module with speeds up to 8 MHz. The ACI defines a protocol providing access to all the services offered by the layers of the embedded Bluetooth stack. The ACI commands are described in the associated document on ACI command interface (UM1755). In addition, the ACI provides a set of commands that allow to program BlueNRG firmware from an external device connected to SPI. The complete description of updater commands and procedures is provided in a separate application note (AN4491). 22/44 DocID025108 Rev 10 BlueNRG 8 Absolute maximum ratings and thermal data Absolute maximum ratings and thermal data Absolute maximum ratings are those values above which damage to the device may occur. Functional operation under these conditions is not implied. All voltages are referred to GND. Table 7: Absolute maximum ratings Pin Parameter Value Unit 5, 19, 24, 26, 28 DC-DC converter supply voltage input and output -0.3 to +3.9 V 12, 29 DC voltage on linear voltage regulator -0.3 to +3.9 V 1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 25, 27, 30, 31, 32 DC voltage on digital input/output pins -0.3 to +3.9 V 13, 14, 15,16 DC voltage on analog pins -0.3 to +3.9 V 17, 18, 22, 23 DC voltage on XTAL pins -0.3 to +1.4 V DC voltage on RF pins -0.3 to +1.4 V Storage temperature range -40 to +125 °C ±2.0 kV 20, 21 (1) TSTG VESD-HBM Electrostatic discharge voltage Notes: (1)+8 dBm input power at antenna connector in Standard mode, +11 dBm in High Power mode, with given reference design. Table 8: Thermal data Symbol Rthj-amb Rthj-c Parameter Thermal resistance junction-ambient Thermal resistance junction-case DocID025108 Rev 10 Value 34 (QFN32) 50 (WLCSP36) 2.5 (QFN32) 25 (WLCSP36) Unit °C/W °C/W 23/44 General characteristics 9 BlueNRG General characteristics Table 9: Recommended operating conditions Symbol VBAT TA 24/44 Parameter Min. Typ. Max. Unit Operating Battery supply voltage 2.0 3.6 V Operating Ambient temperature range -40 +85 °C DocID025108 Rev 10 BlueNRG Electrical specification 10 Electrical specification 10.1 Electrical characteristics Characteristics measured over recommended operating conditions unless otherwise specified. Typical value are referred to TA = 25 °C, VBAT = 3.0 V. All performance data are referred to a 50 W antenna connector, via reference design, QFN32 package version. Table 10: Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit Power consumption when DC-DC converter active Reset Standby Sleep Active IBAT Supply current RX TX Standard mode TX High Power mode DocID025108 Rev 10 5 RAM2 OFF 1.3 RAM2 ON 2 32 kHz XO ON (RAM2 OFF) 1.7 32 kHz XO ON (RAM2 ON) 2.4 32 kHz RO ON (RAM2 OFF) 2.8 32 kHz RO ON (RAM2 ON) 3.5 CPU, Flash and RAM off 2 CPU, Flash and RAM on 3.3 High Power mode 7.7 Standard mode 7.3 +5 dBm 11 0 dBm 8.2 -2 dBm 7.2 -6 dBm 6.7 -9 dBm 6.3 -12 dBm 6.1 -15 dBm 5.9 nA μA μA mA -18 dBm 5.8 +8 dBm 15.1 +4 dBm 10.9 +2 dBm 9 -2 dBm 8.3 -5 dBm 7.7 mA mA mA 25/44 Electrical specification Symbol BlueNRG Parameter Test conditions Min. Typ. -8 dBm 7.1 -11 dBm 6.8 -14 dBm 6.6 Max. Unit Power consumption when DC-DC converter not active 5 Reset Standby Sleep RAM2 ON IBAT Supply current TX Standard mode TX High Power mode μA 2 32 kHz XO ON (RAM2 OFF) 1.7 32kHz XO ON (RAM2 ON) 2.4 32 kHz RO ON (RAM2 OFF) 2.8 32 kHz RO ON (RAM2 ON) 3.5 μA Active CPU, Flash and RAM off RX nA 1.4 RAM2 OFF 2.3 High Power mode 14.5 Standard mode 14.3 +5 dBm 21 0 dBm 15.4 -2 dBm 13.3 -6 dBm 12.2 -9 dB 11.5 -12 dBm 11 -15 dBm 10.6 -18 dBm 10.4 +8 dBm 28.8 +4 dBm 20.5 +2 dBm 17.2 -2 dBm 15.3 -5 dBm 14 -8 dBm 13 -11 dBm 12.3 -14 dBm mA mA mA mA 12 Digital I/O CIN 26/44 Port I/O capacitance 1.29 DocID025108 Rev 10 1.38 1.67 pF BlueNRG Electrical specification Symbol Test conditions Min. Typ. Max. Unit TRISE Rise time 0.1*VDD to 0.9*VDD, CL = 50 pF 5 19 ns TFALL Fall time 0.9*VDD to 0.1*VDD, CL = 50 pF 6 22 ns T(RST) 10.2 Parameter Hold time for reset 1.5 ms TC VBAT range 3.0 3.3 3.6 V TC1 VBAT range 2.25 2.5 2.75 V VIL Input low voltage VIH Input high voltage VOL Output low voltage VOH Output high voltage IOL IOH VBAT range: TC -0.3 0.8 VBAT range: TC1 -0.3 0.7 VBAT range: TC 2.0 3.6 VBAT range: TC1 1.7 3.6 VBAT range: TC 0.4 VBAT range: TC1 0.7 VBAT range: TC 2.4 VBAT range: TC1 1.7 Low level output current @ VOL (max.) VBAT range: TC 3.4 5.6 7.9 VBAT range: TC1 3.8 6.6 10.1 High level output current @ VOH (min) VBAT range: TC 5.5 10.6 17.6 VBAT range: TC1 3.7 7.2 12.0 V V V V mA mA RF general characteristics Characteristics measured over recommended operating conditions unless otherwise specified. Typical value are referred to TA = 25 °C, VBAT =3.0 V. All performance data are referred to a 50 W antenna connector, via reference design, QFN32 package version. Table 11: RF general characteristics Symbol Parameter FREQ Frequency range FCH Channel spacing RFch RF channel center frequency Test conditions Min. Typ. 2400 Max. Unit 2483.5 MHz 2 DocID025108 Rev 10 2402 MHz 2480 MHz 27/44 Electrical specification 10.3 BlueNRG RF transmitter characteristics Characteristics measured over recommended operating conditions unless otherwise specified. Typical value are referred to TA = 25 °C, VBAT = 3.0 V. All performance data are referred to a 50 W antenna connector, via reference design, QFN32 package version. Table 12: RF Transmitter characteristics Symbol Test conditions MOD Modulation scheme BT Bandwidth-bit period product Mindex Min. Typ. Max. Unit GFSK 0.5 Modulation index 0.45 0.5 0.55 DR Air data rate STacc Symbol time accuracy PMAX Maximum output power at antenna connector PRFC Minimum output power PRFC RF power accuracy PBW1M 6 dB bandwidth for modulated carrier (1 Mbps) Using resolution bandwidth of 100 kHz PRF1 1st adjacent channel transmit power 2 MHz Using resolution bandwidth of 100 kHz and average detector -20 dBm PRF2 2nd adjacent channel transmit power >3 MHz Using resolution bandwidth of 100 kHz and average detector -30 dBm PSPUR Spurious emission Harmonics included. Using resolution bandwidth of 1 MHz and average detector -41 dBm CFdev Center frequency deviation During the packet and including both initial frequency offset and drift ±150 kHz Freqdrift Frequency drift During the packet ±50 kHz IFreqdrift Initial carrier frequency drift ±20 kHz Maximum drift rate 400 Hz/μs DriftRatemax ZLOAD 28/44 Parameter 1 Optimum differential load Mbps 50 ppm High power +8 +10 dBm Standard mode +5 +7 dBm High power -15 Standard mode -18 dB ±2 500 kHz Standard mode @ 2440 MHz 25.9 + j44.4 High power mode @ 2440 MHz 25.4 + j20.8 DocID025108 Rev 10 dB Ÿ BlueNRG 10.4 Electrical specification RF receiver characteristics Characteristics measured over recommended operating conditions unless otherwise specified. Typical value are referred to TA = 25 °C, VBAT =3.0 V. All performance data are referred to a 50 W antenna connector, via reference design, QFN32 package version. Table 13: RF receiver characteristics Symbol Parameter Test conditions RXSENS Sensitivity BER