CRX14
ISO14443 type-B contactless coupler chip
with anti-collision, CRC management and anti-clone function
Features
■
Single 5 V ±500 mV supply voltage
■
SO16N package
■
Contactless communication
– ISO14443 type-B protocol
– 13.56MHz carrier frequency using an
external oscillator
– 106 Kbit/s data rate
– 36-byte input/output frame register
– Supports frame answer with/without
SOF/EOF
– CRC generation and check
– France Telecom proprietary anti-clone
function
– Automated ST anti-collision exchange
■
16
1
SO16 (MQ)
150 mils width
I²C communication
– Two-wire I²C serial interface
– Supports 400 kHz protocol
– 3 chip enable pins
– Up to 8 CRX14 connected on the same bus
April 2010
Doc ID 8880 Rev 4
1/47
www.st.com
1
Contents
CRX14
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
4
5
2/47
2.1
Oscillator (OSC1, OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
Antenna output driver (RFOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Antenna input filter (RFIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Transmitter reference voltage (VREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5
Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6
Serial data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7
Chip enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8
Power supply (VCC, GND, GND_RF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CRX14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Parameter register (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Input/output frame register (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3
Authenticate register (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4
Slot marker register (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CRX14 I²C protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
I²C start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2
I²C stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3
I²C acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4
I²C data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5
I²C memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6
CRX14 I²C write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7
CRX14 I²C read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Applying the I²C protocol to the CRX14 registers . . . . . . . . . . . . . . . . 22
5.1
I²C parameter register protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2
I²C input/output frame register protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3
I²C authenticate register protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.4
I²C slot marker register protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Doc ID 8880 Rev 4
CRX14
Contents
5.5
6
7
Addresses above location 06h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CRX14 ISO14443 type-B radio frequency data transfer . . . . . . . . . . . . 26
6.1
Output RF data transfer from the CRX14 to the PICC (request frame) . . 26
6.2
Transmission format of request frame characters . . . . . . . . . . . . . . . . . . 26
6.3
Request start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4
Request end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.5
Input RF data transfer from the PICC to the CRX14 (answer frame) . . . . 28
6.6
Transmission format of answer frame characters . . . . . . . . . . . . . . . . . . . 28
6.7
Answer start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.8
Answer end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.9
Transmission frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.10
CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Tag access using the CRX14 coupler . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1
Standard TAG command access description . . . . . . . . . . . . . . . . . . . . . . 31
7.2
Anti-collision TAG sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Appendix A ISO14443 type B CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Doc ID 8880 Rev 4
3/47
List of tables
CRX14
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
4/47
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CRX14 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Parameter register bits description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input/output frame register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Slot marker register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CRX14 request frame character format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
I²C AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
I²C input parameters(1,2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
I²C DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
I²C AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
RFOUT AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
RFIN AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
SO16 narrow - 16 lead plastic small outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Doc ID 8880 Rev 4
CRX14
List of figures
List of figures
Figure 1.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2.
Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3.
SO pin connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4.
CRX14 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5.
Maximum RL value versus bus capacitance (CBUS) for an I²C bus . . . . . . . . . . . . . . . . . . 11
Figure 6.
I²C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7.
CRX14 I²C write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8.
I²C polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9.
CRX14 I²C read modes sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Host-to-CRX14 transfer: I²C write to parameter register . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. CRX14-to-host transfer: I²C random address read from parameter register . . . . . . . . . . . 22
Figure 12. CRX14-to-host transfer: I²C current address read from parameter register . . . . . . . . . . . 22
Figure 13. Host-to-CRX14 transfer: I²C write to I/O frame register for ISO14443B . . . . . . . . . . . . . . 23
Figure 14. CRX14-to-host transfer: I²C random address read from I/O frame register for
ISO14443B 23
Figure 15. CRX14-to-host transfer: I²C current address read from I/O frame register
for ISO14443B 24
Figure 16. Host-to-CRX14 transfer: I²C write to slot marker register . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17. CRX14-to-host transfer: I²C random address read from slot marker register . . . . . . . . . . 25
Figure 18. CRX14-to-host transfer: I²C current address read from slot marker register . . . . . . . . . . . 25
Figure 19. Wave transmitted using ASK modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 20. CRX14 request frame character format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 21. Request start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 22. Request end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 23. Wave received using BPSK sub-carrier modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 24. Answer start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 25. Answer end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 26. Example of a complete transmission frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 27. CRC transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 28. Standard TAG command: request frame transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 29. Standard TAG command: answer frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 30. Standard TAG command: complete TAG access description. . . . . . . . . . . . . . . . . . . . . . . 32
Figure 31. Anti-collision ST short range memory sequence (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 32. Anti-collision ST short range memory sequence continued . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 33. I²C AC testing I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 34. I²C AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 35. CRX14 synchronous timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 36. SO16 narrow - 16 lead plastic small outline, 150 mils body width, package outline. . . . . . 42
Doc ID 8880 Rev 4
5/47
Summary description
1
CRX14
Summary description
The CRX14 is a contactless coupler that is compliant with the short range ISO14443 type-B
standard. It is controlled using the two wire I²C bus.
The CRX14 generates a 13.56 MHz signal on an external antenna. Transmitted data are
modulated using Amplitude Shift Keying (ASK). Received data are demodulated from the
PICC (Proximity integrated Coupling Card) load variation signal, induced on the antenna,
using Bit Phase Shift Keying (BPSK) of a 847kHz sub-carrier. The Transmitted ASK wave is
10% modulated. The Data transfer rate between the CRX14 and the PICC is 106 Kbit/s in
both transmission and reception modes.
The CRX14 follows the ISO14443 type-B recommendation for Radio frequency power and
signal interface.
The CRX14 is specifically designed for short range applications that need disposable or
secure and reusable, products.
The CRX14 includes an automated anti-collision mechanism that allows it to detect and
select any ST short range memories that are present at the same time within its range. The
anti-collision mechanism is based on the STMicroelectronics probabilistic scanning method.
The CRX14 provides an anti-clone function, from FRANCE TELECOM, which allows the
authentication of the ST short range memories. Using the CRX14 single chip coupler,
therefore, it is easy to design a reader, with authentication capability and to build an end
application with a high level of security at low cost.
The CRX14 provides a complete analog interface, compliant with the ISO14443 type-B
recommendations for Radio-Frequency power and signal interfacing. With it, any ISO14443
type-B PICC products can be powered and have their data transmission controlled via a
simple antenna.
The CRX14 is fabricated in STMicroelectronics High Endurance Single Poly-silicon CMOS
technology.
The CRX14 is organized as 4 different blocks (see Figure 2):
●
The I²C bus controller. It handles the serial connection with the application host. It is
compliant with the 400kHz I²C bus specification, and controls the read/write access to
all the CRX14 registers.
●
The RAM buffer. It is bi-directional. . It stores all the request frame Bytes to be
transmitted to the PICC, and all the received Bytes sent by the PICC on the answer
frame.
●
The transmitter. It powers the PICCs by generating a 13.56MHz signal on an external
antenna. The resulting field is 10% modulated using ASK (amplitude shift keying) for
outgoing data.
●
The receiver. It demodulates the signal generated on the antenna by the load variation
of the PICC. The resulting signal is decoded by a 847kHz BPSK (binary phase shift
keying) sub-carrier decoder.
The CRX14 is designed to be connected to a digital host (Microcontroller or ASIC). This
host has to manage the entire communication protocol in both transmit and receive modes,
through the I²C serial bus.
6/47
Doc ID 8880 Rev 4
CRX14
Summary description
Figure 1.
Logic diagram
VCC
VREF
RFOUT
OSC1
OSC2
SCL
SDA
E0
E1
E2
CRX14
Antenna
RFIN
GND
GND_RF
AI06828B
Table 1.
Signal names
Signal
Description
RFOUT
Antenna Output Driver
RFIN
Antenna Input Filter
OSC1
Oscillator Input
OSC2
Oscillator Output
E0, E1, E2
Chip Enable Inputs
SDA
I²C Bi-Directional Data
SCL
I²C Clock
VCC
Power Supply
GND
Ground
VREF
Transmitter Reference Voltage
GND_RF
Ground for RF circuitry
Doc ID 8880 Rev 4
7/47
Summary description
Figure 2.
CRX14
Logic block diagram
VCC
VREF
CRX14
Transmitter
RFOUT
GND
OSC2
Antenna
Receiver
SCL
SDA
E0
E1
E2
RAM Buffer
I²C Bus Controller
OSC1
RFIN
GND_RF
AI10910
Figure 3.
SO pin connections
SO16
VREF
RFIN
E0
E1
E2
GND_RF
GND
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
RFOUT
GND_RF
OSC1
OSC2
GND
SCL
SDA
AI10911
8/47
Doc ID 8880 Rev 4
CRX14
2
Signal description
Signal description
See Figure 1: Logic diagram, and Table 1: Signal names, for an overview of the signals
connected to this device.
2.1
Oscillator (OSC1, OSC2)
The OSC1 and OSC2 pins are internally connected to the on-chip oscillator circuit. The
OSC1 pin is the input pin, the OSC2 is the output pin. For correct operation of the CRX14, it
is required to connect a 13.56MHz quartz crystal across OSC1 and OSC2. If an external
clock is used, it must be connected to OSC1 and OSC2 must be left open.
2.2
Antenna output driver (RFOUT)
The Antenna Output Driver pin, RFOUT, generates the modulated 13.56MHz signal on the
antenna. Care must be taken as it will not withstand a short-circuit.
RFOUT has to be connected to the antenna circuitry as shown in Figure 4: CRX14
application schematic The LRC antenna circuitry must be connected across the RFOUT pin
and GND.
2.3
Antenna input filter (RFIN)
The antenna input filter of the CRX14, RFIN, has to be connected to the external antenna
through an adapter circuit, as shown in Figure 4.
The input filter demodulates the signal generated on the antenna by the load variation of the
PICC. The resulting signal is then decoded by the 847kHz BPSK decoder.
2.4
Transmitter reference voltage (VREF)
The Transmitter Reference Voltage input, VREF, provides a reference voltage used by the
output driver for ASK modulation.
The Transmitter Reference Voltage input should be connected to an external capacitor, as
shown in Figure 4.
2.5
Serial clock (SCL)
The SCL input pin is used to strobe all I²C data in and out of the CRX14. In applications
where this line is used by slave devices to synchronize the bus to a slower clock, the master
must have an open drain output, and a pull-up resistor must be connected from the Serial
Clock (SCL) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be
calculated).
In most applications, though, this method of synchronization is not employed, and so the
pull-up resistor is not necessary, provided that the master has a push-pull (rather than open
drain) output.
Doc ID 8880 Rev 4
9/47
Signal description
2.6
CRX14
Serial data (SDA)
The SDA signal is bi-directional. It is used to transfer I²C data in and out of the CRX14. It is
an open drain output that may be wire-OR’ed with other open drain or open collector signals
on the bus. A pull-up resistor must be connected from Serial data (SDA) to VCC. (Figure 5
indicates how the value of the pull-up resistor can be calculated).
2.7
Chip enable (E0, E1, E2)
The Chip Enable inputs E0, E1, E2 are used to set and reset the value on the three least
significant bits (b3, b2, b1) of the 7-bit I²C Device Select Code. They are used for hardwired
addressing, allowing up to eight CRX14 devices to be addressed on the same I²C bus.
These inputs may be driven dynamically or tied to VCC or GND to establish the Device
Select Code (note that the VIL and VIH levels for the inputs are CMOS compatible, not TTL
compatible).
When left open, E0, E1 and E2 are internally read at the logic level 0 due to the internal pulldown resistors connected to each inputs.
2.8
Power supply (VCC, GND, GND_RF)
Power is supplied to the CRX14 using the VCC, GND and GND_RF pins.
VCC is the Power Supply pin that supplies the power (+5V) for all CRX14 operations.
The GND and GND_RF pins are ground connections. They must be connected together.
Decoupling capacitors should be connected between the VCC Supply Voltage pin, the GND
Ground pin and the GND_REF Ground pin to filter the power line, as shown in Figure 4.
Figure 4.
CRX14 application schematic
D1
1N4148 (OPTIONAL)
C6VCC
C8
100pF50V
VCC
100nF50V
OPT
OPT
R1
R3
E0
0R
WURTH 742-792-042U1
FL7
1
VREF
VCC
2
R5
RFIN RFOUT
22nF50V
3
E0
GND_RF
4
E1
OSC1
5
E2
OSC2
6
E2
GND_RF GND
7
0R
GND
SCL
8
GND
SDA
R6
CRX14
OPT C3
E1
0R
R2
R4
C1 7pF50V
16
15
14
13
12
11
10
9
X1
13.56MHz
C8'
8pF50V
C5
10pF50V R8
0R
ANT1
C7
C7'
120pF50V 33pF50V
C2 7pF50V
R7
ANT2
0R
J1
4
3
2
1
SDASCL
FL5 0R
FL4
0R
FL6
0R
VCC
+ C4
22uF 10V
AI10952
10/47
Doc ID 8880 Rev 4
CRX14
Signal description
Figure 5.
Maximum RL value versus bus capacitance (CBUS) for an I²C bus
VCC
Maximum RP value (kΩ)
20
16
RL
12
RL
SDA
MASTER
8
fc = 100kHz
4
fc = 400kHz
CBUS
SCL
CBUS
0
10
1000
100
CBUS (pF)
AI01665
Doc ID 8880 Rev 4
11/47
CRX14 registers
3
CRX14
CRX14 registers
The CRX14 chip coupler contains six volatile registers. It is entirely controlled, at both digital
and analog level, using the four registers listed below and shown in Table 2:
●
Parameter Register
●
Input/Output Frame Register
●
Authentication Register
●
Slot Marker Register
The other 3 registers are located at addresses 02h, 04h and 05h. They are “ST Reserved”,
and must not be used in end-user applications.
In the I²C protocol, all data Bytes are transmitted Most Significant Byte first, with each Byte
transmitted Most significant bit first.
Table 2.
CRX14 control registers
Address
00h
01h
02h
03h
Length
Parameter Register
Input/output Frame Register
Authenticate Register
Slot Marker Register
Access
Purpose
W
Set parameter register
R
Read parameter register
W
Store and send request frame to the PICC.
Wait for PICC answer frame
R
Transfer PICC answered frame data to Host
W
Start the Authentication process
R
Get the Authentication status
W
Launch the automated anti-collision process
from Slot_0 to Slot_15
R
Return data FFh
1 Byte
36 Bytes
NA
1 Byte
04h
ST Reserved
NA
R and W
ST Reserved. Must not be used
05h
ST Reserved
NA
R and W
ST Reserved. Must not be used
3.1
Parameter register (00h)
The Parameter Register is an 8-bit volatile register used to configure the CRX14, and thus,
to customize the circuit behavior. The Parameter Register is located at the I²C address 00h
and it is accessible in I²C Read and Write modes. Its default value, 00h, puts the CRX14 in
standard ISO14443 type-B configuration.
Table 3.
Bit
12/47
Parameter register bits description
Control
b0
Frame Standard
b1
RFU
Value
Description
0
ISO14443 type-B frame management
1
RFU(1)
0
Not used
Doc ID 8880 Rev 4
CRX14
CRX14 registers
Table 3.
Bit
Parameter register bits description (continued)
Control
b2
Answer Frame Format
b3
ASK Modulation Depth
b4
Carrier Frequency
b5
tWDG
b6
Answer delay watchdog
b7
RFU
Value
Description
0
Answer PICC Frames are delimited by SOF and EOF
1
Answer PICC Frames do not provide SOF and EOF
delimiters
0
10% ASK modulation depth mode
1
RFU
0
13.56MHz carrier on RF OUT is OFF
1
13.56MHz carrier on RF OUT is ON
b5=0, b6=0: Watchdog time-out = 500µs to be used for read
b5=0, b6=1: Watchdog time-out = 5ms to be used for authentication
b5=1, b6=0: Watchdog time-out = 10ms to be used for write
b5=1, b6=1: Watchdog time-out = 309ms to be used for MCU timings
0
Not used
1. RFU = Reserved for Future Use.
3.2
Input/output frame register (01h)
The Input/Output Frame Register is a 36-Byte buffer that is accessed serially from Byte 0
through to Byte 35 (see Table 4). It is located at the I²C address 01h.
The Input/Output Frame Register is the buffer in which the CRX14 stores the data Bytes of
the request frame to be sent to the PICC. It automatically stores the data Bytes of the
answer frame received from the PICC. The first Byte (Byte 0) of the Input/Output Frame
Register is used to store the frame length for both transmission and reception.
When accessed in I²C Write mode , the register stores the request frame Bytes that are to
be transmitted to the PICC. Byte 0 must be set with the request frame length (in Bytes) and
the frame is stored from Byte 1 onwards. At the end of the transmission, the 16-bit CRC is
automatically added. After the transmission, the CRX14 wait for the PICC to send back an
answer frame. When correctly decoded, the PICC answer frame Bytes are stored in the
Input/Output Frame Register from Byte 1 onwards. Byte 0 stores the number of Bytes
received from the PICC.
When accessed in I²C Read mode, the Input/Output Register sends back the last PICC
answer frame Bytes, if any, with Byte 0 transmitted first. The 16-bit CRC is not stored, and it
is not sent back on the I²C bus.
The Input/Output Frame Register is set to all 00h between transmission and reception. If
there is no answer from the PICC, Byte 0 is set to 00h. In the case of a CRC error, Byte 0 is
set to FFh, and the data Bytes are discarded and not appended in the register.
The CRX14 Input/Output Frame Register is so designed as to generate all the ST short
range memory command frames. It can also generate all standardized ISO14443 type-B
command frames like REQB, SLOT-MARKER, ATTRIB, HALT, and get all the answers like
ATQB, or answer to ATTRIB. All ISO14443 type-B compliant PICCs can be accessed by the
CRX14 provided that their data frame exchange is not longer than 35 Bytes in both request
and answer.
Doc ID 8880 Rev 4
13/47
CRX14 registers
Table 4.
CRX14
Input/output frame register description
Byte 0
Byte 1
Byte 2
Frame Length
First data Byte
Second data Byte
Byte 3
...
Byte 34
Byte 35
Last data Byte
00h No Byte transmitted
FFh CRC Error
xxh Number of transmitted Bytes
3.3
Authenticate register (02h)
The Authenticate Register is used to trigger the complete authentication exchange between
the CRX14 and the secured ST short range memory. It is located at the I²C address 02h.
The Authentication system is based on a proprietary challenge/response mechanism that
allows the application software to authenticate a secured ST short range memory of the
SRXxxx family. A reader designed with the CRX14 can check the authenticity of a memory
device and protect the application system against silicon copies or emulators.
A complete description of the Authentication system is available under Non Disclosure
Agreement (NDA) with STMicroelectronics. For more details about this CRX14 function,
please contact the nearest STMicroelectronics sales office.
3.4
Slot marker register (03h)
The slot Marker Register is located at the I²C address 03h. It is used to trigger an automated
anti-collision sequence between the CRX14 and any ST short range memory present in the
electromagnetic field. With one I²C access, the CRX14 launches a complete stream of
commands starting from PCALL16(), SLOT_MARKER(1), SLOT_MARKER(2) up to
SLOT_MARKER(15), and stores all the identified Chip_IDs into the Input/Output Frame
Register (I²C address 01h).
This automated anti-collision sequence simplifies the host software development and
reduces the time needed to interrogate the 16 slots of the STMicroelectronics anti-collision
mechanism.
When accessed in I²C Write mode, the Slot Marker Register starts generating the sequence
of anti-collision commands. After each command, the CRX14 wait for the ST short range
memory answer frame which contains the Chip_ID. The validity of the answer is checked
and stored into the corresponding Status Slot Bit (Byte 1 and Byte 2 as described in
Table 5). If the answer is correct, the Status Slot Bit is set to ‘1’ and the Chip_ID is stored
into the corresponding Slot_Register. If no answer is detected, the Status Slot Bit is set to
‘0’, and the corresponding Slot_Register is set to 00h. If a CRC error is detected, the Status
Slot Bit is set to ‘0’, and the corresponding Slot_Register is set to FFh.
Each time the Slot Marker Register is accessed in I²C Write mode, Byte 0 of the
Input/Output Frame Register is set to 18, Bytes 1 and 2 provide Status Bits Slot information,
and Bytes 3 to 18 store the corresponding Chip_ID or error code.
The Slot Marker Register cannot be accessed in I²C Read mode. All the anti-collision data
can be accessed by reading the Input/Output Frame Register at the I²C address 01h.
14/47
Doc ID 8880 Rev 4
CRX14
Table 5.
CRX14 registers
Slot marker register description
b7
b6
b5
b4
b3
b2
b1
b0
Byte 0
Number of stored Bytes: fixed to 18
Byte 1
Status Slot Status Slot Status Slot Status Slot Status Slot Status Slot Status Slot Status Slot
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 2
Status Slot Status Slot Status Slot Status Slot Status Slot Status Slot Status Slot Status Slot
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Byte 3
Slot_Register 0 = Chip_ID value detected in Slot 0
Byte 4
Slot_Register 1 = Chip_ID value detected in Slot 1
Byte 5
Slot_Register 2 = Chip_ID value detected in Slot 2
Byte 6
Slot_Register 3 = Chip_ID value detected in Slot 3
Byte n
.....
Byte 17
Slot_Register 14 = Chip_ID value detected in Slot 14
Byte 18
Slot_Register 15 = Chip_ID value detected in Slot 15
Status bit value description:
1: No error detected. The Chip_ID stored in the Slot register is valid.
0: Error detected
– Slot register = 00h: No answer frame detected from ST short range memory
– Slot register = FFh: Answer Frame detected with CRC error. Collision may have occurred
Doc ID 8880 Rev 4
15/47
CRX14 I²C protocol description
4
CRX14
CRX14 I²C protocol description
The CRX14 is compatible with the I²C serial bus memory standard, which is a two-wire
serial interface that uses a bi-directional data bus and serial clock.
The CRX14 has a pre-programmed, 4-bit identification code, ’1010’ (as shown in Table 6),
that corresponds to the I²C bus definition. With this code and the three Chip Enable inputs
(E2, E1, E0) up to eight CRX14 devices can be connected to the I²C bus, and selected
individually.
The CRX14 behaves as a slave device in the I²C protocol, with all CRX14 operations
synchronized to the serial clock.
I²C Read and Write operations are initiated by a START condition, generated by the bus
master.
The START condition is followed by the Device Select Code and by a Read/Write bit (R/W).
It is terminated by an acknowledge bit. The Device Select Code consists of seven bits (as
shown in Table 6):
●
the Device Code (first four bits)
●
plus three bits corresponding to the states of the three Chip Enable inputs, E2, E1 and
E0, respectively
When data is written to the CRX14, the device inserts an acknowledge bit (9th bit) after the
bus master’s 8-bit transmission.
When the bus master reads data, it also acknowledges the receipt of the data Byte by
inserting an acknowledge bit (9th bit).
Data transfers are terminated by a STOP condition after an ACK for Write, or after a NoACK
for Read.
The CRX14 supports the I²C protocol, as summarized in Figure 6.
Any device that sends data on to the bus, is defined as a transmitter, and any device that
reads the data, as a receiver.
The device that controls the data transfer is known as the master, and the other, as the
slave. A data transfer can only be initiated by the master, which also provides the serial
clock for synchronization. The CRX14 is always a slave device in all I²C communications. All
data are transmitted Most Significant Bit (MSB) first.
Table 6.
Device select code
Device code
CRX14 Select
4.1
Chip enable
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
E2
E1
E0
RW
I²C start condition
START is identified by a High-to-Low transition of the Serial Data line, SDA, while the Serial
Clock, SCL, is stable in the High state. A START condition must precede any data transfer
command.
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Doc ID 8880 Rev 4
CRX14
CRX14 I²C protocol description
The CRX14 continuously monitors the SDA and SCL lines for a START condition (except
during Radio Frequency data exchanges), and will not respond unless one is sent.
4.2
I²C stop condition
STOP is identified by a Low-to-High transition of the Serial Data line, SDA, while the Serial
Clock, SCL, is stable in the High state.
A STOP condition terminates communications between the CRX14 and the bus master.
A STOP condition at the end of an I²C Read command, after (and only after) a NoACK,
forces the CRX14 into its stand-by state.
A STOP condition at the end of an I²C Write command triggers the Radio Frequency data
exchange between the CRX14 and the PICC.
4.3
I²C acknowledge bit (ACK)
An acknowledge bit is used to indicate a successful data transfer on the I²C bus.
The bus transmitter, either master or slave, releases the Serial Data line, SDA, after sending
8 bits of data. During the 9th clock pulse the receiver pulls the SDA line Low to acknowledge
the receipt of the 8 data bits.
4.4
I²C data input
During data input, the CRX14 samples the SDA bus signal on the rising edge of the Serial
Clock, SCL. For correct device operation, the SDA signal must be stable during the Low-toHigh Serial Clock transition, and the data must change only when the SCL line is Low.
Doc ID 8880 Rev 4
17/47
CRX14 I²C protocol description
Figure 6.
CRX14
I²C bus protocol
SCL
SDA
START
CONDITION
SCL
1
SDA
MSB
SDA
INPUT
2
SDA
CHANGE
STOP
CONDITION
3
7
8
9
ACK
START
CONDITION
SCL
1
SDA
MSB
2
3
7
8
9
ACK
STOP
CONDITION
AI00792
4.5
I²C memory addressing
To start up communication with the CRX14, the bus master must initiate a START condition.
Then, the bus master sends 8 bits (with the most significant bit first) on the Serial Data line,
SDA. These bits consist of the Device Select Code (7 bits) plus a RW bit.
According to the I²C bus definition, the seven most significant bits of the Device Select Code
are the Device Type Identifier. For the CRX14, these bits are defined as shown in Table 6.
The 8th bit is the Read/Write bit (RW). It is set to ‘1’ for I²C Read, and to ‘0’ for I²C Write
operations.
If the data sent by the bus master matches the Device Select Code of a CRX14 device, the
corresponding device returns an acknowledgment on the SDA bus during the 9th bit time.
The CRX14 devices whose Device Select Codes do not correspond to the data sent,
generate a No-ACK. They deselect themselves from the bus and go into stand-by mode.
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Doc ID 8880 Rev 4
CRX14
4.6
CRX14 I²C protocol description
CRX14 I²C write operations
The bus master sends a START condition, followed by a Device Select Code and the R/W
bit set to ’0’. The CRX14 that corresponds to the Device Select Code, acknowledges and
waits for the bus master to send the Byte address of the register that is to be written to. After
receipt of the address, the CRX14 returns another ACK, and waits for the bus master to
send the data Bytes that are to be written.
In the CRX14 I²C Write mode, the bus master may sends one or more data Bytes depending
on the selected register.
The CRX14 replies with an ACK after each data Byte received. The bus master terminates
the transfer by generating a STOP condition.
The STOP condition at the end of a Write access to the Input/Output Frame, Authenticate or
Anti-Collision Register causes the Radio Frequency data exchange between the CRX14
and the PICC to be started.
During the Radio Frequency data exchange, the CRX14 disconnects itself from the I²C bus.
The time (tRFEX) needed to complete the exchange is not fixed as it depends on the PICC
command format. To know when the exchange is complete, the bus master uses an ACK
polling sequence as shown in Figure 8. It consists of the following:
Initial condition: a Radio Frequency data exchange is in progress.
●
Step 1: the master issues a START condition followed by the first Byte of the new
instruction (Device Select Code plus R/W bit).
●
Step 2: if the CRX14 is busy, no ACK is returned and the master goes back to Step 1. If
the CRX14 has completed the Radio Frequency data exchange, it responds with an
ACK, indicating that it is ready to receive the second part of the next instruction (the
first Byte of this instruction being sent during Step 1).
BUS Master
R/W
DEV SEL
BYTE ADDR
DATA 1
DATA 2
DATA N
DATA 3
STOP
CRX14 I²C write mode sequence
START
Figure 7.
●
CRX14 WRITE
BUS Slave
ACK
ACK
ACK
ACK
ACK
ACK
AI09265
Doc ID 8880 Rev 4
19/47
CRX14 I²C protocol description
Figure 8.
CRX14
I²C polling flowchart using ACK
Radio Frequency
data exchange
in progress
START Condition
DEVICE SELECT
CODE with R/W=1
NO
First byte of instruction
with R/W = 1 already
decoded by the CRX14
ACK
returned
YES
NO
Next
operation is
addressing
the CRX14
YES
Proceed to READ
Operation
ReSTART
STOP
STOP
ai09234
4.7
CRX14 I²C read operations
To send a Read command, the bus master sends a START condition, followed by a Device
Select Code and the R/W bit set to ’1’.
The CRX14 that corresponds to the Device Select Code acknowledges and outputs the first
data Byte of the addressed register.
To select a specific register, a dummy Write command must first be issued, giving an
address Byte but no data Bytes, as shown in the bottom half of Figure 9. This causes the
new address to be stored in the internal address pointer, for use by the Read command that
immediately follows the dummy Write command.
In the I²C Read mode, the CRX14 may read one or more data Bytes depending on the
selected register. The bus master has to generate an ACK after each data Byte to read all
the register data in a continuous stream. Only the last data Byte should not be followed by
an ACK. The master then terminates the transfer with a STOP condition, as shown in
Figure 9.
20/47
Doc ID 8880 Rev 4
CRX14
CRX14 I²C protocol description
After reading each Byte, the CRX14 waits for the master to send an ACK during the 9th bit
time. If the master does not return an ACK within this time, the CRX14 terminates the data
transfer and switches to stand-by mode.
Figure 9.
CRX14 I²C read modes sequences
ACK
R/W
ACK
ACK
ACK
NoACK
STOP
BUS Master
START
I²C CURRENT ADDRESS READ
DEV SEL
CRX14 READ
DATA 1
BUS Slave
DATA 2
DATA 3
DATA 4
DATA N
ACK
DEV SEL
ADDRESS
R/W
ACK
ACK
NoACK
STOP
R/W
Re-START
BUS Master
START
I²C RANDOM ADDRESS READ
DEV SEL
CRX14 READ
DATA 1
BUS Slave
ACK
ACK
DATA 2
DATA N
ACK
AI09266
Doc ID 8880 Rev 4
21/47
Applying the I²C protocol to the CRX14 registers
CRX14
5
Applying the I²C protocol to the CRX14 registers
5.1
I²C parameter register protocol
Figure 10 shows how new data is written to the Parameter Register. The new value
becomes active after the I²C STOP condition.
Figure 11 shows how to read the Parameter Register contents. The CRX14 sends and resends the Parameter Register contents until it receives a NoACK from the I²C Host.
The CRX14 supports the I²C Current Address and Random Address Read modes. The
Current Address Read mode can be used if the previous command was issued to the
register where the Read is to take place.
Figure 10. Host-to-CRX14 transfer: I²C write to parameter register
Bus Master
CRX14 Write
S
T
A
R
T
R/W
Device Select
Code
Parameter Register
Address
1 0 1 0 X X X
00h
Register Byte
Value
S
T
O
P
data
Bus Slave
ACK
ACK
ACK
ai09240
Figure 11. CRX14-to-host transfer: I²C random address read from parameter register
Bus Master
CRX14 Read
S
T
A
R
T
R
E
S
T
A
R
T
R/W
Device Select
Code
Parameter Register
Address
1 0 1 0 X X X
00h
R/W
S
T
O
P
Device Select
Code
data
1 0 1 0 X X X
Bus Slave
ACK
ACK
NoACK
ACK
Register Byte
Value
ai09241
Figure 12. CRX14-to-host transfer: I²C current address read from parameter register
Bus Master
CRX14 Read
S
T
A
R
T
R/W
NoACK
Device Select
Code
1 0 1 0 X X X
S
T
O
P
data
Bus Slave
ACK
Register Byte
Value
ai09242
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Doc ID 8880 Rev 4
CRX14
Applying the I²C protocol to the CRX14 registers
5.2
I²C input/output frame register protocol
Figure 13 shows how to store a PICC request frame command of N Bytes into the
Input/Output Frame Register.
After the I²C STOP condition, the request frame is RF transmitted in the ISO14443 type-B
format. The CRX14 then waits for the PICC answer frame which will also be stored in the
Input/Output Frame Register. The request frame is over-written by the answer frame.
Figure 14 shows how to read an N-Byte PICC answer frame.
The two CRC Bytes generated by the PICC are not stored.
The CRX14 continues to output data Bytes until a NoACK has been generated by the I²C
Host, and received by the CRX14. After all 36 Bytes have been output, the CRX14 “rolls
over”, and starts outputting from the start of the Input/Output Frame Register again.
The CRX14 supports the I²C Current Address and Random Address Read modes. The
Current Address Read mode can be used if the previous command was issued to the
register where the Read is to take place.
Figure 13. Host-to-CRX14 transfer: I²C write to I/O frame register for ISO14443B
Bus
Master
CRX14
Write
S
T
A
R
T
R/W
Device
Select
Code
Input/Output
Register
Address
1 0 1 0 XX X
Bus
Slave
PICC
Command
Code
Request Frame
Length N
01h
N
ACK
PICC
Command
Parameter
Data 1
ACK
PICC
Command
Parameter
Data 2
ACK
ACK
PICC
Command
Parameter
S
T
O
P
Data N
ACK
ACK
ACK
ai09243
Figure 14. CRX14-to-host transfer: I²C random address read from I/O frame register for
ISO14443B
R/W
S
Device
T
Select
Bus
A
Code
Master R
T
CRX14
1 0 1 0XXX
Read
Bus
Slave
Input/Output
Register
Address
01h
ACK
R
E
S
T
A
R
T
ACK
ACK
R/W
ACK
ACK
NoACK
Device
Select
Code
1 0 1 0 XXX
ACK
S
T
O
P
N
Received
ACK Frame
Length
Data1
Answer
Frame
Data
Data 2
Answer
Frame
Data
Data N
Answer
Frame
Data
Answer
Frame
Data
ai09243
Doc ID 8880 Rev 4
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Applying the I²C protocol to the CRX14 registers
CRX14
Figure 15. CRX14-to-host transfer: I²C current address read from I/O frame register
for ISO14443B
S
T
A
R
T
Bus Master
CRX14 Write
ACK
R/W
ACK
ACK
ACK
NoACK
Device
Select
Code
S
T
O
P
1 0 1 0 XX X
N
Bus Slave
ACK
Data 1
Answer Frame
Received
Data
Frame Length
Data 2
Data N
Answer Frame
Data
Answer Frame
Data
Answer Frame
Data
ai09245
5.3
I²C authenticate register protocol
For information please contact your nearest STMicroelectronics sales office.
5.4
I²C slot marker register protocol
An I²C Write command to the Slot Marker Register generates an automated sixteencommand loop (See Figure 16 for a description of the command).
All the answers from the ST short range memory devices that are detected, are written in
the Input/Output Frame Register.
Read from the I²C Slot Marker Register is not supported by the CRX14. If the I²C Host tries
to read the Slot Marker Register, the CRX14 will return the data value FFh in both Random
Address and Current Address Read modes until NoACK is generated by the I²C Host.
The result of the detection sequence is stored in the Input/Output Frame Register. This
Register can be read by the host by using I²C Random Address Read.
Figure 16. Host-to-CRX14 transfer: I²C write to slot marker register
Bus Master
CRX14 Write
S
T
A
R
T
R/W
Device Select
Code
Slot Marker
Register
Address
1 0 1 0 X X X
03h
S
T
O
P
Bus Slave
ACK
ACK
ai09246
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Doc ID 8880 Rev 4
CRX14
Applying the I²C protocol to the CRX14 registers
Figure 17. CRX14-to-host transfer: I²C random address read from slot marker register
Bus Master
CRX14 Read
S
T
A
R
T
R/W
Device Select
Code
Slot Marker
Register
Address
1 0 1 0 X X X
00h
R
E
S
T
A
R
T
R/W
NoACK
Device Select
Code
S
T
O
P
FFh
1 0 1 0 X X X
Bus Slave
ACK
ACK
ACK
ai09247
Figure 18. CRX14-to-host transfer: I²C current address read from slot marker register
Bus Master
CRX14 Read
S
T
A
R
T
R/W
NoACK
Device Select
Code
S
T
O
P
FFh
1 0 1 0 X X X
Bus Slave
ACK
ai09248
5.5
Addresses above location 06h
In I²C Write mode, when the CRX14 receives the 8-bit register address, and the address is
above location 06h, the device does not acknowledge (NoACK) and deselects itself from the
bus. The Serial Data line, SDA, stays at logic ‘1’ (pull-up resistor), and the I²C Host receives
a NoACK during the 9th bit time. The SDA line stays High until the STOP condition is issued.
In the I²C Current and Random Address Read modes, when the CRX14 receives the 8-bit
register address, and the address is above location 06h, the device does not acknowledge
the Device Select Code after the START condition, and deselects itself from the bus.
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25/47
CRX14 ISO14443 type-B radio frequency data transfer
CRX14
6
CRX14 ISO14443 type-B radio frequency data
transfer
6.1
Output RF data transfer from the CRX14 to the PICC (request
frame)
The CRX14 output buffer is controlled by the 13.56MHz clock signal generated by the
external oscillator and by the request frame generator. The CRX14 can be directly
connected to an external matching circuit to generate a 13.56MHz sinusoidal carrier
frequency on its antenna.
The current driven into the antenna coil is directly generated by the CRX14 RFOUT output
driver.
If the antenna is correctly tuned, it emits an H-field of a large enough magnitude to power a
contactless PICC from a short distance. The energy received on the PICC antenna is
converted to a Power Supply Voltage by a regulator, and turned into data bits by the ASK
demodulator. The CRX14 amplitude modulates the 13.56MHz wave by 10% as represented
in Figure 19. The data transfer rate is 106 kbit/s.
Figure 19. Wave transmitted using ASK modulation
DATA BIT TRANSMITTED
BY THE CRX14
10% ASK MODULATION
OF THE 13.56MHz WAVE,
GENERATED BY THE RFOUT
DRIVER
10% ASK MODULATION
OF THE 13.56MHz WAVE,
GENERATED ON THE CRX14
ANTENNA
Transfer time for one data bit is 1/106 kHz
AI10912
6.2
Transmission format of request frame characters
The CRX14 transmits characters of 10 bits, with the Least Significant Bit (b0) transmitted
first, as shown in Figure 20.
Several 10-bit characters, preceded by the Start Of Frame (SOF) and followed by the End Of
Frame (EOF), constitute a Request Frame, as shown in Figure 26.
A Request Frame includes the SOF, instructions, addresses, data, CRC and the EOF as
defined in the ISO14443 type-B.
Each bit duration is called an Elementary Time Unit (ETU). One ETU is equal to 9.44µs
(1/106kHz).
26/47
Doc ID 8880 Rev 4
CRX14
CRX14 ISO14443 type-B radio frequency data transfer
Figure 20. CRX14 request frame character format
b0
b1
b2
b3
1
Start LSB
ETU
'0'
b4
b5
b6
b7
b8
b9
MSB Stop
'1'
Information Byte
ai09250
Table 7.
CRX14 request frame character format
Bit
6.3
Description
Value
b0
Start bit used to synchronize the transmission
b0 = 0
b1 to b8
Information Byte (instruction, address or data)
Information Byte is sent Least
Significant Bit first
b9
Stop bit used to indicate the end of the character
b9 = 1
Request start of frame
The Start Of Frame (SOF) described in Figure 21 consists of:
●
a falling edge,
●
followed by ten Elementary Time Units (ETU) each containing a logical ‘0’
●
followed by a single rising edge
●
followed by two ETUs, each containing a logical ‘1’.
Figure 21. Request start of frame
ETU
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
0
0
0
0
0
0
0
0
0
0
1
1
ai09251
6.4
Request end of frame
The End Of Frame (EOF) shown in Figure 22 consists of:
●
a falling edge,
●
followed by ten Elementary Time Units (ETU) containing each a logical ‘0’,
●
followed by a single rising edge.
Figure 22. Request end of frame
ETU
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
0
0
0
0
0
0
0
0
0
0
ai09252
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27/47
CRX14 ISO14443 type-B radio frequency data transfer
6.5
CRX14
Input RF data transfer from the PICC to the CRX14 (answer
frame)
The CRX14 uses the ISO14443 type-B retro-modulation scheme which is demodulated and
decoded by the RFIN circuitry.
The modulation is obtained by modifying the PICC current consumption (load modulation).
This load modulation induces an H-field variation, by coupling, that is detected by the
CRX14 RFIN input as a voltage variation on the antenna. The RFIN input demodulates this
variation and decodes the information received from the PICC.
Data must be transmitted using a 847kHz, BPSK modulated sub-carrier frequency, fS, as
shown in Figure 23, and as specified in ISO14443 type-B. In BPSK, all data state transitions
(from ‘0’ to ‘1’ or from ‘1’ to ‘0’) are encoded by phase shift keying the sub-carrier.
Figure 23. Wave received using BPSK sub-carrier modulation
1/106kHz
PICC data bit to be transmitted
to the CRX14.
847kHz BPSK, resulting signal
generated by the PICC for the
load modulation.
1/847kHz
phase shift
VRFIN
VRET
VDYN
Load modulation effect on
the H-Field received on the
CRX14 RFIN input pad
VOFFSET
t
ai09253
6.6
Transmission format of answer frame characters
The PICC should use the same character format as that used for output data transfer (see
Figure 20).
An Answer Frame includes the SOF, data, CRC and the EOF, as illustrated in Figure 26. The
data transfer rate is 106 kbit/s.
The CRX14 will also accept Answer Frames that do not contain the SOF and EOF
delimiters, provided that these Frames are correctly set in the Parameter Register. (See
Figure 26).
28/47
Doc ID 8880 Rev 4
CRX14
6.7
CRX14 ISO14443 type-B radio frequency data transfer
Answer start of frame
The PICC SOF must be compliant with the ISO14443 type-B, and is shown in Figure 24
●
Ten or eleven Elementary Time Units (ETU) each containing a logical ‘0’,
●
Two ETUs containing a logical ‘1’.
Figure 24. Answer start of frame
ETU
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
0
0
0
0
0
0
0
0
0
0
1
1
1
ai09254
6.8
Answer end of frame
The PICC EOF must be compliant with the ISO14443 type-B, and is shown in Figure 25:
●
Ten or eleven Elementary Time Units (ETU) each containing a logical ‘0’,
●
Two ETUs containing a logical ‘1’
Figure 25. Answer end of frame
ETU
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
0
0
0
0
0
0
0
0
0
0
1
1
1
ai09254
6.9
Transmission frame
The Request Frame transmission must be followed by a minimum delay, t0 (see Table ), in
which no ASK or BPSK modulation occurs, before the Answer Frame can be transmitted. t0
is the minimum time required by the CRX14 to switch from transmission mode to reception
mode, and should be inserted after each frame. After t0, the 13.56MHz carrier frequency is
modulated by the PICC at 847kHz for a minimum time of t1 (see Table ) to allow the CRX14
to synchronize. After t1, the first phase transition generated by the PICC represents the start
bit (‘0’) of the Answer SOF (or the start bit ‘0’ of the first data character in non SOF/EOF
mode).
Doc ID 8880 Rev 4
29/47
CRX14 ISO14443 type-B radio frequency data transfer
CRX14
Figure 26. Example of a complete transmission frame
Sent by
the CRX14
SOF
12 bits
at 106Kb/s
Cmd
Data
CRC
CRC
EOF
10 bits
10 bits
10 bits
10 bits
10 bits
tDR
fs = 847.5kHz
Sync
Case of Answer Frame with SOF & EOF
t0
64/fs Min
Sent by the PICC
t1
80/fs Min
SOF
12 or 13
bits
Data
CRC
CRC
10 bits
10 bits
10 bits
EOF
12 or 13
bits
tWDG
Sync
Case of Answer Frame without SOF & EOF
t0
64/fs Min
t1
80/fs Min
Data
Data
Data
CRC
CRC
10 bits
10 bits
10 bits
10 bits
10 bits
tWDG
Output Data Transfer using ASK Modulation
Input Data Transfer using 847kHz BPSK Modulation
ai09255
6.10
CRC
The 16-bit CRC used by the CRX14 follows the ISO14443 type B recommendation. For
further information, please see Appendix A on page 44.
The two CRC Bytes are present in all Request and Answer Frames, just before the EOF.
The CRC is calculated on all the Bytes between the SOF and the CRC Bytes.
Upon transmission of a Request from the CRX14, the PICC verifies that the CRC value is
valid. If it is invalid, it discards the frame and does not answer the CRX14.
Upon reception of an Answer from the PICC, the CRX14 verifies that the CRC value is valid.
If it is invalid, it stores the value FFh in the Input/Output Frame Register.
The CRC is transmitted Least Significant Byte first. Each Byte is transmitted Least
Significant Bit first.
Figure 27. CRC transmission rules
LSByte
LSBit
MSByte
MSBit LSBit
CRC 16 (8 bits)
MSBit
CRC 16 (8 bits)
ai09256
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Doc ID 8880 Rev 4
CRX14
7
Tag access using the CRX14 coupler
Tag access using the CRX14 coupler
In all the following I²C commands, the last three bits of the Device Select Code can be
replaced by any of the three-bit binary values (000, 001, 010, 011, 100, 101, 110, 111).
These values are linked to the logic levels applied to the E2, E1 and E0 pads of the CRX14.
7.1
Standard TAG command access description
Standard PICC commands, like Read and Write, are generated by the CRX14 using the
Input/Output Frame Register.
When the host needs to send a standard frame command to the PICC, it first has to
internally generate the complete frame, with the command code followed by the command
parameters. Only the two CRC Bytes should not be generated, as the CRX14 automatically
adds them during the RF transmission.
When the frame is ready, the host has to write the request frame into the Input/Output Frame
Register using the I²C write command specified in Figure 13 on page 23. After the I²C STOP
condition, the CRX14 inserts the I²C Bytes in the required ISO character format ( Figure 20)
and starts to transmit the request frame to the PICC. Once the RF transmission is over, the
CRX14 waits for the PICC to send an answer frame.
If the PICC answers, the characters received (Figure 26) are demodulated, decoded and
stored into the Input/Output Frame Register, as specified in Table 4. During the entire RF
transmission, the CRX14 disconnects itself from the I²C bus. On reception of the PICC EOF,
the CRX14 checks the CRC and reconnects itself to the I²C bus.
The host can then get the PICC answer frame by issuing an Input/Output Frame Register
Read on the I²C bus, as specified in Figures 14 and 15.
If no answer from the PICC is detected after a time-out delay, fixed in the Parameter
Register (bits b5 and b6), the Input/Output Frame Register is set as specified in Table 4.
Figure 28. Standard TAG command: request frame transmission
S
T
A Device
R Select
T Code
I²C
RF
Input/
Output
Register
Address
Request
Frame
Length
TAG
Cmd
Code
01h
N
Data 1
Param
Data 2
Param
Data
S
T
O
P
Param
CRX14
SOF
TAG
Cmd
Code
Param
Param
Param
CRC
CRC
SRX14
EOF
Data 2
Data
Data N
CRC
CRC
EOF
Data N
SOF
Data 1
ai09260
Doc ID 8880 Rev 4
31/47
Tag access using the CRX14 coupler
CRX14
Figure 29. Standard TAG command: answer frame reception
TAG
SOF
TAG
Data
TAG
Data
TAG
Data
TAG
Data
TAG
CRC
TAG
CRC
TAG
EOF
S
T
A Device
R Select
T Code
I²C
RF
SOF
Data 1
Data 2
Data
Data P
CRC
CRC
Input/
Output
Register
Address
Answer
Frame
Length
TAG
Data
01h
P
Data 1
TAG
Data
Data 2
TAG
Data
Data
S
T
O
P
TAG
Data
Data P
EOF
ai09261
Figure 30. Standard TAG command: complete TAG access description
Device
I/O
Request Request
Select
Code Register Frame Frame
Write Address Length Bytes
I²C
START
Device Answer Request
Select Frame Frame
Code Length Bytes
Read
STOP
START
STOP
SOF
RF
EOF
SOF
EOF
Request
TAG
Frame
CRC T0 T1 Answer Frame CRC
Characters
Characters
ai09262
7.2
Anti-collision TAG sequence
The CRX14 can identify an ST short range memory using a proprietary anti-collision
system.
Issuing an I²C Write command to the Slot Marker Register (Figure 16) causes the CRX14
TO automatically generate a 16-slot anti-collision sequence, and to store the identified
Chip_ID in the Input/Output Frame Register, as specified in Table 4.
After receiving the Slot Marker Register I²C Write command, the CRX14 generates an RF
PCALL16 command followed by fifteen SLOT_MARKER commands, from
SLOT_MARKER(1) to SLOT_MARKER(15). After each command, the CRX14 waits for a
tag answer. If the answer is correctly decoded, the corresponding Chip_ID is stored in the
Input/Output Frame Register. If there is no answer, or if the answer is wrong (with a CRC
error, for example), the CRX14 stores an error code in the Input/Output Frame Register. At
the end of the sequence, the host has to read the Input/Output Frame Register to retrieve all
the identified Chip_IDs.
32/47
Doc ID 8880 Rev 4
CRX14
Tag access using the CRX14 coupler
Figure 31. Anti-collision ST short range memory sequence (1)
S
Slot S
T Device Marker
T CRX14
A Select Register
SOF
R Code Address O
P
T
I²C
RF
PCALL 16 TAG
Command
CRC
CRC
CRX14
EOF
CRC
CRC
EOF
Slot Marker CRC
Command
CRC
CRX14
EOF
TAG
SOF
TAG
Chip_ID
TAG
CRC
TAG
CRC
TAG
EOF
SOF
Chip_ID
CRC
CRC
EOF
TAG
SOF
TAG
Chip_ID
TAG
CRC
TAG
CRC
TAG
EOF
03h
Slot 0
SOF
06h
CRX14
SOF
04h
t0 t1
I²C
RF...
Slot 1
SOF
16h
CRC
CRC
EOF
t0 t1
SOF
Chip_ID
CRC
CRC
EOF
Slot 2
SOF
26h
CRC
CRC
EOF
t0 t1
SOF
Chip_ID
CRC
CRC
EOF
Slot 3
SOF
36h
CRC
CRC
EOF
t0 t1
SOF
Chip_ID
CRC
CRC
EOF
Slot 4
SOF
46h
CRC
CRC
EOF
t0 t1
SOF
Chip_ID
CRC
CRC
EOF
Slot 5
SOF
56h
CRC
CRC
EOF
t0 t1
SOF
Chip_ID
CRC
CRC
EOF
Slot 6
SOF
66h
CRC
CRC
EOF
t0 t1
SOF
Chip_ID
CRC
CRC
EOF
Slot 7
SOF
76h
CRC
CRC
EOF
t0 t1
SOF
Chip_ID
CRC
CRC
EOF
Slot 8
SOF
86h
CRC
CRC
EOF
t0 t1
SOF
Chip_ID
CRC
CRC
EOF
Slot 9
SOF
96h
CRC
CRC
EOF
t0 t1
SOF
Chip_ID
CRC
CRC
EOF
I²C
RF...
I²C
RF...
I²C
RF...
I²C
RF...
I²C
RF...
I²C
RF...
I²C
RF...
I²C
RF...
ai09263
Doc ID 8880 Rev 4
33/47
Tag access using the CRX14 coupler
CRX14
Figure 32. Anti-collision ST short range memory sequence continued
I²C
RF ...
Slot 10
SOF
96h
CRC
CRC
EOF
t0 t1
SOF
Chip_ID
CRC
CRC
EOF
Slot 11
SOF
56h
CRC
CRC
EOF
t0 t1
SOF
Chip_ID
CRC
CRC
EOF
Slot 12
SOF
66h
CRC
CRC
EOF
t0 t1
SOF
Chip_ID
CRC
CRC
EOF
Slot 13
SOF
76h
CRC
CRC
EOF
t0 t1
SOF
Chip_ID
CRC
CRC
EOF
Slot 14
SOF
86h
CRC
CRC
EOF
t0 t1
SOF
Chip_ID
CRC
CRC
EOF
Slot 15
SOF
96h
CRC
CRC
EOF
SOF
Chip_ID
CRC
CRC
EOF
I²C
RF ...
I²C
RF ...
I²C
RF ...
I²C
RF ...
I²C
RF ...
S
T Device
A Select
R Code
T
I²C ...
RF
t0
t1
R
E
S
T Device Answer Status
Status
Slot 1
I/O
Slot 2
Slot 3
Slot 4
Slot 5
Slot 6
Slot 7
Slot 8
Slot 0
Register A Select Frame Slot Bits Slot Bits Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID
Address R Code Length b0 to b7 b8 to b15 Answer Answer Answer Answer Answer Answer Answer Answer Answer
T
01h
12h
Status
Status Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID
S
Slot 9
Slot 10 Slot 11 Slot 12 Slot 13 Slot 14 Slot 15 T
Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID O
Answer Answer Answer Answer Answer Answer Answer P
I²C ... Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID
RF
ai09264
34/47
Doc ID 8880 Rev 4
CRX14
8
Maximum rating
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions
for extended periods may affect device reliability. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the
Operating sections of this specification is not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 8.
Absolute maximum ratings
Symbol
Value
Unit
Storage Temperature
–65 to 150
°C
VIO
Input or Output range (SDA)
–0.3 to 6.5
V
VIO
Input or Output range (other pads)
–0.3 to Vcc+0.3
V
VCC
Supply Voltage
–0.3 to 6.5
V
POUT
Output Power on Antenna Output Driver (RFOUT)
100
mW
Electrostatic Discharge Voltage (Human Body model) (1)
4000
V
Electrostatic Discharge Voltage (Machine model) (2)
500
V
TSTG
VESD
Parameter
1. MIL-STD-883C, 3015.7 (100 pF, 1500 ).
2. EIAJ IC-121 (Condition C) (200 pF, 0 )
Doc ID 8880 Rev 4
35/47
DC and AC parameters
9
CRX14
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 9.
I²C AC measurement conditions
Parameter
Min.
Max.
Unit
VCC Supply Voltage
4.5
5.5
V
Ambient Operating Temperature (TA)
–20
85
°C
50
ns
Input Rise and Fall Times
Input Pulse Voltages
0.2VCC
0.8VCC
V
Input and Output Timing Reference Voltages
0.3VCC
0.7VCC
V
Figure 33. I²C AC testing I/O waveform
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI09235
Table 10.
I²C input parameters(1,2)
Symbol
Parameter
Min.
Max.
Unit
CIN
Input Capacitance (SDA)
8
pF
CIN
Input Capacitance (SCL, E0, E1, E2))
6
pF
tNS
Low Pass Filter Input Time Constant (SCL & SDA Inputs)
400
ns
Max.
Unit
100
1. Sampled only, not 100% tested.
2. TA = 25 °C, f = 400kHz.
Table 11.
Symbol
36/47
I²C DC characteristics
Parameter
Test condition
Min.
ILI
Input Leakage Current
(SCL, SDA, E0, E1, E2)
0V VIN VCC
±2
µA
ILO
Output Leakage Current
(SCL, SDA, E0, E1, E2)
0V VOUT VCC, SDA in Hi-Z
±2
µA
Doc ID 8880 Rev 4
CRX14
DC and AC parameters
Table 11.
I²C DC characteristics (continued)
Symbol
ICC
Parameter
Test condition
Min.
Max.
Unit
VCC = 5 V, fC = 400 kHz
(rise/fall time < 30ns), RF OFF
6
mA
VCC = 5V, fC = 400 kHz (rise/fall
time < 30ns), RF ON
20
mA
VIN = VSS or VCC, VCC = 5 V, RF
OFF
5
mA
Supply Current
ICC1
Supply Current (Stand-by)
VIL
VIH
VOL
Input Low Voltage (SCL,
SDA)
–0.3
0.3VCC
V
Input Low Voltage (E0, E1,
E2)
–0.3
0.3VCC
V
Input High Voltage (SCL,
SDA)
0.7VCC VCC + 1
V
Input High Voltage (E0, E1,
E2)
0.7VCC VCC + 1
V
IOL = 3 mA, VCC = 5 V
Output Low Voltage (SDA)
0.4
V
Figure 34. I²C AC waveforms
tCHCL
CLCH
SCL
tDXCX
tDLCL
tCHDH
SDA IN
tCHDX
START
CONDITION
tCLDX
SDA
INPUT
tDHDL
STOP &
BUS FREE
SDA
CHANGE
SCL
tCLQV
tCLQX
DATA VALID
SDA OUT
DATA OUTPUT
SCL
tRFEX
SDA IN
tCHDX
tCHDH
STOP
CONDITION
CRX14 command execution
START
CONDITION
ai09236
Doc ID 8880 Rev 4
37/47
DC and AC parameters
Table 12.
Symbol
CRX14
I²C AC characteristics
Alt.
Parameter
Fast I²C
I²C
400 kHz
100 kHz
Min
tCH1CH2
Min
Max
tR
Clock Rise Time
300
1000
ns
tCL1CL2(1)
tF
Clock Fall Time
300
300
ns
tDH1DH2(1
tR
SDA Rise Time
20
300
20
1000
ns
tDL1DL2(1)
tF
SDA Fall Time
20
300
20
300
ns
tCHDX (2)
tSU:STA
Clock High to Input Transition
600
4700
ns
tCHCL
tHIGH
Clock Pulse Width High
600
4000
ns
tDLCL
tHD:STA
Input Low to Clock Low (START)
600
4000
ns
tCLDX
tHD:DAT
Clock Low to Input Transition
0
0
µs
tCLCH
tLOW
Clock Pulse Width Low
1.3
4.7
µs
tDXCX
tSU:DAT
Input Transition to Clock Transition
100
250
ns
tCHDH
tSU:STO
Clock High to Input High (STOP)
600
4000
ns
tDHDL
tBUF
Input High to Input Low (Bus Free)
1.3
4.7
µs
tCLQV
tAA
Clock Low to Data Out Valid
tCLQX
tDH
Data Out Hold Time After Clock Low
fC
fSCL
Clock Frequency
(1)
)
1. Sampled only, not 100% tested.
2. For a reSTART condition, or following a write cycle.
38/47
Max
Unit
Doc ID 8880 Rev 4
1000
200
3500
200
400
ns
ns
100
kHz
CRX14
DC and AC parameters
Figure 35. CRX14 synchronous timing
RFOUT ASK Modulated Signal
VRFOUT
tRFSBL
tRFF
A
tRFR
B
fCC
tPOR
FRAME transmission between the reader and the contactless device
tDR
1
tDR
0
DATA 1
EOF
FRAME transmitted by the CRX14 in ASK
847kHz
FRAME transmitted by the PICC in BPSK
t0
SOF
t1
1 1 0 DATA
tDA
1 0 DATA
1 0
tDA
Data jitter on FRAME transmitted by the CRX14 in ASK
tJIT
tJIT
tJIT
tJIT
tJIT
0
START
tRFSBL
tRFSBL
tRFSBL
tRFSBL
tRFSBL
ai09258
Table 13.
Symbol
RFOUT AC characteristics
Parameter(1)
Condition
Min.
Max.
Unit
fCC
External Oscillator Frequency
VCC = 5 V
13.553
13.567
MHz
MICARRIER
Carrier Modulation Index
MI=(A-B)/(A+B)
10
14
%
tRFR, tRFF
10% Rise and Fall time
0.5
1.5
µs
tRFSBL
Pulse Width on RFOUT
1 ETU = 128/fCC
9.44
tJIT
ASK modulation bit jitter
CRX14 to PICC
-0.5
t0
Antenna Reversal delay
Min = 64/fS
75
µs
t1
Synchronization delay
Min = 80/fS
94
µs
Doc ID 8880 Rev 4
µs
0.5
µs
39/47
DC and AC parameters
Table 13.
Symbol
CRX14
RFOUT AC characteristics (continued)
Parameter(1)
Condition
Min.
Max.
Unit
tWDG
Answer delay watchdog (b5=0, b6=0)
tWDG
Answer delay watchdog (b5=0, b6=1)
tWDG
Answer delay watchdog (b5=1, b6=0)
tWDG
Answer delay watchdog (b5=1, b6=1)
tDR
Time Between Request characters
PA
RFOUT output power
90
mW
tPOR
CRX14 Power-On delay
20
ms
Request EOF
rising edge to
first Answer
start bit
CRX14 to PICC
500
µs
5
ms
10
ms
309
ms
9.44
µs
1. Data specified in the table above are estimated or target values. All values can be updated during product qualification.
Table 14.
Symbol
tRFSBL
RFIN AC characteristics
Parameter(1)
PICC Pulse Width
fS
PICC Sub-carrier Frequency
tDA
Time Between Answer characters
VDYN
VOFFSET
VRET
RFIN Dynamic Voltage Level
Condition
Min.
Max.
1 ETU = 128/fCC
9.44
µs
fCC/16
847.5
KHz
PICC to CRX14
1, 2, 3
ETU
VDYN Max for VOFFSET = VCC/2
RFIN Offset Voltage Level
RFIN Retro-modulation Level
0.5
VCC/2
V
2
3
V
120
1. Data specified in the table above are estimated or target values. All values can be updated during product qualification.
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Unit
Doc ID 8880 Rev 4
mV
CRX14
10
Package mechanical
Package mechanical
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark
Doc ID 8880 Rev 4
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Package mechanical
CRX14
Figure 36. SO16 narrow - 16 lead plastic small outline, 150 mils body width, package
outline
H§
$
!
!
C
!
B
MM
'AGEPLANE
CCC#
%
%
,
K
1?-%
E
1. Drawing is not to scale.
Table 15.
SO16 narrow - 16 lead plastic small outline, 150 mils body width,
package mechanical data
Millimeters
Inches
Symbol
Typ.
Min.
A
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Max.
Typ.
Min.
1.75
Max.
0.0689
A1
0.1
0.25
0.0039
0.0098
A2
1.25
b
0.31
0.51
0.0122
0.0201
c
0.17
0.25
0.0067
0.0098
0.0492
D
9.9
9.8
10
0.3898
0.3858
0.3937
E
6
5.8
6.2
0.2362
0.2283
0.2441
E1
3.9
3.8
4
0.1535
0.1496
0.1575
e
1.27
0.05
h
0.25
0.5
0.0098
0.0197
L
0.4
1.27
0.0157
0.05
k
0°
8°
0°
8°
Tolerance
millimeters
inches
ccc
0.1
0.0039
Doc ID 8880 Rev 4
CRX14
11
Ordering information
Ordering information
Table 16.
Ordering information scheme
Example:
CRX14
–
MQ / XXX
Device type
CRX14
Package
MQ = SO16 Narrow (150 mils width)
MQP = SO16 Narrow (150 mils width) ECOPACK®
Customer code
XXX = Given by the issuer
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST Sales Office.
Doc ID 8880 Rev 4
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ISO14443 type B CRC calculation
Appendix A
CRX14
ISO14443 type B CRC calculation
#include
#include
#include
#include
#define BYTEunsigned char
#define USHORTunsigned short
unsigned short UpdateCrc(BYTE ch, USHORT *lpwCrc)
{
ch = (ch^(BYTE)((*lpwCrc) & 0x00FF));
ch = (ch^(ch 8)^((USHORT)ch > 8) & 0xFF);
return;
}
int main(void)
{
BYTE BuffCRC_B[10] = {0x0A, 0x12, 0x34, 0x56}, First, Second, i;
printf("Crc-16 G(x) = x^16 + x^12 + x^5 + 1");
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Doc ID 8880 Rev 4
CRX14
ISO14443 type B CRC calculation
printf("CRC_B of [ ");
for(i=0; i
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