E-L6385D013TR

L6385 ® HIGH-VOLTAGE HIGH AND LOW SIDE DRIVER HIGH VOLTAGE RAIL UP TO 600 V dV/dt IMMUNITY +- 50 V/nsec IN FULL TEMPERATURE RANGE DRIVER CURRENT CAPABILITY: 400 mA SOURCE, 650 mA SINK SWITCHING TIMES 50/30 nsec RISE/FALL WITH 1nF LOAD CMOS/TTL SCHMITT TRIGGER INPUTS WITH HYSTERESIS AND PULL DOWN UNDER VOLTAGE LOCK OUT ON LOWER AND UPPER DRIVING SECTION INTERNAL BOOTSTRAP DIODE OUTPUTS IN PHASE WITH INPUTS ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O DESCRIPTION The L6385 is an high-voltage device, manufactured with the BCD"OFF-LINE" technology. It has a Driver structure that enables to drive inde- SO8 Minidip ORDERING NUMBERS: L6385D L6385 pendent referenced N Channel Power MOS or IGBT. The Upper (Floating) Section is enabled to work with voltage Rail up to 600V. The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices. BLOCK DIAGRAM BOOTSTRAP DRIVER VCC 3 UV DETECTION 8 UV DETECTION H.V. HVG DRIVER R R HIN 2 LOGIC LEVEL SHIFTER Cboot HVG 7 S OUT VCC LIN Vboot 1 LVG DRIVER 6 TO LOAD 5 LVG 4 GND D97IN514B November 2003 1/9 L6385 ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Vout Output Voltage Parameter -3 to Vboot - 18 V Vcc Supply Voltage - 0.3 to +18 V Vboot Floating Supply Voltage - 1 to 618 V Vhvg Vlvg Upper Gate Output Voltage Lower Gate Output Voltage - 1 to Vboot -0.3 to Vcc +0.3 V V Vi dVout/dt Logic Input Voltage Allowed Output Slew Rate -0.3 to Vcc +0.3 50 V V/ns Ptot Total Power Dissipation (Tj = 85 °C) 750 mW Tj Junction Temperature 150 °C Ts Storage Temperature -50 to 150 °C ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Note: ESD immunity for pins 6, 7 and 8 is guaranteed up to 900V (Human Body Model) PIN CONNECTION LIN 1 8 Vboot HIN 2 7 HVG Vcc 3 6 OUT GND 4 5 LVG D97IN517 THERMAL DATA Symbol Rth j-amb Parameter Thermal Resistance Junction to Ambient SO8 Minidip Unit 150 100 °C/W PIN DESCRIPTION N. Name Type Function 1 2 3 4 LIN HIN Vcc GND I I I Lower Driver Logic Input Upper Driver Logic Input Low Voltage Power Supply Ground 5 6 7 LVG (*) VOUT HVG (*) O O O Low Side Driver Output Upper Driver Floating Reference High Side Driver Output 8 Vboot Bootstrap Supply Voltage (*) The circuit guarantees 0.3V maximum on the pin (@ Isink = 10mA). This allows to omit the "bleeder" resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low. 2/9 L6385 RECOMMENDED OPERATING CONDITIONS Symbol Pin Vout 6 Output Voltage Note 1 580 V VbootVout 8 Floating Supply Voltage Note 1 17 V 2 Switching Frequency Supply Voltage 400 17 kHz V 125 °C fsw Vcc Parameter Test Condition Typ. HVG,LVG load CL = 1nF Junction Temperature Tj Min. -45 Max. Unit Note 1: If the condition Vboot - Vout < 18V is guaranteed, Vout can range from -3 to 580V. ELECTRICAL CHARACTERISTICS AC Operation (Vcc = 15V; Tj = 25°C) ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Symbol Pin Parameter Test Condition Min. Typ. Max. ton 1 vs 5 High/Low Side Driver Turn-On Propagation Delay Vout = 0V 110 Unit ns toff 2 vs 7 High/Low Side Driver Turn-Off Propagation Delay Vout = 600V 105 ns tr 7,5 Rise Time CL = 1000pF 50 ns tf 7,5 Fall Time CL = 1000pF 30 ns DC OPERATION (Vcc = 15V; Tj = 25°C) Symbol Pin Parameter Test Condition Min. Typ. Max. Unit Supply Voltage Vcc UV Turn On Threshold 9.1 9.6 17 10.1 V V Vccth2 Vcc UV Turn Off Threshold 7.9 8.3 8.8 V Vcchys Iqccu Vcc UV Hysteresis Undervoltage Quiescent Supply Current Vcc ≤ 9V 1.3 150 220 V µA Quiescent Current Bootstrap Driver on Resistance (*) Vcc = 15V Vcc ≥ 12.5V 250 125 Low Supply Voltage Section Vcc Vccth1 3 Iqcc Rdson 320 µA Ω 17 V 10.5 9.2 Bootstrapped supply Voltage Section VBS 8 VBSth1 VBSth2 VBShys IQBS Bootstrap Supply Voltage HVG ON 200 V V V µA ILK High Voltage Leakage Current High/Low Side Driver VS = VB = 600V 10 µA Iso 5,7 Isi Logic Inputs VIN = Vih (tp < 10µs) VIN = Vil (tp < 10µs) Vil Vih Iih Iil VBS UV Turn On Threshold VBS UV Turn Off Threshold VBS UV Hysteresis VBS Quiescent Current 2,3 Source Short Circuit Current Sink Short Circuit Current 8.5 7.2 300 450 9.5 8.2 1.3 400 650 Low Level Logic Threshold Voltage High Level Logic Threshold Voltage High Level Logic Input Current Low Level Logic Input Current (*) RDSON is tested in the following way: RDSON = mA mA 1.5 V 70 1 V µA µA 3.6 VIN = 15V VIN = 0V 50 (VCC − VCBOOT1) − (VCC − VCBOOT2) I1(VCC,VCBOOT1) − I2(VCC,VCBOOT2) where I1 is pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2. 3/9 L6385 Figure 1. Input/Output Timing Diagram HIN HVG LIN ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O LVG D99IN1053 Figure 2. Typical Rise and Fall Times vs. Load Capacitance time (nsec) D99IN1054 250 Figure 3. Quiescent Current vs. Supply Voltage Iq (µA) 104 D99IN1055 200 Tr 103 150 Tf 100 102 50 0 10 0 1 2 3 4 5 C (nF) For both high and low side buffers @25˚C Tamb BOOTSTRAP DRIVER A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (fig. 4a). In the L6385 a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in fig. 4b An internal charge pump (fig. 4b) provides the DMOS driving voltage . The diode connected in series to the DMOS has been added to avoid undesirable turn on of it. CBOOT selection and charging: To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. 4/9 0 2 4 6 8 10 12 14 16 VS(V) This capacitor CEXT is related to the MOS total gate charge : CEXT = Qgate Vgate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss . It has to be: CBOOT>>>CEXT e.g.: if Qgate is 30nC and Vgate is 10V, CEXT is 3nF. With CBOOT = 100nF the drop would be 300mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the L6385 leakage losses. e.g.: HVG steady state consumption is lower than 200µA, so if HVG TON is 5ms, CBOOT has to supply 1µC to CEXT. This charge on a 1µF capacitor means a voltage drop of 1V. The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. drop on the bootstrap DMOS: Vdrop = IchargeRdson → Vdrop = Qgate Rdson Tcharge where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about 1V, if the Tcharge is 5µs. In fact: ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 125 Ohm). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the Figure 4. Bootstrap Driver. Vdrop = 30nC ⋅ 125Ω ~ 0.8V 5µs Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used. DBOOT VS VBOOT VBOOT VS H.V. H.V. HVG HVG CBOOT VOUT CBOOT VOUT TO LOAD TO LOAD LVG LVG a D99IN1056 b Figure 6. Turn Off Time vs. Temperature Figure 5. Turn On Time vs. Temperature 250 250 @ Vcc = 15V 200 200 150 150 Toff (ns) Ton (ns) @ Vcc = 15V Typ. 100 50 Typ. 100 50 0 0 -45 -25 0 25 50 Tj (°C) 75 100 125 -45 -25 0 25 50 Tj (°C) 75 100 125 5/9 L6385 Figure 7. VBOOT UV Turn On Threshold vs. Temperature Figure 10. Vcc UV Turn Off Threshold vs. Temperature 11 13 @ Vcc = 15V 12 10 Typ. 10 Vccth2(V) Vbth1 (V) 11 9 8 7 9 Typ. 8 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 7 6 6 5 -45 -25 0 25 50 Tj (°C) 75 100 -45 125 75 100 125 @ Vcc = 15V @ Vcc = 15V 800 current (mA) 12 Vbth2 (V) 50 1000 13 11 10 9 8 600 Typ. 400 200 Typ. 7 0 6 -45 -25 0 25 50 75 100 -45 125 Figure 9. Vcc UV Turn On Threshold vs. Temperature -25 0 25 50 Tj (°C) 75 100 125 Figure 12. Output Sink Current vs. Temperature 13 1000 @ Vcc = 15V 12 800 11 current (mA) Vccth1(V) 25 Figure 11. Output Source Current vs. Temperature 14 10 Typ. 600 Typ. 400 200 8 0 7 -45 6/9 0 Tj (°C) Figure 8. VBOOT UV Turn Off Threshold vs. Temperature 9 -25 -25 0 25 50 Tj (°C) 75 100 125 -45 -25 0 25 50 Tj (°C) 75 100 125 L6385 mm inch DIM. MIN. A TYP. MAX. MIN. 3.32 TYP. MAX. OUTLINE AND MECHANICAL DATA 0.131 a1 0.51 0.020 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b Minidip e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O D E 10.92 7.95 9.75 0.430 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L Z 3.18 3.81 1.52 0.125 0.150 0.060 7/9 L6385 mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D (1) 4.80 5.00 0.189 0.197 E 3.80 4.00 0.15 0.157 OUTLINE AND MECHANICAL DATA ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b SO-8 e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O e 1.27 0.050 H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 k ddd Note: 0˚ (min.), 8˚ (max.) 0.10 0.004 (1) Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm (.006inch) in total (both side). 0016023 C 8/9 L6385 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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