E-L6386D

L6386 ® HIGH-VOLTAGE HIGH AND LOW SIDE DRIVER HIGH VOLTAGE RAIL UP TO 600V dV/dt IMMUNITY +- 50 V/nsec iN FULL TEMPERATURE RANGE DRIVER CURRENT CAPABILITY: 400 mA SOURCE, 650 mA SINK SWITCHING TIMES 50/30 nsec RISE/FALL WITH 1nF LOAD CMOS/TTL SCHMITT TRIGGER INPUTS WITH HYSTERESIS AND PULL DOWN UNDER VOLTAGE LOCK OUT ON LOWER AND UPPER DRIVING SECTION INTEGRATED BOOTSTRAP DIODE OUTPUTS IN PHASE WITH INPUTS DESCRIPTION The L6386 is an high-voltage device, manufactured with the BCD "OFF-LINE" technology. It has a Driver structure that enables to drive indeBLOCK DIAGRAM (s) BOOTSTRAP DRIVER VCC 4 HIN UV DETECTION o r P e 3 t e l o SD bs O LIN 2 ct du SO14 DIP14 ORDERING NUMBERS: L6386D c u d o r P pendent referenced Channel Power MOS or IGBT. The Upper (Floating) Section is enabled to work with voltage Rail up to 600V. The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices. e t le o s b O - Vboot 14 UV DETECTION H.V. HVG DRIVER R R LEVEL SHIFTER ) s t( L6386 CBOOT HVG 13 S OUT VCC LOGIC 12 TO LOAD LVG LVG DRIVER 9 PGND 8 1 VREF - 5 DIAG + SGND 7 6 CIN D97IN520D July 1999 1/10 L6386 ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Vout Output Voltage Parameter -3 to Vboot - 18 V Vcc Supply Voltage - 0.3 to +18 V Vboot Floating Supply Voltage -1 to 618 V Vhvg Vlvg Upper Gate Output Voltage Lower Gate Output Voltage - 1 to Vboot -0.3 to Vcc +0.3 V V Vi Vdiag Logic Input Voltage Open Drain Forced Voltage -0.3 to Vcc +0.3 -0.3 to Vcc +0.3 V V Vcin Comparator Input Voltage -0.3 to Vcc +0.3 V dVout/dt Allowed Output Slew Rate 50 V/ns Total Power Dissipation (Tj = 85 °C) Junction Temperature 750 150 mW °C -50 to 150 °C Ptot Tj Ts Storage Temperature Note: ESD immunity for pins 12, 13 and 14 is guaranteed up to 900V (Human Body Model) PIN CONNECTION LIN 1 14 Vboot SD 2 13 HVG HIN 3 12 OUT c u d e t le VCC 4 11 N.C. DIAG 5 10 N.C. CIN 6 9 LVG SGND 7 8 PGND o s b O - ) s t( o r P D97IN521A THERMAL DATA ) s ( ct Symbol Rth j-amb Parameter Thermal Resistance Junction to Ambient u d o PIN DESCRIPTION N. 1 2 3 4 5 6 7 8 9 10, 11 12 13 14 Name LIN SD (*) HIN VCC DIAG CIN SGND PGND LVG (*) N.C. OUT HVG (*) Vboot r P e t e l o s b O Type I I I I O I O O O SO14 DIP14 Unit 165 100 °C/W Function Lower Driver Logic Input Shut Down Logic Input Upper Driver Logic Input Low Voltage Supply Open Drain Diagnostic Output Comparator Input Ground Power Ground Low Side Driver Output Not Connected Upper Driver Floating Driver High Side Driver Output Bootstrapped Supply Voltage (*) The circuit guarantees 0.3V maximum on the pin (@ Isink = 10mA), with VCC >3V. This allows to omit the "bleeder" resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition. 2/10 L6386 RECOMMENDED OPERATING CONDITIONS Symbol Pin Vout 12 Output Voltage Note1 580 V VbootVout 14 Floating Supply Voltage Note1 17 V 4 Switching Frequency Supply Voltage 400 17 kHz V 125 °C fsw Vcc Parameter Test Condition Min. HVG,LVG load CL = 1nF Junction Temperature Tj Typ. -45 Max. Unit Note 1: if the condition Vboot - Vout < 18V is guaranteed, Vout can range from -3 to 580V. ELECTRICAL CHARACTERISTICS AC Operation (Vcc = 15V; Tj = 25°C) Symbol Pin ton 1.3 vs 9, 13 Parameter Typ. Max. Unit Vout = 0V Test Condition Min. 110 150 ns Vout = 0V 105 150 ns Vout = 0V 105 150 ns tsd 2 vs 9,13 High/Low Side Driver Turn-On Propagation Delay High/Low Side Driver Turn-Off Propagation Delay Shut Down to High/Low Side Propagation Delay tr 13,9 Rise Time CL = 1000pF 50 tf 13,9 Fall Time CL = 1000pF 30 toff c u d DC Operation (Vcc = 15V; Tj = 25°C) Symbol Pin Parameter Low Supply Voltage Section Vcc 4 Supply Voltage Vccth1 Vcc UV Turn On Threshold Vccth2 Vcc UV Turn Off Threshold Vcchys Vcc UV Hysteresis Iqccu Undervoltage Quiescent Supply Current Iqcc Quiescent Current Bootstrapped Supply Section Vboot 14 Bootstrapped Supply Voltage Vbth1 Vboot UV Turn On Threshold Vbth2 Vboot UV Turn Off Threshold Vbhys Vboot UV Hysteresis Iqboot Vboot Quiescent Current Ilk Leakage Current Rdson Bootstrap Driver on Resistance (*) Driving Buffers Section Iso 9, 13 High/Low Side Driver Short Circuit Source Current Isi High/Low Side Driver Short Circuit Sink Current Logic Inputs Vil 1,2,3 Low Level Logic Threshold Voltage Vih High Level Logic Threshold Voltage Iih High Level Logic Input Current Iil Low Level Logic Input Current (s) e t le Test Condition o s b O - r P e t e l o s b O (*) RDSON is tested in the following way: RDSON = Min. Typ. 11.5 9.5 12 10 2 200 250 Vcc ≤ 11V Vcc = 15V ct u d o o r P ns Max. Unit 17 12.5 10.5 V V V V µA µA 320 125 300 400 mA 500 650 mA Vout = Vboot Vout = Vboot = 600V Vcc ≥ 12.5V; Vin = 0V 11.9 9.9 2 17 12.9 10.7 200 10 1.5 3.6 VIN = 15V VIN = 0V ns V V V V µA µA Ω 10.7 8.8 VIN = Vih (tp < 10µs) ) s t( 50 70 1 V V µA µA (VCC − VCBOOT1) − (VCC − VCBOOT2) I1(VCC,VCBOOT1) − I2(VCC,VCBOOT2) where I1 is pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2. 3/10 L6386 DC OPERATION (continued) Symbol Pin Parameter Test Condition Min. Typ. Max. Unit 10 mV Sense Comparator Vio Input Offset Voltage -10 Vcin ≥ 0.5 Iio 6 Input Bias Current Vol 2 Open Drain Low Level Output Voltage, Iod = -2.5mA Vref µA 0.2 Comparator Reference voltage 0.460 0.5 0.8 V 0.540 V Figure 1. Timing Waveforms HIN LIN SD c u d HOUT LOUT e t le VREF VCIN DIAG ) s ( ct ) s t( o r P o s b O - D97IN522A Note: SD active condition is latched until next negative IN edge. u d o Figure 2. Typical Rise and Fall Times vs. Load Capacitance Figure 3. Quiescent Current vs. Supply Voltage time (nsec) Iq (µA) 104 250 D99IN1054 t e l o s b O 200 r P e Tr D99IN1057 103 150 Tf 100 102 50 0 4/10 10 0 1 2 3 4 5 C (nF) For both high and low side buffers @25˚C Tamb 0 2 4 6 8 10 12 14 16 VS(V) L6386 BOOTSTRAP DRIVER A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (fig. 4a). In the L6386 a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in fig. 4b An internal charge pump (fig. 4b) provides the DMOS driving voltage . The diode connected in series to the DMOS has been added to avoid undesirable turn on of it. CBOOT selection and charging: To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge : CEXT = supply 1µC to CEXT. This charge on a 1µF capacitor means a voltage drop of 1V. The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 125 Ohm). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS: Vdrop = IchargeRdson → Vdrop = Qgate Vgate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss . It has to be: CBOOT>>>CEXT ) s ( ct d o r u d o r P e Qgate Tcharge Rdson where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about 1V, if the Tcharge is 5µs. In fact: P e let o s b O - e.g.: if Qgate is 30nC and Vgate is 10V, CEXT is 3nF. With CBOOT = 100nF the drop would be 300mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage losses. e.g.: HVG steady state consumption is lower than 200µA, so if HVG TON is 5ms, CBOOT has to uc ) s t( Vdrop = 30nC ⋅ 125Ω ~ 0.8V 5µs Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used. Figure 4. Bootstrap Driver. s b O t e l o DBOOT VS VBOOT VBOOT VS H.V. H.V. HVG HVG CBOOT VOUT VOUT TO LOAD TO LOAD LVG a CBOOT LVG b D99IN1056 5/10 L6386 Figure 5. Turn On Time vs. Temperature Figure 8. VBOOT UV Turn On Threshold vs. Temperature 15 250 @ Vcc = 15V 13 Vbth1 (V) Ton (ns) @ Vcc = 15V 14 200 150 Typ. 100 12 Typ. 11 10 9 50 8 0 7 -45 -25 0 25 50 Tj (°C) 75 100 125 Figure 6. Turn Off Time vs. Temperature -45 @ Vcc = 15V 14 Vbth2 (V) Toff (ns) 13 150 Typ. 100 75 100 125 ) s t( e t le 12 o r P @ Vcc = 15V o s b O 11 Typ. 10 9 50 ) s ( ct 0 -45 -25 0 25 50 Tj (°C) 75 100 r P e Figure 7. Shutdown Time vs. Temperature t e l o 250 -45 -25 0 25 50 Tj (°C) 75 100 125 3 @ Vcc = 15V @ Vcc = 15V Vbhys (V) 2.5 150 100 7 Figure 10. VBOOT UV Hysteresis bs 200 8 125 u d o tsd (ns0 25 50 Tj (°C) c u d 15 200 Typ. 2 Typ. 1.5 50 0 1 -45 6/10 0 Figure 9. VBOOT UV Turn Off Threshold vs. Temperature 250 O -25 -25 0 25 50 Tj (°C) 75 100 125 -45 -25 0 25 50 Tj (°C) 75 100 125 L6386 Figure 11. Vcc UV Turn On Threshold vs. Temperature Figure 14. Output Source Current vs. Temperature 15 1000 14 800 13 current (mA) Vccth1(V) @ Vcc = 15V Typ. 12 11 Typ. 400 200 10 9 0 -45 -25 0 25 50 Tj (°C) 75 100 125 Figure 12. Vcc UV Turn Off Threshold vs. Temperature -45 -25 0 25 50 Tj (°C) 75 c u d 100 125 ) s t( Figure 15. Output Sink Current vs. Temperature 12 1000 11 800 current (mA) Vccth2(V) 600 10 Typ. 9 Typ. e t le 600 o r P @ Vcc = 15V o s b O 400 200 8 7 -45 -25 0 25 50 ) s ( ct 75 u d o Tj (°C) 100 125 0 -45 -25 0 25 50 Tj (°C) 75 100 125 r P e Figure 13. Vcc UV Hysteresis vs. Temperature t e l o 3 s b O Vcchys (V) 2.5 Typ. 2 1.5 1 -45 -25 0 25 50 Tj (°C) 75 100 125 7/10 L6386 mm DIM. MIN. a1 0.51 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 F 7.1 0.280 I 5.1 0.201 L 3.3 Z 1.27 2.54 0.050 r P e 8/10 o r P DIP14 e let 0.100 u d o t e l o c u d 0.130 ) s ( ct s b O OUTLINE AND MECHANICAL DATA o s b O - ) s t( L6386 mm DIM. MIN.. TYP. A inch MAX.. MIN.. TYP.. MAX.. a1 1.75 0.1 0.069 0.25 a2 0.004 0.009 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 c1 OUTLINE AND MECHANICAL DATA 0.020 45˚ (typ.) D (1) 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 F (1) 3.8 4 0.150 0.157 G L 4.6 5.3 0.181 0.209 0.4 1.27 0.016 0.050 M 0.68 0.027 e t le (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). ) s ( ct o r P SO14 8˚ (max.) S c u d ) s t( o s b O - u d o r P e t e l o s b O 9/10 L6386 c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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