E-L9826

L9826 Octal protected low-side driver with diagnostic and serial/parallel input control Features ■ 8 channels low side driver with 450 mA output current capability ■ Typical RDSON 1.5  at TJ = 25 °C ■ Parallel control for output 1 and 2 ■ SPI control on all outputs ■ Reset function ■ Diagnostic through 8 bit SPI ■ Intrinsic output voltage clamping 50 V (Typ) protection for inductive load drive ■ Short circuit current limitation and thermal shutdown for outputs 1 and 2 ■ Overcurrent and short circuit shutdown for outputs 3 to 8 '!0'03 SO20 The 8 -bit serial peripheral interface (SPI) is able to control the device's eight channels and to provide its load's diagnosis. In addition output 1 and 2 can also be controlled through dedicated input pins NON1 and NON2. Description The L9826 is a protected octal low-side driver IC designed for the automotive environment. Table 1. Overcurrent and short-circuit protections are present as well as the output voltage clamping which is able to protect the L9826 during operation with inductive loads. Device summary Order code Package Packing L9826 SO20 Tube L9826TR SO20 Tape and reel E-L9826 SO20 Tube E-L9826TR SO20 Tape and reel September 2013 Doc ID 7214 Rev 10 1/19 www.st.com 1 Contents L9826 Contents 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 Output stage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 5.4 5.2.1 Via parallel, only for output 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2.2 Via 8-bit SPI for all the outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output stage diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3.1 Diagnostic on Outputs 1 and 2 controlled via NON1/NON2 . . . . . . . . . 15 5.3.2 Diagnostic on Outputs 1 to 8 controlled via SPI . . . . . . . . . . . . . . . . . . 15 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4.1 Flyback current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4.2 Current regulation mode outputs 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . 16 5.4.3 Short circuits outputs 3 to 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 Doc ID 7214 Rev 10 L9826 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings for voltages and currents applied externally to the device. . . . . 7 Absolute maximum ratings for currents determined within the device . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Outputs control tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Diagnostic table for outputs 1 and 2 in parallel controlled mode . . . . . . . . . . . . . . . . . . . . 15 Diagnostic table for outputs 1 to 8 in SPI controlled mode . . . . . . . . . . . . . . . . . . . . . . . . . 15 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Doc ID 7214 Rev 10 3/19 List of figures L9826 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. 4/19 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Typical application circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Parallel control for output 1 and 2 (Example for Power-on) . . . . . . . . . . . . . . . . . . . . . . . . 12 Output control register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Timing of the serial interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 The pulse diagram to read the outputs status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 The structure of the outputs status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SO20 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Doc ID 7214 Rev 10 L9826 Block Diagram Figure 1.Block diagram 6## 6## ./. /54   3  )/, ,ATCH$RIVER 1 2 /VERTEMPERATURE$ETECTION  &AULT,ATCH $IAG 6$' #( ./. 6## #,+ 6## 3$) #( /UTPUT,ATCH .#3 1 $IAG 30) )NTERFACE 6## 3HIFT2EGISTER 1 Block Diagram 6## 3$/ /54 1 1 1 1 1 1 1 1 6## 2ESET 1 3 ,ATCH$RIVER $IAG $IAG $IAG $IAG $IAG 1 $IAG $IAG $IAG $IAG 1 $IAG $IAG '.$ .2%3 /54 2ESET 5NDERVOLTAGE 2%3%4 )/, 2  6$' #( #( #( 1 $IAG #( 1 $IAG #( 1 $IAG #( /54 /54 /54 /54 /54 '.$ '!0'03 Doc ID 7214 Rev 10 5/19 Pins description 2 L9826 Pins description Figure 2. Connection diagram (top view) /54   /54 /54   /54 N2%3   6CC .#3   ./. '.$   '.$ '.$   '.$ ./.   #,+ 3$/   3$) /54   /54 /54   /54 '!0'03 Table 2. 6/19 Pin description N° Pin Description 1 Out 6 Output 6 2 Out 1 Output 1 3 NRes Asynchronous reset 4 NCS Chip select (active low) 5 GND Device ground 6 GND Device ground 7 NON1 Control input 1 8 SDO Serial data output 9 Out 8 Output 8 10 Out 3 Output 3 11 Out 5 Output 5 12 Out 2 Output 2 13 SDI Serial data input 14 CLK Serial clock 15 GND Device ground 16 GND Device ground 17 NON2 Control input 2 18 VCC Supply voltage 19 Out 7 Output 7 20 Out 4 Output 4 Doc ID 7214 Rev 10 L9826 Electrical specifications 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings for voltages and currents applied externally to the device Symbol VCC Parameter Test condition Supply voltage Min. Typ. Max. Unit -0.3 - 7 V -0.3 - 7 V T  1ms -20 - 20 mA - -0.7 - 45 V - -2 - 1.0 A IOUT  150mA - - 10 mJ - Inputs and data lines (NONx, NCS, CLK, SDI, nRes) VIN IIN Voltage (NONx, NCS, CLK, SDI, nRes) Protection diodes current(1) Outputs (Out1 ... Out8) VOUTc IOUT EOUTcl Continuous output voltage Output current (2) Output clamp energy 1. All inputs are protected against ESD according to MIL 883C; tested with HBM at 2 kV. It corresponds to a dissipated energy E  0.2 mJ. 2. Transient pulses in accordance to DIN40839 part 1, 3 and ISO 7637 Part 1, 3. Table 4. Absolute maximum ratings for currents determined within the device Symbol Parameter Test condition Min. Typ. Max. Unit Outputs (Out1 ... Out8) IOUT IOUT1 i = 1-8 Output current (Out1, Out2) - - - ILIM A Output current (Out3 ... Out8) - - - ISCB A Total average-current all outputs (1) Tamb = 60°C 2.0 - - A 1. When operating the device with short circuit 1ch and 2ch outputs at the same time, damage due to electrical overstress might occur. 3.2 Thermal data Table 5. Thermal data Symbol Parameter Test condition Min. Typ. Max. Unit - 150 165 - °C Thermal shutdown TJSC Thermal shutdown threshold Thermal resistance Rthj a-one Single output (junction ambient) - - - 90 °C/W Rthj a-all All outputs (junction ambient) - - - 75 °C/W Rth j-pin Junction to Pin - - - 18 °C/W Doc ID 7214 Rev 10 7/19 Electrical specifications 3.3 L9826 Electrical characteristics Refer to 4.5 V  VCC  5.5 V; -40 °C  TJ 150 °C; unless otherwise specified. Table 6. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit Supply voltage IccSTB IccOPM ICC Standby current without load (nRes = Low) - - 70 A Operating mode IOUT1 ... 8 = 500 mA SPI - CLK = 3 MHz NCS = LOW SDO no load - - 5 mA ICC during reverse output current Iout = -2 A - - 100 mA Reset of all registers and disable of all outputs 3 - 4 V VDDRES Undervoltage reset Inputs (NONx. NCS, CLK, SDI, nRES) VINL Low level - -0.3 - 0.2·VCC V VINH High level - 0.7·VCC - VCC +0,3 V Vhyst Hysteresis voltage - 0.85 - - V - - 10 A Input current NONx, NCS, CLK, SDI VIN = VCC NRES (VIN = 0V) -10 - - A 50 - 250 k - - 10 pF VCC -0.4 - - V - 0.4 V -10 - 10 A IIN RIN Pull-up resistance (NONx, NCS, CLK, SDI) Pull-down resistance (NRes) CIN Input capacitance Guaranteed by design Serial data outputs VSDOH High output level ISDO = -4mA VSDOL Low output level ISDO = 3,2mA ISDOL Tristate leakage current NCS = high; 0V  VSDO  VCC CSDO Output capacitance fSDO = 300 kHz, Guaranteed by design - - 10 pF OUTx = OFF; VOUTx = 25 V; VCC = 5 V - - 100 A OUTx = OFF; VOUTx = 16 V; VCC = 5 V - - 100 A OUTx = OFF; VOUTx = 16 V; VCC = 1 V - - 10 A Outputs OUT 1 ... 8 IOUTL1 - 8 Leakage current 8/19 Doc ID 7214 Rev 10 L9826 Electrical specifications Table 6. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit Output clamp voltage 1 mA  Iclp  Ioutp; Itest = 10 mA with correlation 45 - 62 V RDSon On resistance OUT 1 ... 8 IOUT = 250 mA; Tj = +150 °C - - 3.0  COUT Output capacitance VOUT = 16 V; f = 1 MHz guaranteed by design - - 300 pF Vclp Outputs short circuit protection ISBC Overcurrent shutoff threshold OUT3 ... OUT8 0.45 - 1.1 A ILIM Short circuit current limitation OUT1; OUT2 0.5 - 1.1 A tSCB Delay shutdown - 0.2 3,0 12 s 0.32 ·VCC - 0.4·VCC V Diagnostics VDG Diagnostic threshold voltage - IOL Open load detection sink current Vout = VDG 20 - 100 A tdf Diagnostic detection filter time for output 1 & 2 on each diagnostic condition 15 - 50 s - - 5 s Outputs timing tdon1 NON1, 2 = 50% to VOUT = 0,9·Vbat Turn ON delay of OUT 1 and 2 NCS = 50% to VOUT = 0,9·Vbat (VBAT = 16V, RL = 500) tdon2 Turn ON delay of OUT 3 to 8 NCS = 50% to VOUT = 0,9·Vbat (VBAT = 16V, RL = 500) - - 10 s Turn OFF delay of OUT 1 to 8 NCS = 50% to VOUT = 0,1·Vbat NON1, 2 = 50% to VOUT = 0,1·Vbat (VBAT = 16V, RL = 500) - - 10 s dUon1/dt Turn ON voltage slew-rate For output 3 to 8; 90% to 30% of Vbat; RL = 500; Vbat = 16V 0.7 - 3.5 V/s dUon2/dt Turn ON voltage slew-rate For output 1 and 2; 90% to 30% of Vbat; RL = 500; Vbat = 16V 2 - 10 V/s dUoff1/dt Turn OFF voltage slew-rate For output 1 to 8; 30% to 90% of Vbat; RL = 500; Vbat = 16V 2 - 10 V/s dUoff2/dt Turn OFF voltage slew-rate For output 1 to 8; 30% to 80% of Vbat; RL = 500; Vbat = 0.9 · Vclp 2 - 15 V/s - - 3 MHz tdoff Serial diagnostic link (load capacitor at SDO = 100 pF) fclk Clock frequency 50 % duty cycle tclh Minimum time CLK = high - 160 - - ns tcll Minimum time CLK = low - 160 - - ns - - 100 ns tpcld Propagation delay CLK to data 4.9 V  VCC  5.1V at SDO valid Doc ID 7214 Rev 10 9/19 Electrical specifications Table 6. Symbol L9826 Electrical characteristics (continued) Parameter Test condition Min. Typ. Max. Unit - - 100 ns tcsdv NCS = LOW to data at SDO active - tsclch CLK low before NCS low Setup time CLK to NCS change H/L 100 - - ns thclcl CLK change L/H after NCS = low - 100 - - ns tscld SDI input setup time CLK change H/L after SDI data valid 20 - - ns thcld SDI input hold time SDI data hold after CLK change H/L - - 20 ns tsclcl CLK low before NCS high - 150 - - ns thclch CLK high after NCS high - 150 - - ns tpchdz NCS L/H to output data float - - - 100 ns NCS pulse filter time Multiple of 8 CLK cycles inside NCS period - - - - - 10/19 Doc ID 7214 Rev 10 L9826 Application information 4 Application information The typical application diagram is shown in Figure 3. Figure 3. Typical application circuit diagram 6## 6/,4!'% 2%'5,!4/2 6"!4 6## /54 6## ./.   3  )/, ,ATCH$RIVER 1 2 /VERTEMPERATURE$ETECTION  &AULT,ATCH $IAG 6$' #( ./. #,+ 6## 3$) 1 1 1 1 1 1 1 1 6## 2ESET 2ESET 5NDERVOLTAGE 2%3%4 3 ,ATCH$RIVER )/, 2  6$' #( #( #( 1 $IAG #( 1 $IAG #( 1 $IAG #( /54 /54 /54 /54 /54 2,LOADS '.$ .2%3 3$) 3$/ #,/#+ , .#3 1 $IAG $IAG $IAG $IAG $IAG 1 $IAG $IAG $IAG $IAG 1 $IAG $IAG '.$ N2%3 /54 /54 6## 3$/ —0 #( /UTPUT,ATCH 6## 30) )NTERFACE .#3 1 $IAG 3HIFT2EGISTER 6## , '!0'03 For higher current capability the two outputs of the same kind can be paralleled and the maximum flyback energy should not exceed the limit for a single output. The circuit immunity at output transients have been verified during the characterization with Test Pulses 1, 2, 3a and 3b, DIN40839 or ISO7637 part 3. The Test Pulses are coupled to the outputs with 200 pF series capacitor and all the outputs are able to withstand to test pulses without damage. The load applied was in the range of 30 to 100 ohm for the resistive part and 0 to 600 mH for the inductive one. Doc ID 7214 Rev 10 11/19 Functional description L9826 5 Functional description 5.1 General The L9826 is an 8-channel low-side driver assembled in SO20 package. Its 8-bit SPI serial interface is designed to control all the outputs and to provide their diagnosis. Channels 1 and 2 are controlled either via SPI or via parallel through the inputs pins NON1 and NON2. Diagnostic recognizes operative fault conditions: open load, short circuits to GND or to VB and overcurrent.Thermal shutdown for outputs 1 and 2 is available as well the output voltage clamp which is essential in case of working with inductive loads. The reset feature is an OR function of the external reset nRes and the internal reset generate during the undervoltage condition 5.2 Output stage control 5.2.1 Via parallel, only for output 1 and 2 This is valid only for Outputs 1 and 2 which are controlled through the dedicated inputs NON1 and NON2 (both active low) which are internally configured as pull-up (see Figure 3). This is to guarantee that the outputs are off in case of inputs open. A further feature is the possibility to drive these outputs through a PWM signal independently by SPI commands. Reset signal is common for all the eight channels and it is active low. After an external reset condition (that means NRES pin switched from low to high) to drive outputs 1 and 2 through the parallel input (NON1 and NON2) it is necessary to disable the parallel input itself (NON1, NON2 high) and then subsequently to drive the outputs 1 and 2 at the logic state desiderated through NON1 and NON2. The duration of the command (T) as reported in the Figure 4 should be at less in the order of 100 nSecond. In the next Figure 4 is shown this behavior and in the next Table 7 is summarized the scenario of parallel/series commands. Figure 4. Parallel control for output 1 and 2 (Example for Power-on) 2ESETOFF 2ESETON .2%3 4 !NYVALUES ./.OR ON /54OR Table 7. '!0'03 Outputs control tables Outputs 1, 2: 12/19 Outputs 3 to 8: NON1, 2 1 0 0 1 - - - SPI-bit 1, 2 0 0 1 1 SPI-bit 3 ... 8 0 1 Output 1, 2 off on on on Output 3 ... 8 off on Doc ID 7214 Rev 10 L9826 5.2.2 Functional description Via 8-bit SPI for all the outputs Control data are transmitted to SDI through a microcontroller in configuration master. The device is selected when NCS signal is low. The 8-bit command data are transmitted into L9826 shift registers every CLK falling edge (see Figure 6 for SPI signals timing). The NCS rising edge latches the new data from the shift register to the driver and the output are driven following the commands just sent. The digital filter between NCS and the output latch ensures that the data are transferred only after 8 CLK cycles or multiple of 8 CLK cycles since the last NCS falling edge. The NCS changes only at low CLK. Figure 5 shows the control register structure and in the detail its control-bit, while in the Table 7 are summarized the controls outputs via SPI or dedicated input pins (NON1 and NON2). Figure 5. Output control register structure -3" ,3" 1 1 1 1 1 1 1 1 #ONTROL BITOUTPUT #ONTROL BITOUTPUT #ONTROL BITOUTPUT #ONTROL BITOUTPUT #ONTROL BITOUTPUT #ONTROL BITOUTPUT #ONTROL BITOUTPUT #ONTROL BITOUTPUT '!0'03 Figure 6. Timing of the serial interface .#3 TSCLCH THCLCL TCLH TCLL TSCLCL THCLCH #,+ TCSDV 3$/ TPCLD NOTDEFINED TSCLD 3$) TPCHDZ $ $ THCLD $ $ $ '!0'03 Doc ID 7214 Rev 10 13/19 Functional description 5.3 L9826 Output stage diagnostics All the outputs voltage are compared with the diagnostic threshold (0.38 Typ · VCC) and this information is transferred in dedicated fault latches which are cleared when the NCS reaches the state low. Afterward the latch stores the status bit and the first reading after the error might be wrong. The second one is considered right. The next Figure 7 and 8 show the diagnostic bits read out on SDO and their organization into the dedicated registers. When NCS is low the data contained in the shift register are transferred to SDO output every CLK rising edge. Figure 7. The pulse diagram to read the outputs status register .#3 #,+ 3$/ 3$) -3"  -3"           ,3"  ,3" '!0'03 Figure 8. The structure of the outputs status register -3" ,3" $IAG $IAG $IAG $IAG $IAG $IAG $IAG $IAG $IAGNOSTIC BITOUTPUT $IAGNOSTIC BITOUTPUT $IAGNOSTIC BITOUTPUT $IAGNOSTIC BITOUTPUT $IAGNOSTIC BITOUTPUT $IAGNOSTIC BITOUTPUT $IAGNOSTIC BITOUTPUT $IAGNOSTIC BITOUTPUT '!0'03 14/19 Doc ID 7214 Rev 10 L9826 5.3.1 Functional description Diagnostic on Outputs 1 and 2 controlled via NON1/NON2 Fault condition (1) "output shorted to Vbat" The output has been previously switched-on and its voltage exceeds the diagnostics threshold. It operates in current regulation mode or it is switched-off if thermal shutdown threshold (TJSC) is reached. The status bit is low. Fault condition (2) "open load" or "output shorted to GND" The output is switched-off and its voltage drops below the diagnostics threshold because the load current is lower than the output diagnostic current source. The diagnostic bit is low. Table 8. 5.3.2 Diagnostic table for outputs 1 and 2 in parallel controlled mode Output 1, 2 Output-voltage Status-bit Output-mode off > DG-threshold high correct operation off < DG-threshold low fault condition 2) on < DG-threshold high correct operation on > DG-threshold low fault condition 1) Diagnostic on Outputs 1 to 8 controlled via SPI Fault condition (1) "output shorted to Vbat" The output was previously switched-on, its voltage exceeds the diagnostic threshold and the result is that the output is switched-off. The diagnostic bit is high. Fault condition (2) "open load" or "output shorted to GND" It is the same behavior explained for the outputs 1 and 2 (see paragraph 5.3.1), at NCS falling edge the output status data are transferred to the shift register. Table 9. Diagnostic table for outputs 1 to 8 in SPI controlled mode Output 1 ... 8 Output-voltage Status-bit Output-mode off > DG-threshold high correct operation off < DG-threshold low fault condition 2) on < DG-threshold low correct operation on > DG-threshold high fault condition 1) Load diagnostic: when the output is in OFF condition a typical diagnostic current of 60 µA is sinked. Doc ID 7214 Rev 10 15/19 Functional description 5.4 Protections 5.4.1 Flyback current L9826 Turning off the low side driver with an inductive load, its output voltage rises due to the inductor that tries to drive current. This voltage is internally clamped by the flyback circuit at VCPL value, typical 50V 5.4.2 Current regulation mode outputs 1 and 2 Outputs 1 and 2 which are particularly dedicated for loads with inrush current (as lamps). When the channel is switched on and the current through the load exceeds the short circuit limit value (Ilim) for at least tdf time, the corresponding output goes in current regulation mode. The output current is determinated by the output characteristic and its voltage depends on load resistance. In this mode, high power is dissipated in the output stage and its temperature increases rapidly. When the output stage temperature exceeds the thermal shutdown (TJSC), the overload latch is set and the corresponding output is switched off. 5.4.3 Short circuits outputs 3 to 8 Outputs 3 to 8 which are dedicated for loads without inrush currents. When the output current exceeds the short circuit threshold (Isbc) for at least Tscb time, the corresponding output is switched-off immediately and in the same time, the relative latch store the overload status. 16/19 Doc ID 7214 Rev 10 L9826 6 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 9. SO20 mechanical data and package dimensions MM INCH $)- -). 490 -!8 -). 490 -!8 !     !     "     #     $     %     E   (     H     ,     K DDD /54,).%!.$ -%#(!.)#!,$!4! ƒPLQƒPD[    h$vDIMENSIONDOESNOTINCLUDEMOLDFLASHPROTUSIONSORGATE BURRS-OLDFLASHPROTUSIONSORGATEBURRSSHALLNOTEXCEED MMPERSIDE 3/ $ '!0'03 Doc ID 7214 Rev 10 17/19 Revision history 7 L9826 Revision history Table 10. 18/19 Document revision history Date Revision Changes 22-Apr-2004 7 Initial release in EDOCS 26-Jul-2005 8 Document reformatted. Modify value RON in the “Features”. 08-Feb-2011 9 Updated Features and Description on page 1. Updated Table 1: Device summary on page 1. Updated Figure 3: Typical application circuit diagram. Reworked the content of the Section 5: Functional description. 19-Sep-2013 10 Updated Disclaimer. Doc ID 7214 Rev 10 L9826 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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