E-ST7538P

ST7538 FSK POWER LINE TRANSCEIVER 1 Figure 1. Package FEATURES HALF DUPLEX FREQUENCY SHIFT KEYING (FSK) TRANSCEIVER INTEGRATED POWER LINE DRIVER WITH PROGRAMMABLE VOLTAGE AND CURRENT CONTROL PROGRAMMABLE INTERFACE: – SYNCHRONOUS – ASYNCHRONOUS SINGLE SUPPLY VOLTAGE (FROM 7.5 UP TO 12.5V) VERY LOW POWER CONSUMPTION (Iq=5 mA) INTEGRATED 5V VOLTAGE REGULATOR (UP TO 100mA) WITH SHORT CIRCUIT PROTECTION 8 PROGRAMMABLE TRANSMISSION FREQUENCIES PROGRAMMABLE BAUD RATE UP TO 4800BPS RECEIVING SENSITIVITY 250µVRMS SUITABLE TO APPLICATION IN ACCORDANCE WITH EN 50065 CENELEC SPECIFICATIONS CARRIER OR PREAMBLE DETECTION BAND IN USE DETECTION PROGRAMMABLE REGISTER WITH SECURITY CHECKSUM MAINS ZERO CROSSING DETECTION AND SYNCHRONIZATION ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ) s ( ct ■ ■ Figure 2. Block Diagram r P e u d o DVdd AVdd t e l o AVss Table 1. Order Codes ■ Part Number Package ST7538P TQFP44 (Slug down) c u d WATCHDOG TIMER 2 DESCRIPTION ) s t( o r P The ST7538 is a Half Duplex synchronous/asynchronous FSK Modem designed for power line communication network applications. It operates from a single supply voltage and integrates a line driver and a 5V linear regulator. The device operation is controlled by means of an internal register, programmable through the synchronous serial interface. Additional functions as watchdog, clock output, output voltage and current control, preamble detection, time-out, band in use are included. Realized in Multipower BCD5 technology that allows to integrate DMOS, Bipolar and CMOS structures in the same chip. e t le o s b O TEST1 TEST2 TEST3 BU TEST BU CARRIER DETECTION CD/PD RxFo AGC RxD bs O DVss TQFP44 Slug Down DIGITAL FILTER PLL CLR/T FSK DEMOD IF FILTER FILTER AMPL RAI SERIAL INTERFACE FILTER CONTROL REGISTER REG/DATA CURRENT CONTROL CL VOLTAGE CONTROL Vsense RxTx FSK MODULATOR TxD DAC TX FILTER ALC ATO PLI REGOK TIME BASE OSC OP-AMP ZC ATOP1 ATOP2 + PAVcc VREG - Vdc PG XOut November 2005 XIn WD TOUT RSTO MCLK ZCout ZCin C_OUT CMINUS CPLUS D03IN1407A Rev. 5 1/30 ST7538 N.C. REG_DATA PG GND C_OUT N.C. C_PLUS C_MINUS REG_OK TEST1 N.C. Figure 3. Pin Connection (Top view) 44 43 42 41 40 39 38 37 36 35 34 TEST2 TXD 5 29 VSENSE GND 6 28 AVDD TOUT 7 27 XIN CLR/T 8 26 XOUT BU 9 25 SGND DVDD 10 24 ATO MCLK 11 23 CL 12 13 14 15 16 17 18 19 20 21 22 PAVCC 30 ATOP2 4 PAVSS RXFO RxTx ATOP1 31 DVSS 3 N.C. RAI RXD ZCIN 32 ZCOUT VDC 2 WD 33 DVSS RSTO 1 TEST3 CD_PD e t le Table 2. Pin Description N° Name Type 1 CD_PD 2 DVss Supply 3 RxD Digital/Output 4 RxTx Digital/Input with internal pull-up 5 TxD Digital/Output o r P e o s b O - o r P Description Carrier or Preamble Detect Output. "1" No Carrier or Preamble Detected "0" Carrier or Preamble Detected (t s) Digital Ground c u d RX Data Output. Rx or Tx mode selection input. "1" - RX Session "0" - TX Session Digital/Input with internal pull-down TX Data Input. t e l o Supply Substrate Ground (same function as PIN 41) Digital/Output TX Time Out Event Detection "1" - Time Out Event Occurred "0" - No Time-out Event Occurred 8 CLR/T Digital/Output Synchronous Mains Access Clock or Control Register Access Clock 9 BU Digital/Output Band in use Output. "1" Signal within the Programmed Band "0" No Signal within the Programmed Band 6 7 s b O GND TOUT 10 DVdd Supply Digital Supply Voltage 11 MCLK Digital/Output Master Clock Output 12 RSTO Digital/Output Power On or Watchdog Reset Output 2/30 c u d D01IN1312 ) s t( ST7538 Table 2. Pin Description (continued) N° Name Type 13 TEST 3 Digital/Input with internal pull-down Test Input. Must be connected to DVss during Normal Operation 14 WD Digital/Input with internal pull-up Watchdog input. The Internal Watchdog Counter is cleared on the falling edges. 15 ZCOUT Digital/Output Zero Crossing Detection Output 16 ZCIN1 Analog/Input Zero Crossing AC Input. 17 NC Floating Must be connected to DVss. 18 DVss 19 ATOP1 Supply Digital Ground Power/Output Power Line Driver Output 20 PAVss Supply Power Analog Ground 21 ATOP2 Power/Output Power Line Driver Output 22 PAVCC Supply Power Supply Voltage Analog/Input Current Limiting Feedback. A resistor between CL and AVss sets the PLI Current Limiting Value Analog/Output Small Signal Analog Transmit Output 23 CL 24 ATO 25 SGND Supply Analog Signal Ground 26 XOUT Analog I/O Crystal Output- External Clock Input 27 XIN Analog Input Crystal Oscillator Input 28 AVdd Supply Analog Power supply. Analog/Input Output Voltage Sensing input for the voltage control loop 2 Vsense 30 TEST2 Analog/Input Test Input must be connected SGND 31 RxFO Analog/Output Receiving Filter Output 32 RAI Analog/Input Receiving Analog Input 33 VDC Power 5V Voltage Regulator Output 34 NC floating 35 TEST1 Digital/Input with internal pull-down Test input. Must Be connected to DVss. 36 REGOK Digital/Output Security checksum logic output "1" - Stored data Corrupted "0" - Stored data OK 3 38 C_PLUS 5 NC 41 43 44 r P e t e l o bs 42 GND PG ) s ( ct u d o C_MINUS4 Analog/Input C_OUT Analog/Input Op-amp Inverting Input. Op-amp Not Inverting Input. floating Must Be connected to DVss Analog/Output Op-amp Output Supply Substrate Ground (same function as PIN 6) Digital/Output Power Good logic Output "1" - VDC is above 4.5V "0" - VDC is below 4.25V REG_DATA Digital/Input with internal pull-down NC o s b O - Must Be connected to DVss. 37 40 e t le floating c u d ) s t( o r P 29 39 O Description Mains or Control Register Access Selector "1" - Control Register Access "0" - Mains Access Must be connected to DVss. If not used this pin must be connected to VDC Cannot be left floating Cannot be left floating If not used this pin must be connected to VDC If not used this pin must be tied low (SGND or PAVss or DVss) 3/30 ST7538 Table 3. Absolute Maximum Ratings Symbol Value Unit PAVCC Power Supply Voltage -0.3 to +14 V AVdd Analog Supply Voltage -0.3 to +5.5 V DVdd Digital Supply Voltage -0.3 to +5.5 V AVss/DVss Parameter -0.3 to +0.3 V Digital input Voltage DVss - 0.3 to DVdd +0.3 V VO Digital output Voltage DVss - 0.3 to DVdd +0.3 V IO Digital Output Current VI Voltage between AVss and DVss -2 to +2 mA AVss - 0.3 to AVdd+0.3 V Voltage Range at RAI, ZCIN Inputs -AVdd - 0.3 to AVdd +0.3 V ATO, RxFO, C_OUT, XOUT Voltage range at ATO, RxFO, C_OUT, XOUT Outputs AVss - 0.3 to AVdd +0.3 ATOP1,2 Voltage range at Powered ATO Output Vsense, XIN, C_MINUS, C_PLUS, CL Voltage Range at Vsense, XIN, C_MINUS, C_PLUS, CL Inputs RAI, ZCIN ATOP Powered ATO Output Current (*) Tamb Operating ambient Temperature Tstg Storage Temperature ATOP1 Pin ATOP2 Pin Other pins Maximum Withstanding Voltage Range Test Condition: CDF-AEC-Q100-002- “Human Body Model” Acceptance Criteria: “Normal Performance” (*) This current is intended as not repetitive pulse current ) s ( ct Table 4. Thermal Data AVss - 0.3 to +PAVcc +0.3 V 400 mArms e t le so b O - c u d ) s t( V o r P -40 to +85 °C -50 to 150 °C ±1500 V ±1000 V ±2000 V Parameter TQFP44 with slug Unit Rth-j-amb1 Maximum Thermal Resistance Junction-Ambient Steady State(*) 35 °C/W Rth-j-amb2 Maximum Thermal Resistance Junction-Ambient Steady State(**) 50 °C/W u d o Symbol r P e (*) Mounted on Multilayer PCB with a dissipating surface on the bottom side of the PCB (**) It's the same condition of the point above, without any heatsinking surface on the board. t e l o s b O 4/30 ST7538 Table 5. Electrical Characteristcs (AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C ≤ Tamb ≤ 85°C, Fc = 86kHz, other Control Register parameters as default value, unless otherwise specified). Symbol AVCC, DVCC Parameter Test Condition Supply Voltages Min. Typ. Max. Unit 4.75 5 5.25 V PAVCC - DVCC PAVCC and DVCC Relation during Power-Up Sequence DVCC < 4.75V 0.1 1.2 V PAVCC - AVCC PAVCC and DVCC Relation during Power-Up Sequence AVCC < 4.75V 0.1 1.2 V 7.5 12.5 V 100 V/ms PAVcc Power Supply Voltage Max allowed slope during Power-Up AICC + DICC I PAVCC Input Supply Current Transmission & Receiving mode 5 7 mA Powered Analog Supply Current TX mode (no load) 30 50 mArms RX mode 0.5 Maximum total current c u d Digital I/O VIH High Logic Level Input Voltage 2 VIL Low Logic Level input Voltage VOH High Logic Level Output Voltage IOH= -2mA VOL Low Logic Level Output Voltage IOL= 2mA Rdown Rup Pull up Resistor XOUTSWING XOUT Input Voltage Swing DC XTAL Clock Duty Cycle Xtal Crystal Oscillator frequency XtalESR XtalCL e t le so External Oscillator Esr Resistance b O - External Clock (see par. 3.8) XOUTOFFSET XOUT Input Voltage Offset (s) External Clock 0.4 V V V 100 kΩ 1 3 V 1.5 2.5 V 40 60 16 t c u t e l o 0.8 V kΩ od r P e ) s t( mA mArms 100 External Oscillator Stabilization Capacitance Transmitter % MHz 40 Ω 16 pF 1 mArms IATO Output Transmitting Current on ATO VATO Max Carrier Output AC Voltage RCL = 1.75kΩ Vsense (AC) = 0V 1.75 2.3 3.5 VPP VATODC Output DC Voltage on ATO 1.7 2.1 2.5 V HD2ATO Second Harmonic Distortion on ATO -55 -42 dB HD3ATO Third Harmonic Distortion on ATO -52 -49 dB IATOP Output Transmitting Current in programmable current limiting 310 370 mArms bs O o r P 3.5 Pull Down Resistor Oscillator 1 370 VATO = 2VPP Vsense connected though a 100pF cap to GND; Rcl=1.85kΩ; RLOAD =1Ω (as in fig. 17) 250 5/30 ST7538 Table 5. Electrical Characteristcs (continued) (AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C ≤ Tamb ≤ 85°C, Fc = 86kHz, other Control Register parameters as default value, unless otherwise specified). Symbol Parameter VATOP(AC) Max Carrier Output AC Voltage for each ATOP1 and ATOP2 pins Min. Typ. Max. Unit 3.5 4.6 7 Vpp VATOP(DC) Output DC Voltage on ATOP1 and ATOP2 pins 3.5 4.2 5 V HD2ATOP Second Harmonic Distortion on each ATOP1 and ATOP2 pins VATOP = 4VPP , PAVCC = 10V No Load -55 -42 dB Differential Second Harmonic Distortion VATOP = 4VPP , PAVCC = 10V RLOAD =50Ω (Differential) Carrier Frequency: 132.5KHz -65 -53 dB Third Harmonic Distortion on each ATOP1 and ATOP2 pins VATOP = 4VPP , PAVCC = 10V No Load. -56 -49 dB Differential Third Harmonic Distortion VATOP = 4VPP , PAVCC = 10V RLOAD =50Ω (Differential) Carrier Frequency: 132.5KHz -65 -52 VATOP Accuracy with Voltage Control Loop Active RCL = 1.75kΩ; Vsense (AC) = 0V GSTEP ALC Gain Step Control loop gain step HD3ATOP Test Condition RCL = 1.75kΩ ; Vsense (AC) = 0V VATOP ( AC ) PAVcc ≥ ------------------------------------ + 7.5V 2 DRNG ALC Dynamic Range VCLTH Voltage control loop reference threshold on Vsense pin Figure 15 Hysteresis on Voltage loop reference threshold Figure 15 Current control loop reference threshold on Csense pin Figure 15 VCLHYST CCLTH CCLHYST Hysteresis on Current loop reference threshold t c u VSENSE (DC) Output DC Voltage on VSENSE VSENSE TRxTx TALC TST o s b O - Figure 15 o r P 0.6 1 160 180 d o r P e Carrier Activation Time +1 GSTEP 1.4 dB 200 mVPK 30 dB ±18 mV 1.80 1.90 2.00 V 210 250 290 mV VSENSE Input Impedance t e l o s b O (s) e t le c u d -1 ) s t( dB 1.865 V 36 KΩ Figure 18 - 600 Baud Xtal=16MHz 0.01 1.6 ms Figure 18- 1200 Baud Xtal=16MHz 0.01 800 µs Figure 18- 2400 Baud Xtal=16MHz 0.01 400 µs Figure 18- 4800 Baud Xtal=16MHz 0.01 200 µs Carrier Stabilization Time From STEP 16 to zero or From step 16 to step 31, Figure 18. Xtal =16MHz 3.2 ms Tstep Figure 18 Xtal =16MHz 200 µs 2 mVrms Receiver VIN VIN 6/30 Input Sensitivity (Normal Mode) 0.5 Input Sensitivity (High Sens.) 250 Maximum Input Signal µVrms 2 Vrms ST7538 Table 5. Electrical Characteristcs (continued) (AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C ≤ Tamb ≤ 85°C, Fc = 86kHz, other Control Register parameters as default value, unless otherwise specified). Symbol Parameter Min. Typ. Max. Unit 80 100 140 kΩ Carrier Detection Sensitivity (Normal Mode) 0.5 2 mVrms Carrier Detection Sensitivity (High Sensitivity Mode) 250 Band in Use Detection Level 77 85 dB/ µVrms 5.05 5.2 V 5.2 V RIN Input Impedance VCD VBU Test Condition µVrms Voltage Regulator VDC ∆VDC Linear Regulator Output Voltage -25