STLC7550
Low Power Low Voltage Analog Front End
Features
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
General purpose signal processing Analog
Front End (AFE)
Targeted for V.34bis Modem and 56Kbps
Modem applications
16-BIT oversampling Σ∆ A/D and D/A
converters
83dB signal to noise ratio for sampling
frequency up to 9.6kHz @ 3V
87dB dynamic range @ 3V
Filter bandwidths:
0.425 x the sampling frequency
On-chip reference voltage
Single power supply range: 2.7 to 5.5V
Low power consumption less than 30mW
operating power 3V
Stand-by mode power consumption less than
3mW at 3V
Programming sampling frequency
Max. sampling frequency : 45kHz
Synchronous serial interface for processor
datas exchange Master or Slave operations
0.50µm CMOS process
TQFP48 package
STLC7546 mode of operation compatible
)
s
(
ct
Description
The STLC7550 is a single chip Analog Front-end
(AFE) designed to implement modems up to
56Kbps.
t
e
l
o
s
b
O
It has been especially designed for host
processing application in which the modulation
software (V.34bis, 56Kbps) is performed by the
main application processor : Pentium, Risc or
DSP processors.
The main target of this device is stand alone
appliances as Hand Held PC (HPC), Personnal
Digital Assistants (PDA), Webphones, Network
Computers, Set Top Boxes for Digital Television
(Satellite and Cable).
To comply with such applications STLC7550 is
powered nominally at 3V only.
c
u
d
e
t
le
)
s
t(
o
r
P
o
s
b
O
-
u
d
o
r
P
e
TQFP48 (7 x 7 x 1.4mm)
(Full Plastic Quad Flat Pack)
Maximum Power Dissipation 30mW is well suited
for Battery operations. In case of battery low,
STLC7550 will continue to work even at a 2.7V
level.
STLC7550 also provides clock generator for all
sampling frequencies requested for V.34bis and
56Kbps applications.
This new AFE can also be used for PC mother
boards or add-on cards or stand alone MODEMs.
It can be used in a master mode or slave mode.
The slave mode eases multi AFE architecture
design in saving external logical glue.
Order codes
Part number
Temp range, °C
Package
Packing
STLC7550TQF7
0 to 70
TQFP48
Tube
STLC7550TQF7TR
0 to 70
TQFP48
Tape & Reel
E-STLC7550TQF7 (*)
0 to 70
TQFP48
Tube
(*) ECOPACK® (see Section 6)
February 2006
Rev 9
1/24
www.st.com
24
Content
STLC7550
Content
1
Pins description & Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.1
Power Supply (5 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.2
Host interface (10 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.3
Clock signals (2 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.4
Analog interface (9 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
Transmit D/A section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
2.1.1
Transmit Low Pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2
D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.1
A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2
Receive Low Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
c
u
d
2.3
Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5
Host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6
Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
e
t
le
o
r
P
o
s
b
O
-
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2
Nominal DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3
Nominal AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4
Transmit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
)
s
(
ct
3.4.1
3.5
t
e
l
o
s
b
O
u
d
o
r
P
e
3.4.2
4
)
s
t(
Receive A/D section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Performance of the Tx channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Smoothing filter transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 19
Receive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5.1
Performance of the Rx channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
Definition and Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/24
Rev 9
STLC7550
Pins description & Block diagram
MCM
DGND
DVDD
FS
SCLK
Pin connection (top view)
XTALOUT
Figure 1.
XTALIN/MCLK
1
Pins description & Block diagram
12 11 10 9
8
7
6
5
4
3
2
1
13
48
14
47
HC1
15
46
HC0
16
45
DOUT
PWRDWN
17
44
DIN
M/S
18
43
TSTD1
VREFP
19
42
TS
VREFN
20
41
RESET
AGND1
21
40
OUT-
22
39
OUT+
23
38
24
c
u
d
37
Table 1.
Pin list
AGND2
VCM
AVDD
IN-
IN+
o
s
b
O
-
Pin Name
Type
1 - 2, 10 to 14,
22 to 26, 34 to
38, 46 to 48
NC
-
Not connected
O
Shift Clock Output
FS
I/O
Frame Synchronization Input (slave)/Output (master)
DVDD
I
Positive Digital Power Supply (2.7V TO 5.5V)
6
DGND
I
Digital Ground
7
MCM
I
Master Clock Mode
8
XTALOUT
O
Crystal Output
9
XTALIN/MCLK
I
Crystal Input (MCM = 1) / External Clock (MCM = 0)
15
HC1
I
Hardware Control Input
16
HC0
I
Hardware Control Input
17
PWRDWN
I
Power down Input
18
M/S
I
Master/Slave Mode Control Pin Input
19
VREFP
O
16-bit D/A and A/D Positive Reference Voltage
20
VREFN
O
16-bit D/A and A/D Negative Reference Voltage
4
o
r
P
e
5
t
e
l
o
O
e
t
le
o
r
P
Pin #
3
bs
AUXIN-
AUXIN+
25 26 27 28 29 30 31 32 33 34 35 36
)
s
t(
)
s
(
ct
SCLK
du
Rev 9
Description
3/24
Pins description & Block diagram
Table 1.
Note:
1
2
STLC7550
Pin list (continued)
Pin #
Pin Name
Type
Description
21
AGND1
I
Analog Ground
27
AUXIN+
I
Non-inverting Input to Auxiliary Analog Input
28
AUXIN-
I
Inverting Input to Auxiliary Analog Input
29
IN+
I
Non-inverting Input to Analog Input Amplifier
30
IN-
I
Inverting Input to Analog Input Amplifier
31
AVDD
I
Positive Analog Power Supply (2.7V to 5.5V)
32
VCM
O
Common Mode Voltage Output (AVDD/2)
33
AGND2
I
Analog Ground
39
OUT+
O
Non-inverting Smoothing Filter Output
40
OUT-
O
Inverting Smoothing Filter Output
41
RESET
I
Reset Function to initialize the internal counters
42
TS
I
Timeslot Control Input
43
TSTD1
I/O
44
DIN
I
Serial Data Input
45
DOUT
O
Serial Data Output
c
u
d
Digital Input/Output reserved for test
e
t
le
)
s
t(
o
r
P
To obtain published performance, the analog VDD and Digital VDD should be decoupled with
respect to Analog Ground and Digital Ground, respectively. The decoupling is intended to
isolate digital noise from the analog section ; decoupling capacitors should be as close as
possible to the respective analog and digital supply pins.
o
s
b
O
-
All the ground pins must be tied together. In the following section, the ground and supply
pins are referred to as GND and VDD, respectively.
)
s
(
ct
1.1
Pin description
1.1.1
Power Supply (5 pins)
u
d
o
r
P
e
Analog VDD Supply (AVDD)
t
e
l
o
This pin is the positive analog power supply voltage for the DAC and the ADC section.
bs
O
It is not internally connected to digital VDD supply (DVDD).
In any case the voltage on this pin must be higher or equal to the voltage of the Digital power
supply (DVDD).
Digital VDD Supply (DVDD)
This pin is the positive digital power supply for DAC and ADC digital internal circuitry.
Analog Ground (AGND1, AGND2)
These pins are the ground return of the analog DAC (ADC) section.
4/24
Rev 9
STLC7550
Pins description & Block diagram
Digital Ground (DGND)
This pin is the ground for DAC and ADC internal digital circuitry.
1.1.2
Host interface (10 pins)
Data In (DIN)
In Data Mode, the data word is the input of the DAC channel. In software, the data word is
followed by the control register word.
Data Out (DOUT)
In Data Mode, the data word is the ADC conversion result. In software, the data word is
followed by the register read.
Frame Synchronization (FS)
In master mode, the frame synchronization signal is used to indicate that the device is ready
to send and receive data. The data transfer begins on the falling edge of the frame-sync
signal. The framesync is generated internally and goes low on the rising edge of SCLK in
master mode. In slave mode the frame is generated externally.
c
u
d
Serial Bit Clock (SCLK)
)
s
t(
o
r
P
SCLK clocks the digital data into DIN and out of DOUT during the frame synchronization
interval. The Serial bit clock is generated internally.
e
t
le
Reset Function (RESET)
o
s
b
O
-
The reset function is to initialize the internal counters and control register. A minimum low
pulse of 100ns is required to reset the chip. This reset function initiates the serial data
communications. The reset function will initialize all the registers to their default value and
will put the device in a pre-programmed state. After a low-going pulse on RESET, the device
registers will be initialized to provide an over-sampling ratio equal to 160, the serial interface
will be in data mode, the DAC attenuation will be set to infinite, the ADC gain will be set to
0dB, the Differential input mode on the ADC converter will be selected, and the multiplexor
will be set on the main inputs IN+ and IN-. After a reset condition, the first frame
synchronization corresponds to the primary channel.
)
s
(
ct
u
d
o
r
P
e
Power Down (PWRDWN)
The Power-Down input powers down the entire chip (< 50mW). When PWRDWN Pin is
taken low, the device powers down such that the existing internally programmed state is
maintained. When PWRDWN is driven high, full operation resumes after 1ms. If the
PWRDWN input is not used, it should be tied to VDD.
s
b
O
t
e
l
o
Hardware Control (HC0, HC1)
These two pins are used for Hardware/Software Control of the device. The data on HC0 and
HC1 will be latched on to the device on the rising edge of the Frame Synchronization Pulse.
If these two pins are low, Software Control Mode is selected. When in Software Control
Mode, the LSB of the 16-bit word will select the Data Mode (LSB = 0) or the Control Mode
(LSB = 1). Other combinations of HC0/HC1 are for Hardware Control. These inputs should
be tied low if not used.
Rev 9
5/24
Pins description & Block diagram
STLC7550
Master/Slave Control (M/S)
When M/S is high, the device is in master mode and Fs is generated internally. When M/S is
low, the device is in slave mode and Fs must be generated externally.
Master Clock Mode (MCM)
When MCM is high, XTALIN is provided externally and must be equal to 36.864MHz. When
MCM is low, XTALIN is provided externally and must be equal to oversampling frequency :
Fs x Over (see Figure 3 and Section 2.4).
Timeslot Control (TS)
When TS = 0 the data are assigned to the first 16 bits after falling edge of FS (7546 mode)
otherwise the data are bits 17 to 32. The case M/S = 1 with TS = 1 is reserved for life-test
(transmit gain fixed to 0dB).
1.1.3
Clock signals (2 pins)
Depending on MCM value, these pins have different function.
MCM = 1 (XTALIN, XTALOUT)
c
u
d
)
s
t(
These pins must be tied to external crystal. For the value of crystal see Section 2.3.
MCM = 0 (MCLK, XTALOUT)
e
t
le
o
r
P
MCLK Pin must be connected to an external clock. XTALOUT is not used.
1.1.4
Analog interface (9 pins)
o
s
b
O
-
DAC and ADC Positive Reference Voltage Output (VREFP)
This pin provides the Positive Reference Voltage used by the 16-bit converters. The
reference voltage, VREF, is the voltage difference between the VREFP and VREFN outputs,
and its nominal value is 1.25V. VREFP should be externally decoupled with respect to VCM.
)
s
(
ct
DAC and ADC Negative Reference Voltage Output (VREFN)
u
d
o
This pin provides the Negative Reference Voltage used by the 16-bit converters, and should
be externally decoupled with respect to VCM.
r
P
e
Common Mode Voltage Output (VCM)
t
e
l
o
s
b
O
This output pin is the common mode voltage (AVDD - AGND)/2. This output must be
decoupled with respect to GND.
Non-inverting Smoothing Filter Output(OUT+)
This pin is the non-inverting output of the fully differential analog smoothing filter.
Inverting Smoothing Filter Output (OUT-)
This pin is the inverting output of the fully differential analog smoothing filter. Outputs OUT+
and OUTprovide analog signals with maximum peak-topeak amplitude 2 x VREF, and must
be followed by an external two pole smoothing filter. The external filter follows the internal
single pole switch capacitor filter. The cutoff frequency of the external filter must be greater
6/24
Rev 9
STLC7550
Pins description & Block diagram
than two times the sampling frequency (FS), so that the combined frequency response of
both the internal and external filters is flat in the passband. The attenuator of the last output
stage can be programmed to 0dB, 6dB or infinite.
Non-inverting Analog Input (IN+)
This pin is the differential non-inverting ADC input.
Inverting Analog Input (IN-)
This pin is the differential inverting ADC input. These analog inputs (IN+, IN-) are presented
to the Sigma-Delta modulator. The analog input peak-topeak differential signal range must
be less than 2 x VREF, and must be preceded by an external single pole anti-aliasing filter.
The cut-off frequency of the filter must be lower than one half the oversampling frequency.
These filters should be set as close as possible to the IN+ and IN- pins. The gain of the first
stage is programmable (see Table 4).
Non-inverting Auxiliary Analog Input (AUX IN+)
)
s
t(
This pin is the differential non-inverting auxiliary ADC input. The characteristics are same as
the IN+ input.
c
u
d
Inverting Auxiliary Analog Input (AUX IN-)
o
r
P
This pin is the differential inverting auxiliary ADC input. The characteristics are same as the
IN- input. The input pair (IN+/IN- or AUX IN+/AUX IN-) are software selectable.
IN+
29
IN-
30
AUXIN+
27
du
(0 + 6dB in
diff. input)
o
r
P
e
39
OUT-
40
VREFP
19
VREFN
20
VCM
32
s
b
O
t
e
l
o
HC0 HC1
16 15
(s)
ATTEN.
0dB/+6dB/
INFINITE
31
AVDD
LOW-PASS
(0.425 x sampling
frequency)
ct
28
OUT+
o
s
b
O
-
ANALOG
MODULATOR
MUX
AUXIN-
e
t
le
Block diagram
SERIAL PORTS
AND CONTROL REGISTER
Figure 2.
DAC 1 BIT
First order
differential
switched
capacitor
filter
LOW-PASS
(0.425 x sampling
frequency)
2nd ORDER
MODULATOR
7
MCM
45
DOUT
44
DIN
43
TSTD1
42
TS
18
M/S
4
FS
3
SCLK
CLOCK
GENERATOR
21
33
AGND1 AGND2
8
9
XTALOUT XTALIN
Rev 9
5
6
41
17
DVDD
DGND
RESET
PWRDWN
STLC7550
7/24
Functional description
STLC7550
2
Functional description
2.1
Transmit D/A section
The functions included in the Tx D/A section are detailed hereafter. 16-bit 2’s complement
data format is used in the DAC channel.
2.1.1
Transmit Low Pass Filters
The transmit low pass filter is basically an interpolating filter including a sinx/x correction. It
is a combination of Finite Impulse Response filter (FIR) and an Infinite Impulse Response
filter (IIR). The digital signal from the serial interface gets interpolated by 2, 3, 4, 5 or 6 x
Sampling Frequency (FS) through the IIR filter. The signal is further interpolated by 32 x FS
x n (with n equal to 2, 3, 4, 5, 6) through the IIR and FIR filter. The low pass filter is followed
by the DAC. The DAC is oversampled at 64, 96, 128, 160, 192 x FS. The oversampling ratio
is user selectable.
2.1.2
D/A Converter
c
u
d
)
s
t(
The oversampled D/A converter includes a second order digital noise shaper, a one bit D/A
converter and a single pole analog low-pass filter. The attenuation of the last output stage
can be programmed to 0dB, +6dB or infinite. The cut-off frequency of the single pole switchcapacitor lowpass is:
OCLK
fc – 3dB = ---------------------2 ⋅ π ⋅ 10
with OCLK = Oversampling Clock frequency.
e
t
le
o
r
P
o
s
b
O
-
Continuous-time filtering of the analog differential output is necessary using an off-chip
amplifier and a few external passive components. At least 79dB signal to noise plus
distortion ratio can obtained in the frequency band of 0.425 x 9.6kHz (with an oversampling
ratio equal to 160).
2.2
)
s
(
t
Receive A/D section
c
u
d
o
r
P
e
t
e
ol
The different functions included in the ADC channel section are described below. 16-bit 2’s
complement data format is used in the ADC.
2.2.1
s
b
O
2.2.2
A/D Converter
The oversampled A/D converter is based on a second order sigma-delta modulator. To
produce excellent common-mode rejection of unwanted signals, the analog signal is
processed differentially until it is converted to digital data. Single-ended mode can also be
used. The ADC is oversampled at 64, 96, 128, 160 or 192 x FS. The oversampling ratio is
user selectable. At least -85dB SNDR can be expected in the 0.425 x 9.6kHz bandwidth with
a -6dBr differential input signal and an oversampling ratio equal to 160.
Receive Low Pass Filter
It is a decimation filter. The decimation is performed by two decimation digital filters : one
decimation FIR filter and one decimation IIR filter. The purpose of the FIR filter is to
decimate 32 times the digital signal coming from the ADC modulator.
8/24
Rev 9
STLC7550
Functional description
The IIR is a cascade of 5 biquads. It provides the low-pass filtering needed to remove the
noise remaining above half the sampling frequency. The output of the IIR will be processed
by the DSP.
2.3
Clock generator
The master clock, MCLK is provided by the user thanks to a crystal or external clock
generator (see Figure 3).
The MCLK could be equal to 36.864MHz (MCM = 1). In that case thanks to the divider M x
Q, the STLC7550 is able to generate all V.34bis and 56 Kbps sampling frequencies (see
Table 2).
When MCM = 0, the MCLK must be equal to the oversampling frequency : Fs x OVER (7546
mode). The ADC and DAC are oversampled at the OCLK frequency. OCLK is equal to the
shift clock used in the serial interface.
The MCLK frequency should be :
MCLK = K x Sampling frequency
)
s
t(
Combination of M, Q and oversampling ratios allows to generate several sampling
frequencies.
o
r
P
Recommended values for classical modem applications are as follow :
Table 2.
Sampling Frequencies Generation
Q
e
t
le
over
M
Q
over
4.5
128
1
6
96
-
-
-
-
-
-
FQ = 36.864MHz (1)
FQ = 18.432MHz
F (kHz)
M
Q
over
16.00
3
6
128
13.96
3
5.5
160
13.71
3
7
12.80
3
6
12.00
3
du
o
r
P
e
O
Note:
1
so
M
FQ = 9.216MHz
128
b
O
1
7
192
1
7
96
160
2
4.5
160
1
4.5
160
128
2
6
128
1
6
128
6.5
160
-
-
-
-
-
-
ct
(s)
8
2
11.82
3
10.97
3
7
160
-
-
-
-
-
-
10.47
4
5.5
160
2
5.5
160
1
5.5
160
10.29
4
7
128
2
7
128
1
7
128
9.60
4
6
160
2
6
160
1
6
160
9.00
4
8
128
2
8
128
1
8
128
8.86
4
6.5
160
2
6.5
160
1
6.5
160
8.23
4
7
160
2
7
160
1
7
160
8.00
4
6
192
2
6
192
1
6
192
7.20
4
8
160
2
8
160
1
8
160
t
e
l
o
bs
c
u
d
Recommended value.
Rev 9
9/24
Functional description
Figure 3.
STLC7550
Clock Block Diagram
XTALIN
(MCLK)
XTALOUT
SCLK
MCM (OCLK)
M/S
Sync
VDD
÷M
÷Q
% OVER
Bit 3-4-5
Cont. Reg. : Bit 8-9-10-11-12-13
2.4
FS
Internal
Sampling
Modes of operation
Thanks to MCM and M/S programmation pins we can get the following configuration.
Configuration 1 : MCM = 1, M/S = 1
The STLC7550 is in master mode and we have :
c
u
d
Fs = XTAL IN / (M x Q x OVER)
Fs and SCLK are output pins.
Figure 4.
Configuration 1
e
t
le
fQ = 36.864MHz
o
s
b
O
-
)
s
t(
o
r
P
XTALIN
BCLK
ct
(s)
u
d
o
SCLK
FS
FS
DO
DIN
DI
DOUT
M/S
VDD
MCM
VDD
TS
GND
STLC7550
PROCESSOR
r
P
e
Configuration 2 : MCM = 1, M/S = 0
The STLC7550 is in slave mode. SCLK is provided by the STLC7550, the processor
generates the Fs and controls the phase of the sampling frequency.
Fs must be the result of a division of a number of cycles of SLCK (Fs = SCLK % OVER).
t
e
l
o
bs
O
Configuration 3 : MCM = 0, M/S = 1
The STLC7550 is in master mode and the processor provides the XTAL IN = MCLK =
OCLK. The STLC7550 generates the Fs from OCLK. In this mode the configuration 3 is
equivalent to the STLC7546 mode.
Configuration 4 : MCM = 0, M/S = 0
The STLC7550 is in slave mode. The configuration 4 is equivalent to configuration 3 but the
Fs is generated and phase controlled by the processor.
10/24
Rev 9
STLC7550
Functional description
Figure 5.
Configuration 2
fQ = 36.864MHz
XTALIN
BCLK
FS
FS
DO
DIN
DI
M/S
MCM
TS
DOUT
GND
VDD
GND
STLC7550
PROCESSOR
Figure 6.
SCLK
Configuration 3 (7546 mode)
fQ = K x Fs
XTALIN
BCLK
SCLK
FS
FS
DO
DIN
DI
PROCESSOR
M/S
VDD
MCM
GND
TS
GND
DOUT
STLC7550
e
t
le
c
u
d
)
s
t(
o
r
P
o
s
b
O
-
Configuration 5 : MCM = 1, M/S = 1 (master codec) MCM = 0, M/S = 0 (slave codec) This
is dual codec application. The master codec has his data in timeslot 0 and the slave codec
has his data in timeslot 1 thanks to the programmation of TS.
Figure 7.
Configuration 4
u
d
o
)
s
(
ct
r
P
e
s
b
O
t
e
l
o
fQ = K x Fs
XTALIN
BCLK
SCLK
FS
FS
DO
DIN
DI
DOUT
M/S
GND
MCM
GND
TS
GND
STLC7550
PROCESSOR
Rev 9
11/24
Functional description
Figure 8.
STLC7550
Configuration 5
fQ = 36.864MHz
XTALIN
PROCESSOR
BCLK
SCLK
FS
FS
DO
DIN
DI
DOUT
M/S
VDD
MCM
VDD
TS
GND
STLC7550
HC0
HC1
HC0
HC1
XTAKIN
VDD
TS
M/S
GND
FS
MCM
GND
DIN
c
u
d
DOUT
STLC7550
2.5
e
t
le
Host interface
)
s
t(
o
r
P
o
s
b
O
-
The Host interface consist of the shift clock, the frame synchronization signal, the
ADCchannel data output, and the DAC-channel data input.
Two modes of serial transfer are available :
–
First : Software mode for 15-bit transmit data transfer and 16-bit receive data
transfer
–
Second : hardware mode for 16-bit data transfer.
)
s
(
ct
u
d
o
Both modes are selected by the Hardware Control pins (HC0, HC1).
The data to the device, input/output are MSB-first in 2’s complement format (see Table 3).
r
P
e
When Control Mode is selected, the device will internally generate an additional Frame
Synchronization Pulse (Secondary Frame Synchronization Pulse) at the midpoint of the
original Frame Period. If the device is in slave mode the additional frame sync (secondary
frame sync pulse) must be generated by the processor. The Original Frame Synchronization
Pulse will also be referred to as the Primary Frame Synchronization Pulse.
t
e
l
o
s
b
O
12/24
Table 3.
Mode selection
HC1
HC0
LSB
Useful Data
Secondary
FSYNC
0
0
0
15bits
No
Software Mode for Data Transfer only.
0
0
1
15bits (+16bits reg.)
Yes
Software Mode for Data Transfer + Control
Register Transfer.
Rev 9
Description
STLC7550
Functional description
Table 3.
Mode selection (continued)
HC1
HC0
LSB
Useful Data
Secondary
FSYNC
0
1
X
16bits
No
Hardware Mode for Data Transfer only.
1
X
X
16bits (+16bits reg.)
Yes
Hardware Mode for Data Transfer +
Control Register Transfer.
Figure 9.
Description
Data Mode
Sampling period
FS
SCLK
TxDI
-
-
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
TxDO
-
-
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
Figure 10. Mixed Mode
e
t
le
Sampling Period
1/2 Sampling Period (see Note)
FS
SCLK
TxDI
Data Word Input
TxDO
Data Word Output
(s)
o
s
b
O
-
ct
HC1, HC0
u
d
o
D15 D14
c
u
d
00 or 01
HC1, HC0
)
s
t(
D15 D14
o
r
P
Control Word
Register Word
1X
01
Note : In slave mode, this 1/2 Sampling Period is not mandatory. If 1/2 Sampling Period is not provided, one sample is lost.
2.6
r
P
e
Control register
s
b
O
t
e
l
o
This section defines the control and device status information. The register programming
occurs only during Secondary Frame Synchronization. After a reset condition, the device is
always in data mode.
Table 4.
Bits Assignment
Bits
Name
0
-
1
2
Function
Reset Value
-
0
D1
Aux/Main Input
0
D2
Receive Gain
0
Rev 9
13/24
Functional description
Table 4.
STLC7550
Bits Assignment (continued)
Bits
Name
3
D3
Oversampling bit 0
0
4
D4
Oversampling bit 1
0
5
D5
Oversampling bit 2
0
6
D6
Attenuator transmit bit 0
0
7
D7
Attenuator transmit bit1
0
8
M
M Divider
1
9
Q0
Q0 Divider
1
10
Q1
Q1 Divider
0
11
Q2
Q2 Divider
0
12
T0
M Divider and Test mode bit 0
0
13
T1
M Divider and Test mode bit 1
14
TEST2
Test mode bit 2
15
TEST3
Test mode bit 3
Table 5.
Function
Main Receive Input
1
Auxiliary Receive Input
Table 6.
0
uc
d
o
r
P
e
let
Function
0
Receive Gain
)
s
(
ct
D2
Function
DIFFERENTIAL INPUT
o
s
b
O
-
u
d
o
0
0dB gain (commun mode fixed)
1
+6dB gain (commun mode non-fixed)
r
P
e
SINGLE ENDED (one input used, other at VCM)
bs
t
e
l
o
Note:
O
14/24
1
0
-6dB gain (see Note 1)
1
0dB gain
Not recommended case. Performances could be reduced.
Table 7.
Oversampling Ratio
D5
D4
D3
0
0
0
160
0
0
1
192
0
1
0
Reserved
0
1
1
Reserved
Function
Rev 9
)
s
t(
0
Aux/Main Input
D1
Reset Value
0
STLC7550
Functional description
Table 7.
Oversampling Ratio (continued)
D5
D4
1
0
0
Reserved
1
0
1
64
1
1
0
96
1
1
1
128
Table 8.
D6
0
0
Infinite
0
1
Reserved
1
0
-6dB
1
1
0dB
Function
Q Divider Clock Generator
D11
D10
D9
0
0
0
Q divider = 5
0
0
1
Q divider = 6
0
1
0
Q divider = 7
0
1
1
Q divider = 8
1
0
0
Q divider = 4.5
1
0
1
Q divider = 5.5
1
1
0
Q divider = 6.5
1
1
1
Q divider = 7.5
Table 10.
D12
0
0
t
e
l
o
)
s
(
ct
u
d
o
r
P
e
0
e
t
le
o
r
P
o
s
b
O
-
D8
Function
0
M divider = 3
0
1
M divider = 4
1
X
Reserved
1
0
X
Reserved
1
1
0
M divider = 1
1
1
1
M divider = 2
Table 11.
c
u
d
Function
)
s
t(
M Divider Clock Generator
D13
0
O
Function
Transmit Attenuation
D7
Table 9.
bs
D3
Reserved Mode
D15
D14
X
X
Function
Reserved for test
This two bits must be set to 0 for normal operation.
Rev 9
15/24
Electrical Specifications
3
STLC7550
Electrical Specifications
Unless otherwise noted, Electrical Characteristics are specified over the operating range.
Typical values are given for VDD = 3V, Tamb = 25°C and for nominal Master clock frequency
MCLK = 1.536MHz and oversampling ratio = 160.
3.1
Absolute maximum ratings
Table 12.
Absolute Maximum Ratings (referenced to GND)
Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
-0.3, 7.0
V
VI,VIN
Digital or Analog Input Voltage
-0.3, VDD+0.3
V
II,IIN
Digital or Analog Input Current
±1
mA
IO
Digital Output Current
±20
IOUT
Analog Output Current
±10
Toper
Operating Temperature
Tstg
Storage Temperature
od
PDMAX
ESD
0, 70
Maximum Power Dissipation
e
t
le
Electrostatic Discharge
Pr
°C
mW
2000
V
o
s
b
O
-
Nominal DC Characteristics
(VDD = 3V ± 5%, GND = 0V, TA = 0 to 70°C unless otherwise specified)
Parameter
u
d
o
Supply Voltage Range
mA
200
Table 13.
VDD
uc
°C
Nominal DC Characteristics
Symbol
mA
-40, 125
3.2
)
s
(
ct
)
s
t(
Min.
Typ.
Max.
Unit
2.70
3
5.5
V
r
P
e
POWER SUPPLY AND COMMON MODE VOLTAGE
SINGLE POWER SUPPLY (DVDD= AVDD)
t
e
l
o
IDDA
Analog Supply Current
6
mA
IDDD
Digital Supply Current
4
mA
s
b
O
IDD-LP
VCM
Supply Current in Low Power Mode
MCLK Stopped
MCLK Running
Output Common Mode Voltage VCM Output
Voltage Load Current (see Note 1)
VDD/2-5%
1
200
10
µA
VDD/2
VDD/2+5%
V
0.5
V
DIGITAL INTERFACE
16/24
VIL
Low Level Input Voltage
-0.3
VIH
High Level Input Voltage
DVDD-0.5
Rev 9
V
STLC7550
Table 13.
Electrical Specifications
Nominal DC Characteristics (continued)
(VDD = 3V ± 5%, GND = 0V, TA = 0 to 70°C unless otherwise specified)
Symbol
Parameter
II
Input Current VI = VDD or VI = GND
VOH
High Level Output Voltage (ILOAD= -600µA)
VOL
Low Level Output Voltage (ILOAD= 800µA)
Min.
Typ.
Max.
Unit
-10
±1
10
µA
DVDD-0.5
V
0.3
V
1.35
V
ANALOG INTERFACE
Differential Reference Voltage Output
VREF = (VREFP- VREFN)
VREF
Tcoeff (VREF)
1.15
VREF Temperature Coefficient
1.25
200
ppm/°C
VCMO IN
Input Common Mode Offset Voltage
VCMO IN = [(IN+)+(IN-)]/2 -VCM
VDIF IN
Differential Input Voltage : [(IN+)-(IN-)] ≤ 2 x VREF
VOFF IN
Differential Input DC Offset Voltage
-100
100
VCMO OUT
Output Common Mode Voltage Offset :
(OUT+ + OUT-)/2 - VCM (see Note 1)
-20
VDIF OUT
Differential Output Voltage :
OUT+ - OUT- ≤ 2 x VREF
uc
VOFF OUT
Differential Output DC Offset Voltage :
(OUT+ -OUT-) (0000x)
RIN
Input Resistance IN+, IN- (id. AUX IN)
ROUT
Output Resistance (OUT+, OUT-)
RL
Load Resistance (OUT+, OUT-)
CL
Load Capacitance (OUT+, OUT-)
VADO OUT
Note:
1
)
s
(
ct
-100
100
2 x VREF
r
P
e
t
le
-100
o
s
b
O
-
Output A/D Modulator Voltage Offset:
IN+ = IN- = VCM
Vpp
20
od
2 x VREF
mV
100
100
)
s
t(
mV
mV
V
mV
kΩ
50
W
10
kΩ
-1000
20
pF
+1000
LSB
u
d
o
Device is very sensitive to noise on VCM Pin. VCM output voltage load current must be DC
(
工商网监
湘ICP备2023018690号
