E30NK90Z

N-CHANNEL 900V - 0.21Ω - 28A ISOTOP Zener-Protected SuperMESH™ MOSFET Table 1: General Features TYPE STE30NK90Z s s s s STE30NK90Z Figure 1: Package ID 28 A Pw 500 W VDSS 900 V RDS(on) < 0.26 Ω TYPICAL RDS(on) = 0.21 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED GATE CHARGE MINIMIZED DESCRIPTION The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products. APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING s IDEAL FOR WELDING EQUIPMENT s ISOTOP Figure 2: Internal Schematic Diagram Table 2: Order Codes SALES TYPE STE30NK90Z MARKING E30NK90Z PACKAGE ISOTOP PACKAGING TUBE Rev.3 January 2005 1/10 STE30NK90Z Table 3: Absolute Maximum ratings Symbol VDS VDGR VGS ID ID IDM ( ) PTOT VESD(G-S) dv/dt (1) VISO Tj Tstg Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 2 0 kΩ) Gate- source Voltage Drain Current (continuous) at TC = 2 5°C Drain Current (continuous) at TC = 1 00°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Gate source ESD(HBM-C=100pF, R=1.5KΩ) Peak Diode Recovery voltage slope Insulation Withstand Voltage (AC-RMS) from All Four Terminals to External Heatsink Operating Junction Temperature Storage Temperature Value 900 900 ± 30 28 18 112 500 4.3 6.5 4.5 2500 Unit V V V A A A W W/°C KV V/ns V - 65 to 150 °C ( ) Pulse width limited by safe operating area (1) ISD ≤ 28A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Table 4: Thermal Data Rthj-case Rthj-amb Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max 0.23 40 °C/W °C/W Table 5: Avalanche Characteristics Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 °C, I D = IAR, VDD = 35 V) Max Value 13 500 Unit A mJ Table 6: GATE-SOURCE ZENER DIODE Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs=± 1mA (Open Drain) Min. 30 Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 2/10 STE30NK90Z ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 7: On/Off Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 1 mA, VGS = 0 VDS = Max Rating VDS = Max Rating, T C = 125 °C VGS = ± 20V VDS = VGS, ID = 150 µA VGS = 10V, ID = 14 A 3 3.75 0.21 Min. 900 10 100 ±100 4.5 0.26 Typ. Max. Unit V µA µA µA V Ω Table 8: Dynamic Symbol g fs (1) Ciss Coss Crss C oss eq. (3) td(on) tr td(off) tf Qg Qgs Qgd Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Equivalent Output Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDS = 15 V, ID = 14 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 26 12000 852 166 377 67 59 250 72 350 51 190 490 Max. Unit S pF pF pF pF ns ns ns ns nC nC nC VGS = 0V, VDS = 0V to 720 V VDD = 450 V, ID = 13 A RG = 4.7Ω VGS = 1 0 V (see Figure 17) VDD = 720 V, ID = 26 A, VGS = 10V (see Figure 20) Table 9: Source Drain Diode Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 28 A, VGS = 0 ISD = 26 A, di/dt = 100 A/µs VDD = 100 V, Tj = 25°C (see Figure 18) ISD = 26 A, di/dt = 100 A/µs VDD = 100 V, Tj = 150°C (see Figure 18) 1 18.9 36.6 1.33 25.2 37.8 Test Conditions Min. Typ. Max. 28 112 2 Unit A A V µs µC A µs µC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS. 3/10 STE30NK90Z Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics Figure 5: Transconductance Figure 8: Static Drain-source On Resistance 4/10 STE30NK90Z Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized On Resistance vs Temperature Figure 11: Source-Drain Diode Forward Characteristics Figure 14: Normalized BVdss vs Temperature 5/10 STE30NK90Z Figure 15: Avalanche Energy vs Starting Tj 6/10 STE30NK90Z Figure 16: Unclamped Inductive Load Test Circuit Figure 19: Unclamped Inductive Wafeform Figure 17: Switching Times Test Circuit For Resistive Load Figure 20: Gate Charge Test Circuit Figure 18: Test Circuit For Inductive Load Switching and Diode Recovery Times 7/10 STE30NK90Z ISOTOP MECHANICAL DATA DIM. MIN. A B C D E F G H J K L M N O 11.8 8.9 1.95 0.75 12.6 25.15 31.5 4 4.1 14.9 30.1 37.8 4 7.8 8.2 4.3 15.1 30.3 38.2 mm TYP. MAX. 12.2 9.1 2.05 0.85 12.8 25.5 31.7 MIN. 0.466 0.350 0.076 0.029 0.496 0.990 1.240 0.157 0.161 0.586 1.185 1.488 0.157 0.307 0.322 0.169 0.594 1.193 1.503 inch TYP. MAX. 0.480 0.358 0.080 0.033 0.503 1.003 1.248 G O B A N D E J K L M H C 8/10 F STE30NK90Z Table 10: Revision History Date 12-May-2004 15-Oct-2004 20-Jan-2005 Revision 1 2 3 Description of Changes First Release. New value inserted in table 3. (VISO ) Final Datasheet 9/10 STE30NK90Z Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 10/10