ECMF06-6AM16

ECMF06-6AM16 Common mode filter with ESD protection for MIPI D-PHY and MDDI interface Datasheet − production data Description 1 The ECMF06-6AM16 is a highly integrated common mode filter designed to suppress EMI/RFI common mode noise on high speed differential serial buses like MIPI D-PHY or MDDI. The ECMF06-6AM16 can protect and filter 3 differential lanes. Figure 1. Pin configuration (top view) Micro QFN-16 L: 1.35 x 3.3 mm Features • Very large differential bandwidth: higher than 6 GHz • High common mode attenuation: – -24 dB at 900 MHz – -20 dB between 800 MHz and 2.2 GHz • Very low PCB space consumption D0+ 1 16 D0+ D0- 2 15 D0- GND 3 14 NC D1+ 4 13 D1+ D1- 5 12 D1- GND 6 11 GND D2+ 7 10 D2+ D2- 8 9 D2 - • Thin package: 0.55 mm max • Lead-free package • High reduction of parasitic elements through integration Complies with the following standards: • IEC 61000-4-2 level 4: – ±15 kV (air discharge) – ±8 kV (contact discharge) Applications • Mobile phones • Notebook, laptop • Portable devices May 2014 This is information on a product in full production. DocID022284 Rev 3 1/15 www.st.com Characteristics 1 ECMF06-6AM16 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter Peak pulse voltage IDC Maximum DC current Top Operating temperature Tstg Unit 10 30 kV 100 mA -40 to +85 °C 125 °C - 55 to +150 °C IEC 61000-4-2 contact discharge IEC 61000-4-2 air discharge VPP Tj Value Maximum junction temperature Storage temperature range Figure 2. Electrical characteristics (definitions) I Symbol VBR IRM VRM IR Parameter Breakdown voltage Leakage current @ VRM Stand-off voltage Breakdown current = = = = VBR VRM V IRM IR Table 2. Electrical characteristics (values, Tamb = 25 °C) Symbol 2/15 Test conditions VBR IR = 1 mA IRM VRM = 3 V per line RDC DC serial resistance Min. Typ. Max. 6 V 2.7 DocID022284 Rev 3 Unit 100 nA 4 Ω ECMF06-6AM16 Characteristics Table 3. Pin description Pin name Description Pin name Description Pin name Description Pin name Description 1 D0+ DSI receiver 5 D1DSI receiver 9 D2DSI transmitter 13 D1+ DSI transmitter 2 D0DSI receiver 6 GND DSI receiver 10 D2+ DSI transmitter 14 NC DSI transmitter 3 GND DSI receiver 7 D2+ DSI receiver 11 GND DSI transmitter 15 D0DSI transmitter 4 D1+ DSI receiver 8 D2DSI receiver 12 D1DSI transmitter 16 D0+ DSI transmitter Figure 3. SDD21 differential attenuation measurement (Z0 diff = 100 Ω ) 0 SDD21 (dB) -0.5 -1 -1.5 -2 -2.5 -3 100k 1M D2 D1 10M F/Hz DocID022284 Rev 3 100M 1G D0 3/15 15 Characteristics ECMF06-6AM16 Figure 4. SCC21 common mode attenuation measurement (Z0 com = 50 Ω ) 0 SCC21 (dB) -5 -10 -15 -20 -25 -30 -35 -40 100k 1M 10M D2 D1 F/Hz 100M 1G D0 Figure 5. SDD11 differential return loss measurement (Z0 diff = 100 Ω ) 0 SDD11 (dB) -5 -10 -15 -20 -25 -30 -35 -40 -45 10M 30M 100M D2 D1 4/15 300M F/Hz DocID022284 Rev 3 1G D0 3G ECMF06-6AM16 Characteristics Figure 6. SDD22 differential attenuation measurement (Z0 diff = 100 Ω ) 0 SDD22 (dB) -5 -10 -15 -20 -25 -30 -35 -40 10M 30M 100M D2 D1 300M F/Hz 1G 3G D0 Figure 7. SDDxx inter-lane differential cross-coupling measurement (Z0 diff = 100 Ω ) 0 SDDxx (dB) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 100k 1M 10M D0-D1 F/Hz DocID022284 Rev 3 100M 1G D0-D2 5/15 15 Characteristics ECMF06-6AM16 Figure 8. SCCxx inter-lane common-mode cross-coupling measurement (Z0 diff = 100 Ω ) 0 SCCxx (dB) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 100k 1M 10M D0-D1 F/Hz 100M 1G D0-D2 Figure 9. MIPI D-PHY low power mode test setup Generator Agilent 81110 Pattern mode, F = 10 MHz modulation RZ, 50 Ω output Oscilloscope Lecroy 7300 A, 1 MΩ input CMF 6/15 DocID022284 Rev 3 ECMF06-6AM16 Characteristics Figure 10. Low power pulse response - see Figure 9 for test setup 500 mV/div Dx+ 100 ns/div 500 mV/div Dx- 100 ns/div Figure 11. ESD response to IEC61000-4-2 (+8 kV contact discharge) - see Figure 13 for test set-up 50 V/div 93 V 1 29 V 2 11 V 4 24 V 3 1 2 3 4 122 V 1 9V 2 9V 3 VPP: ESD peak voltage VCL :clamping voltage @ 30 ns VCL :clamping voltage @ 60 ns VCL :clamping voltage @ 100 ns 7V 4 20 ns/div DocID022284 Rev 3 7/15 15 Characteristics ECMF06-6AM16 Figure 12. ESD response to IEC61000-4-2 (-8 kV contact discharge) - see Figure 13 for test set-up 50 V/div -23 V 2 -4 V 4 -6 V 3 -76 V 1 1 2 3 4 -7 V 2 -4 V 3 VPP: ESD peak voltage VCL :clamping voltage @ 30 ns VCL :clamping voltage @ 60 ns VCL :clamping voltage @ 100 ns -1 V 4 -120 V 1 20 ns/div Figure 13. ESD measurement test set-up 2 x 20 dB attenuator ESD contact zap ±8 kV on pins 8/15 D0+ D0+ D0- D0- GND NC D1+ D1+ D1- D1- GND GND D2+ D2+ D2- D2 - DocID022284 Rev 3 Oscilloscope 50 Ω input 2 x 20 dB attenuator ECMF06-6AM16 2 Application information Application information Figure 14. Application information Display DSI Receiver Application processor D0+ D0+ D0- D0- GND GND D1+ D1+ D1- D1- GND GND CLK+ CLK+ CLK- CLK- DocID022284 Rev 3 DSI Transmitter 9/15 15 Package information 3 ECMF06-6AM16 Package information • Epoxy meets UL94, V0 • Lead-free packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 15. Micro QFN 3.3 x 1.35 16L package dimension definitions TOP VIEW D INDEX AREA (D/2 x E/2) E SIDE VIEW A1 A BOTTOM VIEW e INDEX AREA (D/2 x E/2) b 1 8 16 9 PIN # 1 ID L Table 4. Micro QFN 3.3 x 1.35 16L package dimension values Dimensions Ref. 10/15 Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.45 0.50 0.55 0.018 0.020 0.022 A1 0.00 0.02 0.05 0.00 0.0008 0.002 b 0.15 0.20 0.25 0.006 0.008 0.010 D 3.25 3.30 3.35 0.128 0.130 0.132 E 1.30 1.35 1.40 0.051 0.053 0.055 e 0.35 0.40 0.45 0.014 0.016 0.018 L 0.30 0.40 0.50 0.118 0.016 0.020 DocID022284 Rev 3 ECMF06-6AM16 Package information Figure 16. Footprint Figure 17. Marking 0.20 0.60 Dot: Pin 1 XX: Marking WW: Assembly week Y: Assembly year P: Assembly plant XX WW 1.75 YP 0.40 3.00 Figure 18. Tape and reel specifications Dot identifying Pin A1 location 5.5 ± 0.1 All dimensions in mm 1.75 ± 0.1 12.00 ± 0.3 3.70 ± 0.1 0.80 ± 0.1 Ø 1.55 ± 0.05 4.00 ± 0.1 2.00 ± 0.1 XX WW YP XX WW YP 1.70 ± 0.1 XX WW YP XX WW YP XX WW YP XX WW YP 4.00 ± 0.1 User direction of unreeling DocID022284 Rev 3 11/15 15 Recommendation on PCB assembly ECMF06-6AM16 4 Recommendation on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 19. Stencil opening dimensions L T b) W General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L×W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) 2. Reference design a) Stencil opening thickness: 100 µm b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%. c) Stencil opening for leads: Opening to footprint ratio is 90%. Figure 20. Recommended stencil window position 0.40 600 µm 540 µm 30 µm 0.20 0.60 10 µm 1.75 180 µm 200 µm Stencil window Footprint 12/15 DocID022284 Rev 3 3.00 ECMF06-6AM16 4.2 4.3 4.4 4.5 Recommendation on PCB assembly Solder paste 1. Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste recommended. 3. Offers a high tack force to resist component displacement during PCB movement. 4. Use solder paste with fine particles: powder particle size 20-45 µm. Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. Reflow profile Figure 21. ST ECOPACK® recommended soldering reflow profile for PCB mounting 240-245 °C Temperature (°C) 250 -2 °C/s 2 - 3 °C/s 60 sec (90 max) 200 -3 °C/s 150 -6 °C/s 100 0.9 °C/s 50 Time (s) 0 Note: 30 60 90 120 150 180 210 240 270 300 Minimize air convection currents in the reflow oven to avoid component movement. DocID022284 Rev 3 13/15 15 Ordering information 5 ECMF06-6AM16 Ordering information Figure 22. Ordering information scheme ECMF 06 - 6 A M16 Function Common mode filter with ESD protection Number of filtered lines 06 = Number of filtered lines Number of ESD protected lines 6 = 6 lines with ESD protection Version A = Version Package M = Micro QFN, pitch 400 µm 16 = 16 pads Table 5. Ordering information Order code Marking Package Weight Base qty Delivery mode ECMF06-6AM16 KF Micro QFN-16L 6.3 mg 3000 Tape and reel For the latest information on available order codes see the product pages on www.st.com. 6 Revision history Table 6. Document revision history 14/15 Date Revision Changes 14-Feb-2012 1 Initial release. 04-Oct-2012 2 Inserted Table 3 and updated Figure 1 to add A1 marker. 26-may-2014 3 Updated Figure 21, Figure 22, Figure 22 and document reformatted. DocID022284 Rev 3 ECMF06-6AM16 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2014 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com DocID022284 Rev 3 15/15 15