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EK3L02AQ

EK3L02AQ

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    -

  • 描述:

    BOARD EVAL MEMS FOR LIS3L02AQ

  • 数据手册
  • 价格&库存
EK3L02AQ 数据手册
LIS3L02AQ INERTIAL SENSOR: 3Axis - 2g/6g LINEAR ACCELEROMETER 1 ■ ■ ■ ■ ■ ■ ■ 2 Figure 1. Package FEATURES 2.4V TO 3.6V SINGLE SUPPLY OPERATION 0.5mg RESOLUTION OVER 100Hz BW 2g/6g USER SELECTABLE FULL-SCALE OUTPUT VOLTAGE, OFFSET AND SENSITIVITY RATIOMETRIC TO THE SUPPLY VOLTAGE FACTORY TRIMMED DEVICE SENSITIVITY AND OFFSET EMBEDDED SELF TEST HIGH SHOCK SURVIVABILITY ) s ( ct u d o ) r s (P t c e t u e dl o sr P b e O t e l ) o s ( s t b c u O -d o ) r s ( P t ec t u e dl o sr P b eO DESCRIPTION The LIS3L02AQ is a low-power three-axis linear accelerometer that includes a sensing element and an IC interface able to take the information from the sensing element and to provide an analog signal to the external world. The sensing element, capable to detect the acceleration, is manufactured using a dedicated process called THELMA (Thick Epi-Poly Layer for Microactuators and Accelerometers) developed by ST to produce inertial sensors and actuators in silicon. The IC interface instead is manufactured using a CMOS process that allows high level of integration to design a dedicated circuit which is trimmed to better match the sensing element characteristics. QFN-44 Table 1. Order Codes Part Number Package LIS3L02AQ QFN-44 The LIS3L02AQ has a user selectable full scale of 2g, 6g and it is capable of measuring accelerations over a maximum bandwidth of 4.0 KHz for the X and Y axis and 2.5KHz for the Z axis. The device bandwidth may be reduced by using external capacitances. A self-test capability allows the user to check the functioning of the system. The LIS3L02AQ is available in plastic SMD package and it is specified over a temperature range extending from -40°C to +85°C. The LIS3L02AQ belongs to a family of products suitable for a variety of applications: – Motion activated functions in mobile terminals – Gaming and Virtual Reality input devices – Free-fall detection and Data protection – Antitheft systems and Inertial Navigation – Appliance Control and Robotics Figure 2. Block Diagram S1X CHARGE AMPLIFIER S1Y S1Z t e l o rot MUX DEMUX S2Z S2Y bs Routx Voutx Routy Vouty Routz Voutz S/H S/H S2X S/H O VOLTAGE & CURRENT REFERENCE November 2004 TRIMMING CIRCUIT & TEST INTERFACE CLOCK & PHASE GENERATOR Rev. 4 1/9 LIS3L02AQ Table 2. Pin Description N° Pin 1 to 3 NC 4 GND 5 Vdd 6 Vouty 7 ST 8 Voutx Function Internally not connected 0V supply Power supply Output Voltage ) s ( ct Self Test (Logic 0: normal mode; Logic 1: Self-test) Output Voltage u d o ) r s (P t c e t u e dl o sr P b e O t e l ) o s ( s t b c u O -d o ) r s ( P t ec t u e dl o sr P b eO 9-13 14 15 16 NC Internally not connected PD Power Down (Logic 0: normal mode; Logic 1: Power-Down mode) Voutz Output Voltage FS Full Scale selection (Logic 0: 2g Full-scale; Logic 1: 6g Full-scale) 17-18 Reserved 19 NC 20 21 Leave unconnected Internally not connected Reserved Leave unconnected NC Internally not connected 22-23 Reserved 24-25 NC Internally not connected 26 Reserved Connect to Vdd or GND Reserved Leave unconnected or connect to Vdd Reserved Leave unconnected or connect to GND 27 28 29-44 Leave unconnected NC Internally not connected NC NC NC NC NC NC NC NC NC NC NC Figure 3. Pin Connection (Top view) Z 1 Y t e l o NC GND NC Vdd NC LIS3L02AQ Vouty Reserved ST Reserved Voutx Reserved Reserved NC Reserved Reserved Reserved Reserved Reserved NC NC FS NC NC Voutz NC PD X DIRECTION OF THE DETECTABLE ACCELERATIONS 2/9 NC NC NC O NC NC NC bs NC LIS3L02AQ Table 3. Electrical Characteristics (Temperature range -40°C to +85°C) All the parameters are specified @ Vdd =3.3V, T=25°C unless otherwise noted Symbol Parameter Test Condition Min. Supply voltage 3.3 3.6 V Supply current mean value PD pin connected to GND 0.85 1.5 mA Supply current in Power Down Mode rms value PD pin connected to Vdd 2 5 µA Ar So SoDr NL Zero-g level2 T = 25°C Zero-g level Vs temperature Delta from +25°C Acceleration range3 FS pin connected to GND FS pin connected to Vdd Vdd/2-10% fuc an t e l o Vdd/2 Vdd/2+10% V ±1.5 mg/°C ±1.8 ±2.0 g ±5.4 ±6.0 g Sensitivity2 Full-scale = 2g Vdd/5–10% Vdd/5 Vdd/5+10% Full-scale = 6g Vdd/15–10% Vdd/15 Vdd/15+10% Sensitivity drift Vs temperature Delta from +25°C ±0.01 Non Linearity4 Best fit straight line Full-scale = 2g X, Y axis ±0.3 ±1.5 % FS Best fit straight line; Full-scale = 2g Z axis ±0.6 ±2 % FS ±2 ±4 % CrossAx Cross-Axis5 Vt ) s ( ct u d o ) r s (P t c e t u e dl o sr P b e O t e l ) o s ( s t b c u O -d o ) r s ( P t ec t u e dl o sr P b eO OffDr O Unit Idd Voff bs Max. Vdd IddPdn 2.4 Typ.1 V/g V/g %/°C Sensing Element Resonant Frequency6 X, Y axis 3.2 4.0 4.8 KHz Z axis 1.8 2.5 3.2 KHz Acceleration noise density Vdd=3.3V; Full-scale = 2g Self test output voltage delta change7,8,9 50 µg/ Hz T = 25°C Vdd=3.3V Full-scale = 2g X axis -20 -40 mV T = 25°C Vdd=3.3V Full-scale = 2g Y axis 20 40 mV T = 25°C Vdd=3.3V Full-scale = 2g Z axis 20 50 mV 3/9 LIS3L02AQ Table 3. Electrical Characteristics (continued) (Temperature range -40°C to +85°C) All the parameters are specified @ Vdd =3.3V, T=25°C unless otherwise noted Symbol Vst Parameter Test Condition Self test input Rout Unit 0 0.8 V 2.2 Vdd V 140 kΩ 80 110 320 Capacitive load drive Turn-On Time at exit from Power Down mode Max. Logic 0 level 10 Ton Typ.1 Logic 1 level Output impedance Cload Min. Cload in µF 550*Cload +0.3 ms u d o ) r s (P t c e t u e dl o sr P b e O t e l ) o s ( s t b c u O -d o ) r s ( P t ec t u e dl o sr P b eO Notes: 1. Typical specifications are not guaranteed 2. Offset and sensitivity are essentially ratiometric to supply voltage 3. Guaranteed by wafer level test and measurement of initial offset and sensitivity 4. Guaranteed by design through measurements done up to 1g 5. Contribution to the measuring output of the inclination/acceleration along the perpendicular axis 6. Guaranteed by design 7. Self test “output voltage delta change” is defined as Vout(Vst=Logic1)-Vout(Vst=Logic0) 8. Self test “output voltage delta change” varies cubically with supply voltage 9. When full-scale is set to 6g, self-test “output delta change” is one third of the specified value 10.Bandwidth=1/(2*π*110KΩ*Cload) ABSOLUTE MAXIMUM RATING Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 4. Absolute Maximum Rating Symbol Ratings Maximum Value Unit Vdd Supply voltage -0.3 to 7 V Vin Input voltage on any control pin (FS, PD, ST) -0.3 to Vdd +0.3 V Acceleration (Any axis, Powered, Vdd=3.3V) 3000g for 0.5 ms APOW 10000g for 0.1 ms AUNP t e l o bs O 4/9 ) s ( ct pF Acceleration (Any axis, Unpowered) 3000g for 0.5 ms 10000g for 0.1 ms TOP Operating Temperature Range -40 to +85 °C TSTG Storage Temperature Range -40 to +105 °C ESD Electrostatic discharge protection 2KV HBM LIS3L02AQ 3 FUNCTIONALITY The LIS3L02AQ is a low-cost, low-power, analog output three-axis linear accelerometer packaged in QFN package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide an analog signal to the external world. 3.1 Sensing element The THELMA process is utilized to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and free to move on a plane parallel to the substrate itself. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the molding phase. The equivalent circuit for the sensing element is shown in the figure below; when a linear acceleration is applied, the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the sense capacitor. u d o ) r s (P t c e t u e dl o sr P b e O t e l ) o s ( s t b c u O -d o ) r s ( P t ec t u e dl o sr P b eO ) s ( ct Figure 4. Equivalent electrical circuit Cps1 Rs1 S1x Cpr Cs1x Rr Cs2x S2x Cps2 Rs2 Cps1 Rs1 S1y Cs1y Cpr Rr rot Cs2y S2y s b O t e l o Cps2 Rs2 Cps1 Rs1 S1z Cs1z Cpr Rr Cs2z S2z Cps2 Rs2 5/9 LIS3L02AQ The nominal value of the capacitors, at steady state, is few pF and when an acceleration is applied the maximum variation of the capacitive load is few hundredths of pF. 3.2 IC Interface The complete signal processing uses a fully differential structure, while the final stage converts the differential signal into a single-ended one to be compatible with the external world. The first stage is a low-noise capacitive amplifier that implements a Correlated Double Sampling (CDS) at its output to cancel the offset and the 1/f noise. The produced signal is then sent to three different S&Hs, one for each channel, and made available to the outside. The low noise input amplifier operates at 200 kHz while the three S&Hs operate at a sampling frequency of 66 kHz. This allows a large oversampling ratio, which leads to in-band noise reduction and to an accurate output waveform. u d o ) r s (P t c e t u e dl o sr P b e O t e l ) o s ( s t b c u O -d o ) r s ( P t ec t u e dl o sr P b eO ) s ( ct All the analog parameters (output offset voltage and sensitivity) are ratiometric to the voltage supply. Increasing or decreasing the voltage supply, the sensitivity and the offset will increase or decrease linearly. The feature provides the cancellation of the error related to the voltage supply along an analog to digital conversion chain. 3.3 Factory calibration The IC interface is factory calibrated to provide to the final user a device ready to operate. The trimming values are stored inside the device by a non volatile structure. Any time the device is turned on, the trimming parameters are downloaded into the registers to be employed during the normal operation thus allowing the final user to employ the device without any need for further calibration. t e l o s b O 6/9 LIS3L02AQ 4 PACKAGE INFORMATION Figure 5. QFN-44 Mechanical Data & Package Dimensions mm inch OUTLINE AND MECHANICAL DATA DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 1.70 1.80 1.90 0.067 0.071 0.075 A1 0.19 0.21 0.007 ) s ( ct 0.008 u d o ) r s (P t c e t u e dl o sr P b e O t e l ) o s ( s t b c u O -d o ) r s ( P t ec t u e dl o sr P b eO 0.20 0.25 0.30 0.008 0.01 D 7.0 0.276 E 7.0 0.276 e 0.50 0.020 0.012 J 5.04 5.24 0.198 0.206 K 5.04 5.24 0.198 0.206 L 0.38 0.58 0.015 P 0.48 45 REF 0.019 0.023 QFN-44 (7x7x1.8mm) Quad Flat Package No lead 45 REF SEATING PLANE b M G M s b O t e l o N 34 44 44 1 33 1 DETAIL "N" 23 11 22 12 DETAIL G 7/9 LIS3L02AQ Table 5. Revision History Date Revision January 2004 1 First Issue Description of Changes February 2004 2 Values of some parameters has been changed in Electrical characteristics table. November 2004 3 Modified/added some values in the table 2 Electrical characteristics. November 2004 4 Corrected few typo errors. u d o ) r s (P t c e t u e dl o sr P b e O t e l ) o s ( s t b c u O -d o ) r s ( P t ec t u e dl o sr P b eO ) s ( ct t e l o s b O 8/9 LIS3L02AQ ) s ( ct u d o ) r s (P t c e t u e dl o sr P b e O t e l ) o s ( s t b c u O -d o ) r s ( P t ec t u e dl o sr P b eO s b O t e l o Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 9/9
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