EMIF01-10005W5

EMIF01-10005W5 ® Application Specific Discretes A.S.D.TM EMI FILTER INCLUDING ESD PROTECTION MAIN APPLICATIONS Where EMI filtering in ESD sensitive equipment is required : Computers and printers Communication systems Mobile phones MCU Boards DESCRIPTION The EMIF01-10005W5 is a highly integrated array designed to suppress EMI / RFI noise in all systems subjected to electromagnetic interferences. Additionally, this filter includes an ESD protection circuitry which prevents the protected device from destruction when subjected to ESD surges up to 15 kV. BENEFITS SOT323-5L FUNCTIONAL DIAGRAM I1 Cost-effectiveness compared to discrete solution EMI bi-directional low-pass filter High efficiency in ESD suppression. High flexibility in the design of high density boards Very low PCB space consuming : 4.2 mm2 typically High reliability offered by monolithic integration O1 GND I2 O2 COMPLIES WITH THE FOLLOWING STANDARD: IEC 1000-4-2 15kV 8 kV RI/O = 100Ω CIN = 50pF (air discharge) (contact discharge) ESD response to IEC1000-4-2 (16 kV air discharge) Filtering response dB 0 -10 -20 f(MHz) -30 1 10 100 1000 2000 TM : ASD is trademark of STMicroelectronics. May 1999 - Ed: 1 1/10 EMIF01-10005W5 ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C) Symbol VPP Tj Parameter and test conditions Value Unit ESD discharge IEC1000-4-2, air discharge ESD discharge IEC1000-4-2, contact discharge 16 9 kV Junction temperature 150 °C Top Operating temperature range -40 to + 85 °C Tstg Storage temperature range -55 to +150 °C TL Lead solder temperature (10 second duration) 260 °C ELECTRICAL CHARACTERISTICS (Tamb = 25 °C) Symbol Parameter VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic impedance IPP Peak pulse current RI/O Series resistance between Input and Output CIN Input capacitance per line Symbol Test conditions VBR IR = 1 mA IRM VRM = 3V I VCL VBR VRM slope : 1 / R d IPP Min. Typ. Max. Unit 6 7 8 V 1 µA 120 Ω 80 RI/O 100 Rd Ipp = 10 A, tp = 2.5 µs (see note 1) 1 Ω CIN at 0V bias 50 pF Note 1 : to calculate the ESD residual voltage, please refer to the paragraph "ESD PROTECTION" on pages 4 & 5 2/10 V IRM IR EMIF01-10005W5 TECHNICAL INFORMATION FREQUENCY BEHAVIOR The EMIF01-10005W5 is firstly designed as an EMI/RFI filter. This low-pass filter is characterized by the following parameters: - Cut-off frequency - Insertion loss - High frequency rejection Fig A1: EMIF01-10005W5 frequency response curve. dB 0 -10 -20 f(MHz) -30 1 10 100 1000 2000 Figure A1 gives these parameters, in particular the signal rejection at the GSM frequency is about -24dB at 900MHz, Fig A2: Measurement conditions TRACKING GENERATOR Vg SMA TEST BOARD EMIF01 50Ω TG OUT SPECTRUM ANALYSER SMA RF IN 50Ω 3/10 EMIF01-10005W5 ESD PROTECTION In addition to its filtering function, the EMIF01-10005W5 is particularly optimized to perform ESD protection. ESD protection is based on the use of device which clamps at : VCL = VBR + Rd.IPP This protection function is splitted in 2 stages. As shown in figure A3, the ESD strikes are clamped by the first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output voltage very low at the Vout level. Fig A3 : ESD clamping behavior Rg ESD Surge R Rd Rd Vg Vout Vin Rload Vbr Vbr S2 S1 EMIF01-10005W5 Device to be protected To have a good approximation of the remaining voltages at both Vin and Vout stages, we provide the typical dynamical resistance value Rd. By taking into account these following hypothesis : R>>Rd, RG>>Rd and Rload>>Rd, it gives these formulas: Vin = Rg.Vbr+Rd.Vg Rg Vout = R.Vbr+Rd.Vin R The results of the calculation done for VG=8kV, RG=330Ω (IEC1000-4-2 standard) and VBR=7V (typ.) give: Vin = 31.2 V Vout = 7.3 V This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side due the low current involved after the resistance R. Fig A4 : Measurement conditions 16kV Air Discharge 4/10 TEST BOARD Vin EMIF01 ESD SURGE Vout EMIF01-10005W5 The measurements shown here after illustrate very clearly (Fig. A5a) the high efficiency of the ESD protection : - no influence of the parasitic inductances on Vout stage - Vout clamping voltage very close to VBR Fig A5 : Remaining voltage at both stages S1 (Vin) and S2 (Vout) during ESD surge a) Positive surge Please note that the EMIF01-10005W5 is not only acting for positive ESD surges but also for negative ones. For these kind of disturbances it clamps close to ground voltage as shown in Fig. A5b. NOTE: DYNAMIC RESISTANCE MEASUREMENT As the value of the dynamic resistance remains stable for a surge duration lower than 20µs, the 2.5µs rectangular surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of Rd. b) Negative surge Fig A6 : Rd measurement current wave I IPP t 2 µs 2.5 µs 2.5µs duration measurement wave 5/10 EMIF01-10005W5 CROSSTALK BEHAVIOR 1- Crosstalk phenomena Fig A7 : Crosstalk phenomena RG1 line 1 VG1 α VG1 β VG2 RL1 RG2 line 2 VG2 α VG2 RL2 DRIVERS β VG1 RECEIVERS 2- Digital Crosstalk Fig A8 : Digital crosstalk measurement +5V +5V 74HC04 74HC04 Line 1 Square Pulse Generator 5KHz +5V VG1 EMIF01 -10005W5 Line 2 β 21 VG1 Figure A8 shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. Figure A9 shows that in such a condition signal from 0 to 5V and rise time of 3 ns, the impact on the disturbed line is less than 100mV peak to peak. No data disturbance was noted on the concerned line. The same results were obtained with falling edges. Fig A9 : Digital crosstalk results 6/10 EMIF01-10005W5 3- Analog Crosstalk Fig A10 : Analog crosstalk measurement TRACKING GENERATOR SPECTRUM ANALYSER SMA EMIF01 50Ω TG OUT TEST BOARD RF IN 50Ω Vg Figure A10 gives the measurement circuit for the analog application. In figure A11, the curve shows the effect of cell I/O1 on cell I/O2. In usual frequency range of analog signals (up to 100MHz) the effect on disturbed line is less than -43 dB. Fig A11 : Typical analog crosstalk result 0 SMA dB -20 -40 -60 -80 -100 1 10 100 1,000 F(MHz) 7/10 EMIF01-10005W5 4 - PSpice model Fig A12: PSpice model of one EMIF01 cell Fig A13: PSpice parameters Dz 7 25p 100u 1000 10E-15 100p 1 0.3333 1 0.6 50n BV Cjo IBV IKF IS ISR N M RS VJ TT Df 1000 25p 100u 1000 1.016E-15 100p 1.0755 0.3333 1 0.6 50n Dr 1000 1p 100u 1000 10E-15 100p 0.6 0.3333 1m 0.6 1n Note This model is available for an ambient temperature of 27°C Fig. A14: PSpice simulation : IEC 1000-4-2 Contact Discharge response a) Positive surge b) Negative surge (V) (V) 60 Vin 50 Vout 40 0 Vin -10 Vout -20 30 -30 20 -40 10 -50 0 0 20 40 60 80 100 t(ns) dB 0 Measured PSpice -10 -20 1 10 100 F(MHz) 8/10 0 20 40 60 t(ns) Fig A15: Comparison between PSpice simulation and measured frequency response -30 -60 1,000 80 100 EMIF01-10005W5 ORDER CODE EMIF 01 - 100 05 W5 SOT323-5L package EMI FILTER Input capacitance value /10 TYPE Series resistance value Order code Marking Package Weight Base qty Delivery mode EMIF01-10005W5 M12 SOT323-5L 5.4 mg 3000 Tape & reel 9/10 EMIF01-10005W5 PACKAGE MECHANICAL DATA SOT323-5L DIMENSIONS REF. A Millimeters Inches A2 A1 D e e H E Q1 c Min. Max. Min. Max. A 0.8 1.1 0.031 0.043 A1 0 0.1 0 0.004 A2 0.8 1 0.031 0.039 b 0.15 0.3 0.006 0.012 c 0.1 0.18 0.004 0.007 D 1.8 2.2 0.071 0.086 E 1.15 1.35 0.045 0.053 e 0.65 Typ. H 1.8 2.4 0.071 0.094 Q1 0.1 0.4 0.004 0.016 b RECOMMENDED FOOTPRINT 0.3mm Mechanical specifications Lead plating Tin-lead 1mm 29mm 1mm Lead plating thickness 5µm min. 25 µm max. Lead material Sn / Pb (70% to 90% Sn) Lead coplanarity 100µm max. Body material Molded epoxy Flammability UL94V-0 0.35mm Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 1999 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 10/10