EMIF02-MIC03M6
2-line IPAD™, EMI filter and ESD protection for microphone
Features
Pin 1
■
■
■
■
■
■
■
■
EMI symmetrical (I/O) low-pass filter
High efficiency in EMI filtering
Very low PCB space consumption:
1.0 mm x 1.45 mm
Very thin package: 0.6 mm max
High efficiency in ESD suppression
High reliability offered by monolithic integration
High reduction of parasitic elements through
integration and wafer level packaging
Lead-free and halogen-free package
Micro QFN 6 leads
1.45 mm x 1.00 mm
(bottom view)
Figure 1.
Pin configuration (top view)
Complies with following standards
■
IEC 61000-4-2 level 4, input and output pins
■
IEC 61000-4-2 level 4 requirements
– 8 kV (contact discharge)
or
– 15 kV (air discharge)
MICR in
1
6
MICR out
GND
2
5
GND
MICL in
3
4
MICL out
Application
■
Mobile phones
Description
Figure 2.
The EMIF02-MIC03M6 is a 2-line highly
integrated device designed to suppress EMI/RFI
noise in all systems exposed to electromagnetic
interference.
Basic cell configuration
Low-pass filter
Input
This filter includes ESD protection circuitry, which
prevents damage to the application when
subjected to ESD surges up to 8 kV on all pins.
Output
GND
GND
GND
R = 68 Ω, Cline = 45 pF typ.
TM: IPAD is a trademark of STMicroelectronics
May 2011
Doc ID 14448 Rev 2
1/11
www.st.com
11
Characteristics
EMIF02-MIC03M6
1
Characteristics
Table 1.
Absolute ratings(1)
Symbol
VPP
Tj
Parameter
Value
Unit
ESD discharge IEC61000-4-2 contact discharge
ESD discharge IEC61000-4-2 air discharge(2)
8
15
kV
Junction temperature
125
°C
Top
Operating temperature range
-40 to + 85
°C
Tstg
Storage temperature range
-55 to +150
°C
1. limiting values at Tamb = 25 °C unless otherwise specified
2. According to IEC61000-4-2 test conditions with ungrounded table top equipment set-up, PCB board on insulated plane
(dimensions 25 x 25 mm2), 2 serial resistors of 470 kΩ to GND reference plane
Table 2.
Electrical characteristics (Tamb = 25 °C)
Symbol
Parameter
I
VBR
Breakdown voltage
IRM
Leakage current @ VRM
VRM
Stand-off voltage
VCL
Clamping voltage
Rd
Dynamic resistance
IPP
Peak pulse current
RI/O
Series resistance between Input & Output
Cline
Input capacitance per line
Symbol
IPP
VCL VBR VRM
IR
IRM
IRM
IR
Test conditions
VRM VBR VCL
V
IPP
Min.
Typ.
6
8
Max.
Unit
VBR
IR = 1 mA
IRM
VRM = 3 V per line
RI/O
Tolerance ± 20%
68
Ω
VR = 0 V, F = 1 MHz, VOSC = 30 mV
45
pF
Cline (1)
500
1. Tolerance ± 20%
2/11
V
Doc ID 14448 Rev 2
nA
EMIF02-MIC03M6
Figure 3.
0.00
Characteristics
S21 attenuation measurement
dB
Figure 4.
0.00
-5.00
-10.00
-10.00
-20.00
-15.00
-30.00
Analog cross talk measurements
(MIC R / MIC L)
dB
-40.00
-20.00
-50.00
-25.00
-60.00
-30.00
-80.00
300.0k
-40.00
300.0k
Figure 5.
1.0M
3.0M
F (Hz)
-70.00
F (Hz)
-35.00
10.0M 30.0M 100.0M 300.0M 1.0G
3.0G
ESD response to IEC 61000-4-2
(+8 kV contact discharge) on MIC
lines
Figure 6.
1.0M 3.0M
Xtalk R- L
10.0M 30.0M 100.0M 300.0M 1.0G
Xtalk L-R
ESD response to IEC 61000-4-2
(-8 kV contact discharge) on MIC
lines
vi = 20 V/d
Input
3.0G
vi = 20 V/d
Input
vo = 10 V/d
Output
vo = 10 V/d
Output
20 ns/d
Doc ID 14448 Rev 2
20 ns/d
3/11
Ordering information scheme
2
EMIF02-MIC03M6
Ordering information scheme
Figure 7.
Ordering information scheme
EMIF
EMI Filter
Number of lines
Information
xxx = application
zz = version
Package
Mx = Micro QFN x leads
4/11
Doc ID 14448 Rev 2
yy
-
xxx zz
Mx
EMIF02-MIC03M6
3
Package information
Package information
●
Epoxy meets UL94, V0
●
Lead-free packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 3.
Micro QFN 1.45 x 1.00 6L dimensions
Dimensions
D
N
Ref.
Millimeters
Inches
E
1
Min.
Typ.
Max.
Min.
A
0.50
0.55
0.60
0.020 0.022 0.024
A1
0.00
0.02
0.05
0.000 0.001 0.002
b
0.18
0.25
0.30
0.007 0.010 0.012
2
A
A1
1
2
L
k
Typ.
D
1.45
0.057
E
1.00
0.039
e
0.50
0.020
Max.
b
e
Figure 8.
Footprint in mm [inches]
0.50
[0.020]
K
0.20
L
0.30
Figure 9.
0.25
[0.010]
0.008
0.35
0.40
0.012 0.014 0.016
Marking
Dot : Pi n 1 Identification
0.60
[0.023]
0.30
1.60
[0.012] [0.063]
Doc ID 14448 Rev 2
L
5/11
Package information
EMIF02-MIC03M6
Figure 10. Tape and reel specification
Dot identifying pin 1 location
3.5 +/- 0.03
1.65
8.0 +/- 0.3
0.75
All dimensions in mm
Note:
6/11
φ 1.5 +/- 0.1
4.00+/-0.1
1.75 +/- 0.1
2.0+/-0.05
L
L
1.20
L
4.00
User direction of unreeling
Product marking may be rotated by 90° for assembly plant differentiation. In no case should
this product marking be used to orient the component for its placement on a PCB. Only pin
1 mark is to be used for this purpose.
Doc ID 14448 Rev 2
EMIF02-MIC03M6
Recommendation on PCB assembly
4
Recommendation on PCB assembly
4.1
Stencil opening design
1.
General recommendation on stencil opening design
a)
Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 11. Stencil opening dimensions
L
T
b)
W
General design rule
Stencil thickness (T) = 75 ~ 125 µm
W
Aspect Ratio = ----- ≥ 1.5
T
L×W
Aspect Area = ---------------------------- ≥ 0.66
2T ( L + W )
2.
Reference design
a)
Stencil opening thickness: 100 µm
b)
Stencil opening for leads: Opening to footprint ratio is 90%.
Figure 12. Recommended stencil window position
7 µm
7 µm
620 µm
650 µm
15 µm
236 µm
15 µm
Footprint
250 µm
Stencil window
Footprint
Doc ID 14448 Rev 2
7/11
Recommendation on PCB assembly
4.2
4.3
4.4
8/11
EMIF02-MIC03M6
Solder paste
1.
Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
2.
“No clean” solder paste is recommended.
3.
Offers a high tack force to resist component movement during high speed.
4.
Solder paste with fine particles: powder particle size is 20-45 µm.
Placement
1.
Manual positioning is not recommended.
2.
It is recommended to use the lead recognition capabilities of the placement system, not
the outline centering.
3.
Standard tolerance of ± 0.05 mm is recommended.
4.
3.5 N placement force is recommended. Too much placement force can lead to
squeezed out solder paste and cause solder joints to short. Too low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages.
5.
To improve the package placement accuracy, a bottom side optical control should be
performed with a high resolution tool.
6.
For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is
recommended during solder paste printing, pick and place and reflow soldering by
using optimized tools.
PCB design preference
1.
To control the solder paste amount, the closed via is recommended instead of open
vias.
2.
The position of tracks and open vias in the solder area should be well balanced. The
symmetrical layout is recommended, in case any tilt phenomena caused by
asymmetrical solder paste amount due to the solder flow away.
Doc ID 14448 Rev 2
EMIF02-MIC03M6
4.5
Recommendation on PCB assembly
Reflow profile
Figure 13. ST ECOPACK® recommended soldering reflow profile for PCB mounting
Temperature (°C)
260°C max
255°C
220°C
180°C
125 °C
2°C/s recommended
2°C/s recommended
6°C/s max
6°C/s max
3°C/s max
3°C/s max
0
0
1
2
3
4
5
10-30 sec
90 to 150 sec
Note:
6
7
Time (min)
90 sec max
Minimize air convection currents in the reflow oven to avoid component movement.
Doc ID 14448 Rev 2
9/11
Ordering information
5
EMIF02-MIC03M6
Ordering information
Table 4.
Ordering information
Order code
Marking
Package
Weight
Base qty
Delivery mode
EMIF02-MIC03M6
L(1)
Micro QFN
2.2 mg
3000
Tape and reel (7”)
1. The marking can be rotated by 90° to differentiate assembly location
6
Revision history
Table 5.
10/11
Document revision history
Date
Revision
Changes
13-Feb-2008
1
Initial release
27-May-2011
2
Updated ECOPACK statement. Updated n: IEC 61000-4-2 level 4
requirements on page 1. Added note 2. on page 2 . Updated title
Figure 5. and Figure 6. on page 3.
Doc ID 14448 Rev 2
EMIF02-MIC03M6
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Doc ID 14448 Rev 2
11/11
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