EMIF03-SIM02M8

EMIF03-SIM02M8 Datasheet 3 line IPAD, EMI filter for SIM card applications Features 1 8 7 • • • • • • • 2 GND GND 6 3 5 4 Micro QFN 1.7 mm x 1.5 mm (bottom view) Pin configuration (top view) VCC RSTIN RSTEXT GND VCC CLKIN DATA IN CLKEXT DATA EXT • • • • Device configuration RSTIN CLKIN DATA IN VCC 100 Ω R1 47Ω R2 100 Ω R3 RSTEXT CLKEXT DATA EXT • GND Maximum line capacitance = 20 pF Product status EMIF03-SIM02M8 SIM card EMI low-pass filter High efficiency in EMI filtering Very low PCB space consuming: 1.7 mm x 1.5 mm Very thin package: 0.6 mm max. High efficiency in ESD suppression on external pins (IEC 61000-4-2 level 4) High reliability offered by monolithic integration High reduction of parasitic elements through integration and wafer level packaging Lead free package Easy layout and flexibility thanks to I/O topology Low clamping voltage Complies with following standards: – IEC 61000-4-2 level 4 externals pins ◦ 15 kV (air discharge) ◦ 8 kV (contact discharge) – IEC 61000-4-2 level 2 internal pins ◦ 2 kV (air discharge) ◦ 2 kV (contact discharge) MIL STD 883G - Method 3015-7 Class 3A (all pins) Applications Where EMI filtering in ESD sensitive equipment is required: • Keyboard for mobile phones • Computers and printers • Communication systems • MCU boards Description The EMIF03-SIM02M8 is a 3 line highly integrated device designed to suppress EMI/RFI noise in all systems exposed to electromagnetic interference. This filter includes ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up to 15 kV on the external pins. DS5513 - Rev 2 - January 2022 For further information contact your local STMicroelectronics sales office. www.st.com EMIF03-SIM02M8 Characteristics 1 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter Value Unit Internal pins: VPP Tj ESD discharge IEC 61000-4-2 air discharge 2 ESD discharge IEC 61000-4-2 contact discharge 2 kV External pins and VCC: ESD discharge IEC 61000-4-2 air discharge 15 ESD discharge IEC 61000-4-2 contact discharge 8 Maximum junction temperature 125 °C Top Operating temperature range - 40 to + 85 °C Tstg Storage temperature range - 55 to + 150 °C Figure 1. Electrical characteristics (definitions) I IF Symbol VBR IRM VRM VCL Rd IPP RI/O Cline Parameter Breakdown voltage Leakage current at VRM Stand-off voltage Clamping voltage VBR VCL VF VRM V IRM IR Dynamic resistance Peak pulse current Series resistance between Input and Output Input capacitance per line IPP Table 2. Electrical characteristics (Tamb = 25 °C) Symbol DS5513 - Rev 2 Test conditions VBR IR = 1 mA IRM VRM = 3 V per line Min. Typ. 6 Max. Unit 7.9 V 0.2 µA R1, R3 Tolerance ±20% 100 Ω R13 Tolerance ±20% 47 Ω Cline VR = 0 V, VOSC = 30 mV, F = 1 MHz 17 20 pF page 2/13 EMIF03-SIM02M8 Characteristics (curves) 1.1 Characteristics (curves) Figure 3. S21(db) attenuation (CLK line) Figure 2. S21(db) attenuation (RST line) 0.00 dB dB 0.00 -5.00 -5.00 -10.00 -10.00 -15.00 -15.00 -20.00 -20.00 -25.00 -25.00 -30.00 -30.00 F (Hz) F (Hz) -35.00 -35.00 300.0k 1.0M 3.0M 10.0M 3 0.0M 1 00.0M 300.0M 1.0G 3.0G 300.0k Figure 4. S21(db) attenuation (DATA line) 0.00 dB 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G Figure 5. Analog cross talk measurements 0.00 dB -10.00 -20.00 -5.00 -30.00 -10.00 -40.00 -50.00 -15.00 -60.00 -70.00 -20.00 -80.00 -90.00 -25.00 -100.00 -30.00 -110.00 F (Hz) 300.0k 300.0k 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G 1.0M 3.0M ClkIn-RstExt 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G DataIn-Rst/Clk Figure 7. ESD response to IEC 61000-4-2 (-15 kV air discharge) applied to external pin 2 V/div 2 V/div 5 V/div 5 V/div Figure 6. ESD response to IEC 61000-4-2 (+15 kV air discharge) applied to external pin 200 ns/div DS5513 - Rev 2 F (Hz) -120.00 -35.00 200 ns/div page 3/13 EMIF03-SIM02M8 Characteristics (curves) 5 V/div 2 V/div 2 V/div 20 ns/div DS5513 - Rev 2 Figure 9. ESD response to IEC 61000-4-2 (-2 kV air discharge) applied to internal pin 5 V/div Figure 8. ESD response to IEC 61000-4-2 (+2 kV air discharge) applied to internal pin 20 ns/div page 4/13 EMIF03-SIM02M8 Application schematic 2 Application information DS5513 - Rev 2 Vcc RST in CLK in Data in RST EXT CLK EXT Data EXT SIM CONNECTOR Vcc GND SIM PROCESSOR Figure 10. Application schematic page 5/13 EMIF03-SIM02M8 Package information 3 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 3.1 Micro QFN 1.7x1.5-8L package information • Epoxy meets UL94, V0 Figure 11. Micro QFN 1.7x1.5-8L package outline DS5513 - Rev 2 page 6/13 EMIF03-SIM02M8 Micro QFN 1.7x1.5-8L package information Table 3. Micro QFN 1.7x1.5-8L package mechanical data Dimensions Millimeters Ref. Min. Typ. Max. A 0.50 0.55 0.60 A1 0.00 0.02 0.05 b 0.15 0.20 0.25 D 1.65 1.70 1.75 D2 0.85 1.00 1.10 E 1.45 1.50 1.55 E2 0.25 0.40 0.50 e 0.35 0.40 0.45 k 0.20 L 0.25 0.30 0.35 Figure 12. Micro QFN 1.7x1.5-8L footprint (dimensions in mm) Figure 13. Marking XX Dot : Pin 1 identification XX : Marking code (cf Table 4: Ordering information) The marking can be rotated by multiples of 90° to differentiate assembly locations DS5513 - Rev 2 page 7/13 EMIF03-SIM02M8 Micro QFN 1.7x1.5-8L package information Figure 14. Tape and reel outline 4.00 ± 0.1 Ø 1.5 ± 0.1 1.75 ± 0.1 2.00 ± 0.05 3.5 ± 0.03 XX 1.70 XX All dimensions in mm XX 1.90 8.0 ± 0.3 0.75 4.00 User direction of unreeling Product marking may be rotated by 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. DS5513 - Rev 2 page 8/13 EMIF03-SIM02M8 Recommendation on PCB assembly 4 Recommendation on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a. Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 15. Stencil opening dimensions L T 2. General design rule a. Stencil thickness (T) = 75 ~ 125 μm b. c. 3. 4.2 Aspect area = L  ×  W ≥ 0.66 2T L  + W Reference design a. Stencil opening thickness: 100 μm b. Stencil opening for central exposed pad: Opening to footprint ratio is 50%. c. Stencil opening for leads: Opening to footprint ratio is 90% Halide-free flux qualification ROL0 according to ANSI/J-STD-004. “No clean” solder paste is recommended. Offers a high tack force to resist component movement during high speed. Solder paste with fine particles: powder particle size is 20-45 μm. Placement 1. 2. 3. 4. 5. 6. DS5513 - Rev 2 Aspect ratio = W T ≥ 1.5 Solder paste 1. 2. 3. 4. 4.3 W Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering Standard tolerance of ±0.05 mm is recommended. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. page 9/13 EMIF03-SIM02M8 PCB design preference 4.4 PCB design preference 1. 2. 4.5 To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. A symmetrical layout is recommended, to avoid any tilt phenomena caused by asymmetrical solder paste due to solder flow away. Reflow profile Figure 16. ST ECOPACK® recommended soldering reflow profile for PCB mounting 250 240-245 °C Temperature (°C) -2 °C/s 2 - 3 °C/s 60 sec (90 max) 200 -3 °C/s 150 -6 °C/s 100 0.9 °C/s 50 Time (s) 0 Note: DS5513 - Rev 2 30 60 90 120 150 180 210 240 270 300 Minimize air convection currents in the reflow oven to avoid component movement. Maximum soldering profile corresponds to the latest IPC/JEDEC J-STD-020. page 10/13 EMIF03-SIM02M8 Ordering information 5 Ordering information Figure 17. Ordering information scheme EMIF yy - xxx zz Mx EMI Filter Number of lines Information xxx = application zz = version Package Mx = Micro QFN x leads Table 4. Ordering information Part number Marking Package Weight Base qty. Delivery mode EMIF03-SIM02M8 HA(1) Micro QFN 4 mg 3000 Tape and reel (7”) 1. The marking can be rotated by multiples of 90° to differentiate assembly locations. DS5513 - Rev 2 page 11/13 EMIF03-SIM02M8 Revision history Table 5. Document revision history DS5513 - Rev 2 Date Version Changes 07-Oct-2007 1 Initial release. 31-Jan-2022 2 Updated Table 3. Micro QFN 1.7x1.5-8L package mechanical data and Figure 13. Marking. Minor text changes. page 12/13 EMIF03-SIM02M8 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS5513 - Rev 2 page 13/13