ESDA14V2SC5

® ESDAxxSC5 ESDAxxSC6 A.S.D. Application Specific Discretes QUAD TRANSIL ARRAY FOR ESD PROTECTION APPLICATIONS Where transient overvoltage protection in ESD sensitive equipment is required, such as : -COMPUTERS - PRINTERS - COMMUNICATION SYSTEMS - GSM HANDSETS AND ACCESSORIES - OTHER TELEPHONE SET FEATURES n n SOT23-5L (SC-59) ESDAxxSC5 FUNCTIONAL DIAGRAM SOT23-5L SOT23-6L (SC-59) ESDAxxSC6 n 4 UNIDIRECTIONAL TRANSIL FUNCTIONS LOW LEAKAGE CURRENT: IR max. < 20 µA at VBR 500 W PEAK PULSE POWER (8/20 µs) DESCRIPTION The ESDAxxSC5 and ESDAxxSC6 are monolithic voltage suppressors designed to protect components which are connected to data and transmission lines against ESD. They clamp the voltage just above the logic level supply for positive transients, and to a diode drop below ground for negative transient. 1 2 3 5 4 BENEFITS High ESD protection level : up to 25 kV High integration Suitable for high density boards SOT23-6L 1 COMPLIES WITH THE FOLLOWING STANDARDS: IEC61000-4-2 : level 4 MIL STD 883C-Method 3015-6 : class3 (human body model) 6 5 4 2 3 March 2000 Ed: 5D 1/7 ESDAxxSC5 / ESDAxxSC6 ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C) Symbol VPP Test conditions ESD discharge - MIL STD 883C - Method 3015-6 IEC61000-4-2 air discharge IEC61000-4-2 contact discharge Peak pulse power (8/20µs) note1 Junction temperature Storage temperature range Lead solder temperature (10 second duration) Operating temperature range Value 25 16 9 500 150 -55 to +150 260 -40 to +125 Unit kV PPP Tj Tstg TL Top W °C °C °C °C note 1 : 300 W for ESDA14V2SC5 AND ESDA14V2SC6 note 2: Evolution of functional parameters is given by curves. ELECTRICAL CHARACTERISTICS (Tamb = 25°C) Symbol VRM VBR VCL IRM IPP Parameter Stand-off voltage Breakdown voltage Clamping voltage Leakage current Peak pulse current Voltage temperature coefficient Capacitance Dynamic resistance Forward voltage drop Slope: 1 Rd I IF VBR V RM VF I RM V αT C Rd VF I PP VBR Types min. @ IR IRM @ VRM max. Rd typ. note 1 αT max. note 2 10 /°C 5 6 10 10 -4 C typ. 0V bias pF 280 190 100 60 VF @ max. IF max. V ESDA5V3SC5 ESDA5V3SC6 ESDA6V1SC5 ESDA6V1SC6 ESDA14V2SC5 ESDA14V2SC6 ESDA25SC6 5.3 6.1 14.2 25 V 5.9 7.2 15.8 30 mA 1 1 1 1 µA 2 20 5 1 V 3 5.25 12 24 mΩ 230 350 650 1000 V 1.25 1.25 1.25 1.2 mA 200 200 200 10 note 1 : Square pulse, Ipp = 15A, tp=2.5µs. note 2 : ∆ VBR = αT* (Tamb -25°C) * VBR (25°C) 2/7 ESDAxxSC5 / ESDAxxSC6 CALCULATION OF THE CLAMPING VOLTAGE USE OF THE DYNAMIC RESISTANCE The ESDA family has been designed to clamp fast spikes like ESD. Generally the PCB designers need to calculate easily the clamping voltage VCL. This is why we give the dynamic resistance in addition to the classical parameters. The voltage across the protection cell can be calculated with the following formula: VCL = VBR + Rd IPP As the value of the dynamic resistance remains stable for a surge duration lower than 20µs, the 2.5µs rectangular surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of Rd. Where Ipp is the peak current through the ESDA cell. DYNAMIC RESISTANCE MEASUREMENT The short duration of the ESD has led us to prefer a more adapted test wave, as below defined, to the classical 8/20µs and 10/1000µs surges. I Ipp 2µs tp = 2.5µs t 2.5µs duration measurement wave. 3/7 ESDAxxSC5 / ESDAxxSC6 Fig. 1: Peak power dissipation versus initial junction temperature. Ppp[Tj initial]/Ppp[Tj initial=25°C] 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 5000 Fig. 2: Peak pulse power versus exponential pulse duration (Tj initial = 25 °C). Ppp(W) ESDA5V3SC5/SC6 & ESDA6V1SC5/SC6 1000 ESDA14V2SC5/SC6 & ESDA25SC6 Tj initial(°C) tp(µs) 0 25 50 75 100 125 150 100 1 10 100 Fig. 3: Clamping voltage versus peak pulse current (Tj initial = 25 °C). Rectangular waveform tp = 2.5 µs. Ipp(A) 50.0 10.0 ESDA25SC5/SC6 ESDA14V2SC5/SC6 ESDA6V1SC5/SC6 ESDA5V3SC5/SC6 Fig. 4: Capacitance versus reverse applied voltage (typical values). C(pF) 500 F=1MHz Vosc=30mV 200 100 50 ESDA5V3SC5/SC6 ESDA6V1SC5/SC6 1.0 ESDA14V2SC5/SC6 tp=2.5µs 20 VR(V) ESDA25SC6 Vcl(V) 0.1 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 10 1 2 5 10 20 50 Fig. 5: Relative variation of leakage current versus junction temperature (typical values). IR[Tj] / IR[Tj=25°C] 200 100 ESDA14V2SC5/SC6 & ESDA6V1SC5/SC6 Fig. 6: Peak forward voltage drop versus peak forward current (typical values). IFM(A) 5.00 1.00 ESDA5V3SC5/SC6 ESDA14V2SC5/SC6 & ESDA6V1SC5/SC6 ESDA25SC6 ESDA25SC6 10 Tj(°C) 1 25 50 75 ESDA5V3SC5/SC6 0.10 VFM(V) 100 125 Tj=25°C 0.01 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4/7 ESDAxxSC5 / ESDAxxSC6 ESD protection by ESDAXXXSCX Electrostatic discharge (ESD) is a major cause of failure in electronic systems. Transient Voltage Suppressors (TVS) are an ideal choice for ESD protection. They are capable of clamping the incoming transient overvoltage to a low enough level such that damage to the protected semiconductor is prevented. Surface mount TVS arrays offer the best choice for minimal lead inductance. They serve as parallel protection elements, connected between the signal line and ground. As the transient rises above the operating voltage of the device, the TVS array becomes a low impedance path diverting the transient current to ground. I/ O LINES ESD sensitive device GND ESDA6V1SC6 (1connection to GND for ESDAxxSC5) The ESDAxxSCx array is the ideal board level protection of ESD sensitive semiconductor components. The tiny SOT23-5L and SOT23-6L packages allow design flexibility in the high density boards where the space saving is at a premium. This enables to shorten the routing and contributes to hardening against ESD. ADVICE FOR OPTIMIZING CIRCUIT BOARD LAYOUT Circuit board layout is a critical design step in the suppression of ESD induced transients. The following guidelines are recommended : n The ESDAxxSC5/6 should be placed as close as possible to the input terminals or connectors. n n n n The path length between the ESD suppressor and the protected line should be minimized All conductive loops, including power and ground loops should be minimized The ESD transient return path to ground should be kept as short as possible. Ground planes should be used whenever possible. 5/7 ESDAxxSC5 / ESDAxxSC6 ORDER CODE ESDA 6V1 SC6 PACKAGE : SC5: SOT23-5L SC6: SOT23-6L ESD ARRAY VBR min MARKING Type ESDA6V1SC5 ESDA6V1SC6 ESDA5V3SC5 Marking EC61 ES61 EC53 MARKING Type ESDA5V3SC6 ESDA14V2SC5 ESDA14V2SC6 ESDA25SC6 Marking ES53 EC15 ES15 ES25 Packaging: Standard packaging is tape and reel. PACKAGE MECHANICAL DATA SOT23-5L A Packaging: Standard packaging is tape and reel. H DIMENSIONS REF. Millimeters Min. Typ. Max. Min. Inches Typ. Max. 0.057 0.006 0.0512 0.02 0.008 0.118 0.0689 0.0374 3.00 0.102 0.60 0.004 10° 0.118 0.024 10° A2 e D A b e 0.90 0 0.90 0.35 0.09 2.80 1.50 0.95 2.60 0.10 1.45 0.035 0.15 0 A1 A2 A1 1.30 0.035 0.50 0.0137 0.20 0.004 3.00 0.11 b c L c M E D E e H 0.65 0.025 1.3 0.051 1.75 0.059 FOOT PRINT L M 3.6 0.137 1 0.040 mm inch 0.95 0.037 6/7 ESDAxxSC5 / ESDAxxSC6 PACKAGE MECHANICAL DATA SOT23-6L A H DIMENSIONS REF. Millimeters Min. Typ. Max. Min. Inches Typ. Max. 0.057 0.006 0.0512 0.02 0.008 0.118 0.0689 0.0374 3.00 0.102 0.60 0.004 10° 0.118 0.024 10° A2 e D b e A A1 A2 A1 0.90 0 0.90 0.35 0.09 2.80 1.50 0.95 2.60 0.10 1.45 0.035 0.15 0 1.30 0.035 0.50 0.0137 0.20 0.004 3.00 0.11 b C L c M E D E e H 1.75 0.059 FOOT PRINT 0.65 0.025 1.3 0.051 L M 3.6 0.137 1 0.040 mm inch 0.95 0.037 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2000 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 7/7