ESDA5V3L

® ESDAxxL DUAL TRANSIL ARRAY FOR ESD PROTECTION Application Specific Discretes A.S.D. APPLICATIONS Where transient overvoltage protection in ESD sensitive equipment is required, such as : - COMPUTERS - PRINTERS - COMMUNICATION SYSTEMS It is particulary recommended for the RS232 I/O port protection where the line interface withstands only with 2kV ESD surges. FEATURES n n SOT23 n 2 UNIDIRECTIONAL TRANSIL FUNCTIONS. LOW LEAKAGE CURRENT : IR max. < 20µA at VBR. 300 W PEAK PULSE POWER (8/20µs) DESCRIPTION The ESDAxxL is a dual monolithic voltage suppressor designed to protect components which are connected to data and transmission lines against ESD. It clamps the voltage just above the logic level supply for positive transients, and to a diode drop below ground for negative transients. It can also work as bidirectionnal suppressor by connecting only pin1 and 2. FUNCTIONAL DIAGRAM BENEFITS High ESD protection level : up to 25 kV. High integration. Suitable for high density boards. COMPLIES WITH THE FOLLOWING STANDARDS : IEC61000-4-2 level 4 MIL STD 883C-Method 3015-6 : class 3. (human body model) Marchr 2000 - Ed: 4A 1/6 ESDAxxL ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C) Symbol VPP Parameter Electrostatic discharge MIL STD 883C - Method 3015-6 IEC61000-4-2 air discharge IEC61000-4-2 contact discharge Peak pulse power (8/20 µs) Storage temperature range Maximum junction temperature Maximum lead temperature for soldering during 10s Operating temperature range Value 25 16 9 300 - 55 to + 150 150 260 - 40 to + 125 W °C °C °C °C Unit kV PPP Tstg Tj TL Top note 1: Evolution of functional parameters is given by curves. ELECTRICAL CHARACTERISTICS (Tamb = 25°C) Symbol VRM VBR VCL IRM IPP Parameter Stand-off voltage Breakdown voltage Clamping voltage Leakage current Peak pulse current Voltage temperature coefficient Capacitance Dynamic resistance Forward voltage drop Slope: 1 Rd I IF VBR V RM VF I RM V αT C Rd VF I PP Types min. VBR @ max. IR IRM max. µA 2 20 5 1 @ VRM Rd typ. note 1 mΩ 280 350 650 1000 αT max. note 2 10 /⊃C -4 C typ. 0V bias pF 220 140 90 50 VF @ max. IF V V 5.9 7.2 15.8 30 mA 1 1 1 1 V 3 5.25 12 24 V 1.25 1.25 1.25 1.2 mA 200 200 200 10 ESDA5V3L ESDA6V1L ESDA14V2L ESDA25L 5.3 6.1 14.2 25 5 6 10 10 note 1 : Square pulse Ipp = 15A, tp=2.5µs. note 2 : ∆ VBR = αT* (Tamb -25°C) * VBR (25°C) 2/6 ESDAxxL CALCULATION OF THE CLAMPING VOLTAGE USE OF THE DYNAMIC RESISTANCE The ESDA family has been designed to clamp fast spikes like ESD. Generally the PCB designers need to calculate easily the clamping voltage VCL. This is why we give the dynamic resistance in addition to the classical parameters. The voltage across the protection cell can be calculated with the following formula: VCL = VBR + Rd IPP Where Ipp is the peak current through the ESDA cell. DYNAMIC RESISTANCE MEASUREMENT The short duration of the ESD has led us to prefer a more adapted test wave, as below defined, to the classical 8/20µs and 10/1000µs surges. I Ipp As the value of the dynamic resistance remains stable for a surge duration lower than 20µs, the 2.5µs rectangular surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of Rd. 2µs tp = 2.5µs t 2.5µs duration measurement wave. 3/6 ESDAxxL Fig. 1: Peak power dissipation versus initial junction temperature. Fig. 2: Peak pulse power versus exponential pulse duration (Tj initial = 25 °C). Ppp[Tj initial]/Ppp[Tj initial=25°C] 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 3000 1000 Ppp(W) 100 Tj initial(°C) 0 25 50 75 100 125 150 10 1 tp(µs) 10 100 Fig. 3: Clamping voltage versus peak pulse current (Tj initial = 25 °C). Rectangular waveform tp = 2.5 µs. Fig. 4: Capacitance versus reverse applied voltage (typical values). Ipp(A) 50.0 10.0 ESDA5V3L C(pF) 200 ESDA6V1L ESDA14V2L ESDA25L ESDA5V3L F=1MHz Vosc=30mV 100 ESDA6V1L 50 1.0 tp=2.5µs ESDA14V2L 20 VR(V) 10 1 2 5 10 20 ESDA25L Vcl(V) 0.1 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 50 Fig. 5: Relative variation of leakage current versus junction temperature (typical values). Fig. 6: Peak forward voltage drop versus peak forward current (typical values). IR[Tj] / IR[Tj=25°C] 200 100 ESDA6V1L & ESDA14V2L IFM(A) 5.00 Tj=25°C ESDA5V3L ESDA14V2L 1.00 ESDA25L ESDA6V1L ESDA25L 10 0.10 Tj(°C) 1 25 50 75 100 ESDA5V3L VFM(V) 125 0.01 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4/6 ESDAxxL 1. ESD protection by the ESDAxxL Electrostatic discharge (ESD) is a major cause of failure in electronic systems. Transient Voltage Suppressors (TVS) are an ideal choice for ESD protection. They are capable of clamping the incoming transient to a low enough level such that damage to the protected semiconductor is prevented. Surface mount TVS arrays offer the best choice for minimal lead inductance. They serve as parallel protection elements, connected between the signal line to ground. As the transient rises above the operating voltage of the device, the TVS array becomes a low impedance path diverting the transient current to ground. The ESDAxxL array is the ideal board level protection of ESD sensitive semiconductor components. The tiny SOT23 package allows design flexibility in the design of high density boards where the space saving is at a premium. This enables to shorten the routing and contributes to hardening againt ESD. I/O I/O I/O I/O ESD sensitive device GND 2 * ESDAXXL 2. Circuit Board Layout Circuit board layout is a critical design step in the suppression of ESD induced transients. The following guidelines are recommended : n The ESDAxxL should be placed as close as possible to the input terminals or connectors. n The path length between the ESD suppressor and the protected line should be minimized n n n All conductive loops, including power and ground loops should be minimized The ESD transient return path to ground should be kept as short as possible. Ground planes should be used whenever possible. 5/6 ESDAxxL ORDER CODE ESDA 6V1 L ESD ARRAY VBR min PACKAGE MECHANICAL DATA SOT23 (Plastic) E A PACKAGE : SOT23 PLASTIC DIMENSIONS REF. Millimeters Min. Max. 1.4 0.1 0.51 0.18 3.04 1.05 2.1 1.6 2.75 0.65 0.89 0 0.3 0.085 2.75 0.85 1.7 1.2 2.1 0.35 Inches Min. 0.035 0 0.012 0.003 0.108 0.033 0.067 0.047 0.083 0.014 Max. 0.055 0.004 0.02 0.007 0.12 0.041 0.083 0.063 0.108 0.026 e B e1 D A A1 B S A1 c D e e1 E H L L H 0.6 typ. 0.024 typ. c S FOOT PRINT (in millimeters) 0.9 0.035 0.9 0.035 1.1 0.043 MARKING TYPE ESDA5V3L ESDA6V1L mm inch MARKING EL53 EL61 EL15 EL25 2.35 0.92 1.9 0.075 1.45 0.037 ESDA14V2L ESDA25L 1.1 0.043 0.9 0.035 Packaging: Standard packaging is tape and reel. Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2000 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 6/6