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ESDA6V1U1RL

ESDA6V1U1RL

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    SOIC8_150MIL

  • 描述:

    用于ESD保护的TRANSIL阵列 SOIC8_150MIL

  • 数据手册
  • 价格&库存
ESDA6V1U1RL 数据手册
® ESDA6V1U1 TRANSIL™ ARRAY FOR ESD PROTECTION Application Specific Discretes A.S.D.™ APPLICATIONS Where transient overvoltage protection in ESD sensitive equipment is required, such as : - COMPUTERS - PRINTERS - COMMUNICATION SYSTEMS - GSM HANDSETS AND ACCESSORIES - CAR RADIO It is particulary recommended for parallel port protection where the line interface withstands only 2 kV ESD surge. SO8 FEATURES 6 UNIDIRECTIONAL TRANSIL™ FUNCTIONS LOW LEAKAGE CURRENT: IR max. < 2 µA 200 W PEAK PULSE POWER (8/20 µs) DESCRITION The ESDA6V1U1 is a monolithic voltage suppressor designed to protect components which are connected to data and transmission lines against ESD. It clamps the voltage just above the logic level supply for positive transients, and to a diode drop below ground for negative transients. BENEFITS High ESD protection level : up to 25 kV High integration Suitable for high density boards COMPLIES WITH THE FOLLOWING STANDARDS : IEC 1000-4-2 : level 4 MIL STD 883C-Method 3015-6 : class3 (human body model) FUNCTIONAL DIAGRAM I/O 1 I/O 2 2 I/O 3 3 I/O 4 4 8 I/O 6 7 GND 6 GND 5 I/O 5 January 1998 - Ed : 2 1/6 ESDA6V1U1 ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C) Symbol VPP PPP Tstg Tj TL Parameter Electrostatic discharge MIL STD 883C - Method 3015-6 Peak pulse power (8/20µs) Storage temperature range Maximum junction temperature Maximum lead temperature for soldering during 10s Value 25 200 - 55 to + 150 125 260 Unit kV W °C °C °C ELECTRICAL CHARACTERISTICS (Tamb = 25°C) Symbol VRM VBR VCL IRM IPP Parameter Stand-off voltage Breakdown voltage Clamping voltage Leakage current Peak pulse current Voltage temperature coefficient Capacitance Dynamic resistance Forward voltage drop αT C Rd VF Types VBR min. @ max. IR IRM @ VRM max. µA 2 Rd typ. note 1 Ω 0.5 αT max. note 2 10-4/°C 6 C typ. 0V bias pF 100 VF @ max. IF V ESDA6V1U1 6.1 V 7.2 mA 1 V 5 V 1.5 mA 200 note 1 : Square pulse, Ipp = 25A, tp=2.5µs. note 2 : ∆ VBR = αT* (Tamb -25°C) * VBR (25°C) 2/6 ESDA6V1U1 CALCULATION OF THE CLAMPING VOLTAGE USE OF THE DYNAMIC RESISTANCE The ESDA family has been designed to clamp fast spikes like ESD. Generally the PCB designers need to calculate easily the clamping voltage VCL. This is why we give the dynamic resistance in addition to the classical parameters. The voltage across the protection cell can be calculated with the following formula: VCL = VBR + Rd IPP Where Ipp is the peak current through the ESDA cell. DYNAMIC RESISTANCE MEASUREMENT The short duration of the ESD has led us to prefer a more adapted test wave, as below defined, to the classical 8/20µs and 10/1000µs surges. I Ipp ESDA6V1U1 As the value of the dynamic resistance remains stable for a surge duration lower than 20µs, the 2.5µs rectangular surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of Rd. 2µs tp = 2.5µs t 2.5µs duration measurement wave. 3/6 ESDA6V1U1 Fig. 1 : Peak power dissipation versus initial junction temperature. Ppp[Tj initial]/Ppp[Tj initial=25°C] 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2000 1000 Fig. 2 : Peak pulse power versus exponential pulse duration (Tj initial = 25 °C). Ppp(W) 100 Tj initial(°C) 0 25 50 75 100 125 150 10 1 tp(µs) 10 100 Fig. 3 : Clamping voltage versus peak pulse current (Tj initial = 25 °C). Rectangular waveform tp = 2.5 µs. Ipp(A) 50.0 tp=2.5µs Fig. 4 : Capacitance versus reverse applied voltage (typical values). C(pF) 100 F=1MHz Vosc=30mV 10.0 50 1.0 20 VCL(V) VR(V) 10 1 2 5 10 0.1 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Fig. 5 : Relative variation of leakage current versus junction temperature (typical values). IR[Tj] / IR[Tj=25°C] 200 100 Fig. 6 : Peak forward voltage drop versus peak forward current (typical values). IFM(A) Tj=25°C 5.00 1.00 10 0.10 Tj(°C) 1 25 50 75 100 125 VFM(V) 0.01 0.0 0.5 1.0 1.5 2.0 2.5 3.0 4/6 ESDA6V1U1 APPLICATION EXAMPLE : Protection of logic-level signals. ESDA6V1U1 D1 0 to 5 V ESDA6V1U1 D2 0 to 5 V Dn 0 to 5 V APPLICATION EXAMPLE : Protection of symmetrical signals. Note : Capacitance value between any I/O pin and Ground is divided by 2. ESDA6V1U1 A1 +/- 2.5 V A2 +/- 2. 5 V A3 +/- 2.5 V A4 +/- 2.5 V 5/6 ESDA6V1U1 ORDER CODE ESDA 6 V 1 U 1 RL PACKAGING: RL = Tape and reel = Tube PACKAGE: SO8 PLASTIC ESD ARRAY VBR min Unidirectionel MARKING : Logo, Date Code, E6VU1 PACKAGE MECHANICAL DATA SO8 Plastic DIMENSIONS REF. A a1 a2 b b1 C c1 D E e e3 F L M S Packaging : Preferred packaging is tape and reel. Weight : 0.08g. Millimetres Min. 0.1 0.35 0.19 0.50 4.8 5.8 1.27 3.81 3.8 0.4 4.0 0.15 1.27 0.016 0.6 8° (max) 45° (typ) 5.0 0.189 6.2 0.228 0.050 0.150 0.157 0.050 0.024 Typ. Max. Min. 1.75 0.25 0.004 1.65 0.48 0.014 0.25 0.007 0.020 0.197 0.244 Inches Typ. Max. 0.069 0.010 0.065 0.019 0.010 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © 1998 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 6/6
ESDA6V1U1RL 价格&库存

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ESDA6V1U1RL
  •  国内价格
  • 1+0.95000

库存:0