ESDA7P120-1U1M
High power transient voltage suppressor
Datasheet - production data
Applications
Where transient overvoltage protection in ESD
sensitive equipment is required, such as:
n1
Pi
n2
Pi
1610 package
Description
The ESDA7P120-1U1M is a unidirectional single
line TVS diode designed to protect the power line
against EOS and ESD transients.
Features
The device is ideal for applications where high
power TVS and board space saving is required.
Low clamping voltage
Peak pulse power: 1400 W (8/20 µs)
Stand-off voltage 5.5 V
Unidirectional diode
Low leakage current: 1.5 µA at 25 °C
Complies with IEC 61000-4-2 level 4
±30 kV (air discharge)
±30 kV (contact discharge)
July 2017
DocID030241 Rev 3
This is information on a product in full production.
Pin2
Figure 1: Pin configuration
Pin1
Smartphones, mobile phones, tablets,
portable multimedia
USB VBUS protection
Power supply protection
Battery protection
1/9
www.st.com
Characteristics
1
ESDA7P120-1U1M
Characteristics
Table 1: Absolute maximum ratings (Tamb = 25 °C)
Symbol
Parameter
Value
Unit
VPP
Peak pulse voltage
IEC 61000-4-2:
Contact discharge
Air discharge
>30
>30
kV
PPP
Peak pulse power
8/20μs
1400
W
IPP
Peak pulse current
8/20μs
120
A
Tstg
Storage junction temperature range
-55 to +150
Top
Operating junction temperature range
-55 to +150
°C
Figure 2: Electrical characteristics (definitions)
Table 2: Electrical characteristics (Tamb = 25 °C)
Symbol
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Test condition
Min.
Typ.
6.4
6.8
Max.
Unit
VBR
IR = 1 mA
IRM
VRM = 5 V
350
nA
V
IRM
VRM = 5.5 V
1.5
µA
Rd
8/20 µs
VCL
IPP = 80 A, 8/20 µs
9.5
10.0
V
VCL
IPP = 100 A, 8/20 µs
10.2
10.7
V
VCL
IPP = 120 A, 8/20 µs
11
11.5
V
Ω
0.035
DocID030241 Rev 3
Characteristics
ESDA7P120-1U1M
Figure 3: Peak power dissipation versus initial
temperature (typical value)
Figure 4: Peak pulse power versus exponential
pulse duration (typical value)
PPP(W)
P PP(W)
2000
8/20 µs
typical value
1800
10000
Tj initial = 25 °C
typical value
1600
1400
1000
1200
1000
800
100
600
400
tp(µs)
200
Tj (°C)
0
20
40
60
80
10
10
100
120
140
Figure 5: Peak pulse current versus clamping
voltage (maximum value)
1,000.0
100
1000
160
Figure 6: Leakage current versus junction
temperature (typical value)
IPP(A)
Ir (nA)
3000
8/20 µs
Tj initial = 25 °C
2500
100.0
VR = 5.5 V
2000
Reverse typical value
1500
10.0
1000
1.0
VR = 5 V
500
VCL (V)
0.1
6
7
8
9
10
11
0
25
12
150
80
tj (°C)
Figure 7: ESD response to IEC 61000-4-2
(+8kV contact discharge)
5 V/div
5 V/div
25.4
Figure 8: ESD response to IEC 61000-4-2
(-8kV contact discharge)
V1
7.7 V 2
1 V PP : ESD peak voltage
2 V CL : Clamping voltage @ 30 ns
3 V CL : Clamping voltage @ 60 ns
4 V CL : Clamping voltage @ 100 ns
8V
3
6.9 V
-1.2 V 2
4
-23.5 V 1
-1.6 V 3
-0.997 V
4
1 V PP : ESD peak voltage
2 V CL : Clamping voltage @ 30 ns
3 V CL : Clamping voltage @ 60 ns
4 V CL : Clamping voltage @ 100 ns
20 ns/div
20 ns/div
DocID030241 Rev 3
3/9
Package information
2
ESDA7P120-1U1M
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
2.1
QFN 1610 package information
Figure 9: QFN 1610 package outline
E
D
A
Top view
A1
Side view
b
e
L
Bottom view
Table 3: QFN 1610 package mechanical data
Dimensions
Ref.
A
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
0.51
0.55
0.60
0.0201
0.0217
0.0236
0.02
0.05
0.0008
0.0020
0.80
0.85
0.0315
0.0335
A1
b
0.75
0.0295
D
1.60
0.0630
E
1.00
0.0394
e
1.05
0.0413
L
4/9
Inches
0.30
0.35
0.40
DocID030241 Rev 3
0.011
0.013
0.015
Package information
ESDA7P120-1U1M
Figure 10: Footprint recommendations
Figure 11: Alternative footprint dimensions
Figure 12: Marking
E
Pin2
Pin1
Product marking may be rotated by multiples of 90° for assembly plant
differentiation. In no case should this product marking be used to orient the
component for its placement on a PCB. Only pin 1 mark is to be used for this
purpose.
Figure 13: Tape and reel specification (in mm)
2.0 ±0.05
Ø 1.50 +0.10
4.0 ±0.10
1.75 ±0.10
Bar indicates Pin1
E
E
E
3.50 ±0.05
1.14 ±0.03
0.67 ±0.05
E
E
E
E
8.0 ±0.10
1.75 ±0.03
0.20 ±0.02
2.0 ±0.10
All dimensions are typical values in mm
User direction of unreeling
DocID030241 Rev 3
5/9
PCB recommendation
ESDA7P120-1U1M
3
PCB recommendation
3.1
Stencil opening
1.
2.
General recommendation on stencil opening design
a. Stencil opening dimensions: L (Length), W (Width), T (Thickness).
General design rule
a. Stencil thickness (T) = 75 ~ 125 μm
𝑊
b. Aspect ratio = ≥ 1.5
𝑇
c.
3.
Aspect area =
𝐿×𝑊
2𝑇(𝐿+𝑊)
≥ 0.66
Reference design
a. Stencil opening thickness: 100 μm
b. Stencil opening for leads: Opening to footprint ratio is 90%.
Figure 14: Stencil opening dimensions
Figure 15: Recommended stencil window position
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Figure 16: Alternative stencil window position
DocID030241 Rev 3
PCB recommendation
ESDA7P120-1U1M
3.2
Solder paste
1.
2.
3.
4.
3.3
Placement
1.
2.
3.
4.
5.
6.
3.4
Manual positioning is not recommended.
It is recommended to use the lead recognition capabilities of the placement system,
not the outline centering
Standard tolerance of ±0.05 mm is recommended.
3.5 N placement force is recommended. Too much placement force can lead to
squeezed out solder paste and cause solder joints to short. Too low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages.
To improve the package placement accuracy, a bottom side optical control should be
performed with a high resolution tool.
For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is
recommended during solder paste printing, pick and place and reflow soldering by
using optimized tools.
PCB design preference
1.
2.
3.5
Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004.
“No clean” solder paste is recommended.
Offers a high tack force to resist component movement during PCB movement.
Solder paste with fine particles: powder particle size is 20-45 μm.
To control the solder paste amount, the closed via is recommended instead of open
vias.
The position of tracks and open vias in the solder area should be well balanced. A
symmetrical layout is recommended, to avoid any tilt phenomena caused by
asymmetrical solder paste due to solder flow away.
Reflow
Figure 17: ST ECOPACK® recommended soldering reflow profile for PCB mounting
Minimize air convection currents in the reflow oven to avoid component
movement.
DocID030241 Rev 3
7/9
Ordering information
4
ESDA7P120-1U1M
Ordering information
Figure 18: Ordering information scheme
ESDA
7 P120 - 1U1 M
ESD Array
Breakdown voltage
7 = 7 V typ.
IPP 8/20 µs
P120 = 120 A
Direction
1U1 = Unidirectional
Package
M = QFN
Table 4: Ordering information
Order code
Marking(1)
Package
Weight
Base qty.
Delivery mode
ESDA7P120-1U1M
E
QFN 1610
2.4 mg
8000
Tape and reel
Notes:
(1)The
5
marking can be rotated by multiples of 90° to differentiate assembly location
Revision history
Table 5: Document revision history
8/9
Date
Revision
Changes
18-Jan-2017
1
Initial release.
09-Feb-2017
2
Updated Figure 1: "Pin configuration".
10-Jul-2017
3
Updated Table 3: "QFN 1610 package mechanical data".
DocID030241 Rev 3
ESDA7P120-1U1M
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
DocID030241 Rev 3
9/9
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