ESDA9P25-1T2

ESDA9P25-1T2 Datasheet 7.9 V, 24 A unidirectional TVS in SOD882T Features n1 Pi n2 Pi Pin2 Pin1 SOD882T package Pin configuration Product status link ESDA9P25-1T2 • • • • • • Low clamping voltage Unidirectional diode Low leakage current SOD882T (0402) package ECOPACK2 compliant component Exceeds the IEC 61000-4-2 level 4 standard: – ± 30 kV (air discharge) – ± 30 kV (contact discharge) Application Where transient over voltage protection in ESD sensitive equipment is required, such as: • Smartphones, mobile phones, and accessories • Tablets and notebooks • Portable multimedia devices and accessories • Wearable, home automation, healthcare • Highly integrated systems Description The ESDA9P25-1T2 is a unidirectional single line TVS diode designed to protect the power line or other low speed I/O against ESD and small surge transients. The device is ideal for applications where high power TVS and board space saving are required. DS13449 - Rev 2 - February 2024 For further information contact your local STMicroelectronics sales office. www.st.com ESDA9P25-1T2 Characteristics 1 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter Value IEC 61000-4-2 contact discharge 30 IEC 61000-4-2 air discharge 30 Unit Vpp Peak pulse voltage Ppp Peak pulse power (8/20 μs) 300 W Ipp Peak pulse current (8/20 μs) 24 A Top Operating junction temperature range -55 to 150 °C Tstg Storage junction temperature range -55 to 150 °C 260 °C TL Maximum lead temperature for soldering during 10 s kV Figure 1. Electrical characteristics (definitions) I Symbol VBR VCL IRM VRM IPP = = = = = Parameter Breakdown voltage Clamping voltage Leakage current @ V RM Stand-off voltage Peak pulse current RD IR = = Dynamic resistance Breakdown current VCL V BR VRM V I RM IR Slope = 1/ R d I PP Table 2. Electrical characteristics (values) (Tamb = 25° C) Symbol Test conditions Min. Max. Unit 7.9 V 15 250 nA 8.7 9.2 V IPP = 20 A 8/20µs 12.3 13.5 IPP = 24 A 8/20µs 13.7 14.5 VRM Stand-off voltage IRM Leakage current VRM = 7.9 V VBR Breakdown voltage IR = 1 mA VCL Reverse clamping voltage TLP 16 A RD CLINE DS13449 - Rev 2 Dynamic resistance Line capacitance 8.1 Typ. V 10 8/20 µs waveform 0.18 TLP – Pulse duration 100 ns 0.09 VLINE = 0 V, F = 1 MHz 130 Ω pF page 2/11 ESDA9P25-1T2 Characteristics 1.1 Characteristics (curves) Figure 2. Peak pulse power dissipation versus initial junction temperature (typical value) PPP (W) 400 Figure 3. Peak pulse power versus exponential pulse duration (maximum values) PPP (W) 1000 Tj initial = 25 °C 8/20 µs 350 300 250 200 100 150 100 50 Tj (°C) 0 25 50 75 100 125 150 tp (µs) 175 10 20 Figure 4. Peak pulse current versus clamping voltage (maximum value) Figure 5. Leakage current versus junction temperature (typical value) I PP (A) 8/20 µs 200 100 Ir(nA) VR = VRM 10 10 1 0.1 Tj(°C) V CL (V) 1 25 5 6 7 8 9 10 11 12 13 14 Figure 6. ESD response to IEC 61000-4-2 (+8kV contact discharge) DS13449 - Rev 2 50 75 100 125 150 15 Figure 7. ESD response to IEC 61000-4-2 (-8kV contact discharge) page 3/11 ESDA9P25-1T2 Package information 2 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 2.1 SOD882T package information Figure 8. SOD882T package outline Table 3. SOD882T package mechanical data Dimensions Millimeters Ref. Min. Max. A 0.30 A1 0.00 0.02 0.05 L 0.45 0.50 0.55 0.40 D 1.00 E 0.60 e 0.65 b DS13449 - Rev 2 Typ. 0.20 0.25 0.30 page 4/11 ESDA9P25-1T2 Package information Figure 9. SOD882T recommended footprint 0 .4 0 . 55 0 .5 0 . 55 1 .5 Figure 10. Marking Pin2 Note: DS13449 - Rev 2 P Pin1 The marking can be rotated by multiples of 90° to differentiate assemble location. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. page 5/11 ESDA9P25-1T2 Package information Figure 11. Tape and reel specification Indicates Pin1 2.0 Ø 1.50 4.0 0.67 P P P P P E P P 8.0 1.75 3.50 1.75 0.20 2.0 1.14 All dimensions are typical values in mm User direction of unreeling DS13449 - Rev 2 page 6/11 ESDA9P25-1T2 Recommendation on PCB assembly 3 Recommendation on PCB assembly 3.1 Stencil opening design 1. General recommendation on stencil opening design a. Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 12. Stencil opening recommendation L T W b. General design rule ◦ Stencil thickness (T) = 75 ~ 125 μm ◦ W T ◦ ≥ 1.5 L  ×  W 2T L  + W ≥ 0.66 1. Reference design a. Stencil opening thickness: 100 µm b. Stencil opening for leads: Opening to footprint ratio is 90% Figure 13. Recommended stencil window position in mm 0.52mm 0.43mm 0.52mm 0.015mm 0.015mm Footprint DS13449 - Rev 2 0.47mm 1.47mm Stencil window page 7/11 ESDA9P25-1T2 Recommendation on PCB assembly 3.2 Solder paste 1. 2. 3. 4. 3.3 Halide-free flux qualification ROL0 according to ANSI/J-STD-004. “No clean” solder paste is recommended. Offers a high tack force to resist component movement during high speed. Use solder paste with fine particles: powder particle size 20-45 µm. Placement 1. 2. 3. 4. Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering Standard tolerance of ±0.05 mm is recommended. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 3.4 PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. A symmetrical layout is recommended, to avoid any tilt phenomena caused by asymmetrical solder paste due to solder flow away. 3.5 Reflow profile Figure 14. ST ECOPACK recommended soldering reflow profile for PCB mounting 250 240-245 °C Temperature (°C) -2 °C/s 2 - 3 °C/s 60 sec (90 max) 200 -3 °C/s 150 -6 °C/s 100 0.9 °C/s 50 Time (s) 0 Note: DS13449 - Rev 2 30 60 90 120 150 180 210 240 270 300 Minimize air convection currents in the reflow oven to avoid component movement. page 8/11 ESDA9P25-1T2 Ordering information 4 Ordering information Figure 15. Ordering information scheme ESDA 9 P25 - 1 T2 ESD Array Breakdown voltage 9 = 9 V typ. IPP 8/20 µs P25 = 24 A Direction 1 = 1 unidirectional line Package T2 = Thin SOD882 Table 4. Ordering information Order code Marking(1) Package Weight Base qty. Delivery mode ESDA9P25-1T2 P SOD882T (0402) 0.76 mg 12000 Tape and reel 1. The marking can be rotated by multiples of 90° to differentiate assembly location. DS13449 - Rev 2 page 9/11 ESDA9P25-1T2 Ordering information Revision history Table 5. Document revision history DS13449 - Rev 2 Date Revision Changes 15-Sep-2020 1 First issue. 06-Feb-2024 2 Updated Table 2. page 10/11 ESDA9P25-1T2 Ordering information IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2024 STMicroelectronics – All rights reserved DS13449 - Rev 2 page 11/11