ESDALC14-1BU2

ESDALC14-1BU2 Datasheet Low clamping and low capacitance bidirectional single line ESD protection Features 0201 package • Low clamping voltage VCL = 18 V • • • • • • Bidirectional device Low leakage current 0201 package Ultra-low PCB area: 0.18 mm2 ECOPACK2 compliant Exceeds IEC 61000-4-2 level 4 standard: – ±25 kV (air discharge) – ±20 kV (contact discharge) Applications Where transient over voltage protection in ESD sensitive equipment is required, such as: • Smartphones, mobile phones and accessories • Tablets and notebooks • Portable multimedia devices and accessories • Wearable, home automation, healthcare • Highly integrated systems Product status link Description ESDALC14-1BU2 The ESDALC14-1BU2 is a bidirectional single line TVS diode designed to protect the data line or other I/O ports against ESD transients. Product summary The device is ideal for applications where both reduced line capacitance and board space saving are required. Order code ESDALC14-1BU2 Package ST0201 Packing Tape and reel DS12761 - Rev 2 - March 2020 For further information contact your local STMicroelectronics sales office. www.st.com ESDALC14-1BU2 Characteristics 1 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter IEC 61000-4-2 contact discharge 20 IEC 61000-4-2 air discharge 25 VPP Peak pulse voltage PPP Peak pulse power dissipation (8/20 μs) IPP Peak pulse current (8/20 μs) Tj Tstg TL Value Unit kV 100 W 5 A Maximum operating junction temperature range -55 to +150 °C Storage temperature range -65 to +150 °C 260 °C Maximum lead temperature for soldering during 10 s Figure 1. Electrical characteristics (definitions) Table 2. Electrical characteristics (Tamb = 25 °C) Symbol Min. Typ. Max. Unit VBR IR = 1 mA VRM Stand-off voltage 12 V IRM VRM = 12 V 100 nA VCL 8 kV contact discharge after 30 ns, IEC 61000-4-2 VCL RD CLINE DS12761 - Rev 2 Test condition 13 V 18 V 8/20 µs waveform, IPP = 5 A 19.5 V TLP - Pulse duration 100 ns - IPP [1A – 16A] 0.25 Ω F = 1 MHz, VLINE = 0 V, VOSC = 30 mV 22 25 pF page 2/10 ESDALC14-1BU2 Characteristics (curves) 1.1 Characteristics (curves) Figure 2. Leakage current versus junction temperature (typical values) 30 IR(nA) 100 Figure 3. Junction capacitance versus applied voltage (typical values) VR = VRM = 12V IO/IO C(pF) Tj = 25 ° C F = 1 MHz Vosc = 30 mV IO/IO 25 20 10 15 1 10 5 Tj(°C) 0.1 25 50 75 100 125 150 VR(V) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 Figure 4. ESD response to IEC 61000-4-2 (+8 kV contact discharge) Figure 5. ESD response to IEC 61000-4-2 (-8 kV contact discharge) Figure 6. Positive TLP characteristic Figure 7. S21 attenuation measurement result 20 Current (A) 18 16 14 12 10 8 6 4 2 Voltage (V) 0 0 DS12761 - Rev 2 5 10 15 20 page 3/10 ESDALC14-1BU2 Package information 2 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 2.1 ST0201 package information Figure 8. ST0201 package outline D E Top A Side fD D1 fE E1 Bottom DS12761 - Rev 2 b page 4/10 ESDALC14-1BU2 ST0201 package information Note: The marking codes can be rotated by 90 ° or 180° to differentiate assembly location. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Table 3. ST0201 package mechanical data Dimensions Ref. Millimeters Min. Typ. Max. A 0.210 0.240 0.270 b 0.110 0.140 0.170 D 0.580 0.610 0.640 D1 0.350 E 0.280 0.310 0.340 E1 0.160 0.190 0.220 fD 0.060 fE 0.060 Figure 9. Tape and reel specification (in mm) Dot indicates Pin 1 4.0 ±0.1 Ø 1.5 ±0.1 1.75 ±0.1 2.0 ±0.05 0.29 ±0.03 3.5 ±0.05 0.67 ±0.03 8.0 +0.03 -0.01 0.2 ±0.02 0.37 ±0.03 2.0 ±0.05 All dimensions in mm DS12761 - Rev 2 User direction of unreeling page 5/10 ESDALC14-1BU2 Recommendation on PCB assembly 3 Recommendation on PCB assembly 3.1 Footprint 1. Footprint in mm a. SMD footprint design is recommended. Figure 10. Footprint in mm 0.150 0.225 0.187 Solder mask opening 3.2 Stencil opening design 1. Reference design a. Stencil opening thickness: 75 μm / 3 mils Figure 11. Recommended stencil window position in mm 0.167 0.210 0.170 Stencil apertures 3.3 Solder paste 1. 2. 3. 4. DS12761 - Rev 2 Halide-free flux qualification ROL0 according to ANSI/J-STD-004. “No clean” solder paste is recommended. Offers a high tack force to resist component movement during high speed. Use solder paste with fine particles: powder particle size 20-38 µm. page 6/10 ESDALC14-1BU2 Placement 3.4 Placement 1. 2. 3. 4. 5. 6. 3.5 PCB design preference 1. 2. 3.6 Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering Standard tolerance of ±0.05 mm is recommended. 1.0 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. A symmetrical layout is recommended, to avoid any tilt phenomena caused by asymmetrical solder paste due to solder flow away. Reflow profile Figure 12. ST ECOPACK recommended soldering reflow profile for PCB mounting 250 240-245 °C Temperature (°C) -2 °C/s 2 - 3 °C/s 60 sec (90 max) 200 -3 °C/s 150 -6 °C/s 100 0.9 °C/s 50 Time (s) 0 Note: DS12761 - Rev 2 30 60 90 120 150 180 210 240 270 300 Minimize air convection currents in the reflow oven to avoid component movement. Maximum soldering profile corresponds to the latest IPC/JEDEC J-STD-020. page 7/10 ESDALC14-1BU2 Ordering information 4 Ordering information Table 4. Ordering information Order code Marking Package Weight Base qty. Delivery mode ESDALC14-1BU2 V(1) ST0201 0.120 mg 15000 Tape and reel 1. The marking can be rotated by multiples of 90° to differentiate assembly location DS12761 - Rev 2 page 8/10 ESDALC14-1BU2 Revision history Table 5. Document revision history DS12761 - Rev 2 Date Version Changes 07-Sep-2018 1 Initial release. 26-Mar-2020 2 Updated Figure 8 and Table 3. page 9/10 ESDALC14-1BU2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DS12761 - Rev 2 page 10/10