ESDALC5-1BF4

ESDALC5-1BF4 Low clamping and low capacitance bidirectional single line ESD protection Datasheet - production data Description The ESDALC5-1BF4 is a bidirectional single line TVS diode designed to protect the data line or other I/O ports against ESD transients. The device is ideal for applications where both reduced line capacitance and board space saving are required. Figure 1: Functional diagram 0201 package Features        Low clamping voltage Bidirectional device Low leakage current 0201 package Ultra low PCB area: 0.18 mm2 ECOPACK®2 compliant component Exceeds the following standard:  IEC 61000-4-2 level 4 = ±15 kV (air discharge) and ±8 kV (contact discharge) Applications Where transient over voltage protection in ESD sensitive equipment is required, such as:      Smartphones, mobile phones and accessories Tablets and notebooks Portable multimedia devices and accessories Wearable, home automation, healthcare Highly integrated systems February 2018 DocID024341 Rev 3 This is information on a product in full production. 1/9 www.st.com Characteristics 1 ESDALC5-1BF4 Characteristics Table 1: Absolute maximum ratings Symbol Parameter Contact discharge Air discharge Value Unit 16 30 kV 28 W VPP Peak pulse voltage PPP Peak pulse power dissipation (8/20 μs) IPP Peak pulse current (8/20 μs) 2.5 A Tj Operating junction temperature range -40 to +150 °C Tstg Storage temperature range -65 to +150 °C TL Maximum lead temperature for soldering during 10 s 260 °C Figure 2: Electrical characteristics (definitions) Table 2: Electrical characteristics (Tamb = 25 °C) Symbol VBR IR = 1 mA IRM VRM = 5 V CLINE 2/9 Parameter Min. Typ. Max. 5.8 F = 1 MHz, VLINE = 0 V, VOSC = 30 mV DocID024341 Rev 3 Unit V 10 100 nA 12 pF ESDALC5-1BF4 Characteristics Figure 3: Leakage current versus junction temperature (typical values) Figure 4: Junction capacitance versus reverse voltage applied (typical values) IR ( nA) 100 C (pF ) VR = VRM = 5 V Tj = 25°C F = 1 MHz VOSC = 30 mV 10 1 VR(V) Tj (°C) 0.1 25 50 75 100 125 150 Figure 5: ESD response to IEC 61000-4-2 (+8 kV contact discharge) Figure 6: ESD response to IEC 61000-4-2 (-8 kV contact discharge) 5 V/div 5 V/div 30 V 1 1 2 3 4 14 V 2 Peak clamping voltage Clamping voltage at 30 ns Clamping voltage at 60 ns Clamping voltage at 100 ns 12 V 10 V 3 4 4 3 2 --13 V -15 V -10 V 1 2 3 4 Peak clamping voltage Clamping voltage at 30 ns Clamping voltage at 60 ns Clamping voltage at 100 ns 20 ns/div 1 -31 V 20 ns/div Figure 7: TLP characteristic Figure 8: S21 attenuation measurement result IPP (A) 0 30 S21 (dB) -3 25 -6 20 -12 -9 -15 -18 15 -21 -24 10 -27 -30 5 -33 VCL (V) f (Hz) -36 0 100k 0 5 10 15 20 DocID024341 Rev 3 1M 10M 100M 1G 10G ESDALC5-1BF4 3/9 Package information 2 ESDALC5-1BF4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 2.1 0201 package information Figure 9: 0201 package outline The marking codes can be rotated by 90° or 180° to differentiate assembly location. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. 4/9 DocID024341 Rev 3 Package information ESDALC5-1BF4 Table 3: 0201 package mechanical data Dimensions Ref. Millimeters Typ. Min. Max. A 0.280 0.300 0.320 b 0.125 0.140 0.155 D 0.570 0.600 0.630 D1 0.350 E 0.270 0.300 0.330 E1 0.175 0.190 0.205 fD 0.110 0.125 0.140 fE 0.040 0.055 0.070 C Figure 10: Marking Pin1 Pin2 The marking codes can be rotated by 90° or 180° to differentiate assembly location. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Figure 11: Tape and reel specification (in mm) 2.0 ± 0.05 Ø 1.5 ± 0.1 4.0 ± 0.1 3.5 ± 0.05 0.68 ± 0.03 8.0 + 0.03 - 0.01 0.22 C 0.36 ± 0.03 1.75 ± 0.1 Bar indicates Pin 1 C C C C C C 0.38 ± 0.03 2.0 ± 0.05 All dimensions in mm User direction of unreeling DocID024341 Rev 3 5/9 Recommendation on PCB assembly ESDALC5-1BF4 3 Recommendation on PCB assembly 3.1 Footprint Figure 12: Footprint (dimensions in mm) 1. 3.2 SMD footprint design is recommended. Stencil opening design 1. Recommended design reference a. Stencil opening thickness: 75 μm / 3 mils Figure 13: Recommended stencil window position in mm (inches) 3.3 Solder paste 1. 2. 3. 4. 6/9 Halide-free flux qualification ROL0 according to ANSI/J-STD-004. “No clean” solder paste is recommended. Offers a high tack force to resist component movement during high speed. Use solder paste with particle size 20-38 µm DocID024341 Rev 3 Recommendation on PCB assembly ESDALC5-1BF4 3.4 Placement 1. 2. 3. 4. 5. 6. 3.5 PCB design preference 1. 2. 3.6 Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering Standard tolerance of ±0.05 mm is recommended. 1.0 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. A symmetrical layout is recommended, to avoid any tilt phenomena caused by asymmetrical solder paste due to solder flow away. Reflow profile Figure 14: ST ECOPACK® recommended soldering reflow profile for PCB mounting Minimize air convection currents in the reflow oven to avoid component movement. DocID024341 Rev 3 7/9 Ordering information 4 ESDALC5-1BF4 Ordering information Figure 15: Ordering information scheme ESDA LC 5 - 1 B F4 ESD array Low Capacitance Breakdown voltage Number of lines B = Bi-directional Package F4 = 0201 Table 4: Ordering information Order code Marking Package Weight Base qty. Delivery mode ESDALC5-1BF4 C(1) 0201 0.116 mg 15000 Tape and reel Notes: (1)The 5 marking can be rotated by multiples of 90° to differentiate assembly location. Revision history Table 5: Document revision history 8/9 Date Revision Changes 06-Feb-2014 1 01-Jun-2017 2 First issue. Updated Table 3: "0201 package mechanical data". Updated Section 3.2: "Stencil opening design". 08-Feb-2018 3 Updated Table 2: "Electrical characteristics (Tamb = 25 °C)". DocID024341 Rev 3 ESDALC5-1BF4 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DocID024341 Rev 3 9/9